Integrated Digital CCIR-601 to PAL/NTSC Video Encoder ADV7177/ADV7178 FEATURES ITU-R BT601/656 YCrCb to PAL/NTSC video encoder Color-signal control/burst-signal control High quality, 9-bit video DACs Interlaced/noninterlaced operation Integral nonlinearity <1 LSB at 9 bits Complete on-chip video timing generator NTSC-M, PAL-M/N, PAL-B/D/G/H/I OSD support (ADV7177 only) Single 27 MHz crystal/clock required (±2 oversampling) Programmable multimode master/slave operation 75 dB video SNR Macrovision AntiTaping Rev. 7.01 (ADV7178 only)1 32-bit direct digital synthesizer for color subcarrier Closed captioning support Multistandard video output support: On-board voltage reference Composite (CVBS) 2-wire serial MPU interface (I2C®-compatible) Component S-video (Y/C) Single-supply 5 V or 3 V operation Component YUV or RGB Small 44-lead MQFP package Video input data port supports: CCIR-656 4:2:2 8-bit parallel input format Synchronous 27 MHz/13.5 MHz clock output 4:2:2 16-bit parallel input format Full video output drive or low signal drive capability APPLICATIONS 34.7 mA max into 37.5 Ω (doubly terminated 75 R) MPEG-1 and MPEG-2 video, DVD, digital satellite, 5 mA min with external buffers cable systems (set-top boxes/IRDs), digital TVs, Programmable simultaneous composite and S-VHS CD video/karaoke, video games, PC video/multimedia (VHS) Y/C or RGB (SCART)/YUV video outputs Programmable luma filters (low-pass/notch/extended) 1 The Macrovision anticopy process is licensed for noncommercial home use Programmable VBI (vertical blanking interval) only, which is its sole intended use in the device. Please contact sales office Programmable subcarrier frequency and phase for latest Macrovision version available. ITU-R and CCIR are used inter- changeably in this document (ITU-R has replaced CCIR recommendations). Programmable luma delay Individual on/off control of each DAC CCIR and square pixel operation FUNCTIONAL BLOCK DIAGRAM VAA ADV7177 ADV7177/ADV7178 9 9BIT DAC A ONLY DAC (PIN 31) YUV TO 9 9BIT DAC B OSD_EN RBG DAC (PIN 27) OSD_0 MATRIX OSD_1 9 9BIT DAC C Y MULTIPLEXER DAC (PIN 26) OSD_2 8 8 ADD 8 INTER 8 LOWPASS 9 SYNC POLATOR FILTER COLOR 4:2:2 TO YCrCb DATA U 4:4:4 8 TO 8 ADD 8 INTER 8 9 LOWPASS P7–P0 INTER YUV BURST POLATOR FILTER POLATOR MATRIX 8 8 ADD 8 INTER 8 V 9 P15–P8 BURST POLATOR LOWPASS FILTER HSYNC 9 9 VOLTAGE VREF VIDEO TIMING FIELD/VSYNC REFERENCE R GENERATOR I2C MPU PORT SIN/COS SET BLANK DDS BLOCK CIRCUIT COMP CLOCK CLOCK CLOCK/2 RESET SCLOCK SDATA ALSB GND 00228-001 Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com registered trademarks are the property of their respective owners. Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADV7177/ADV7178 TABLE OF CONTENTS General Description......................................................................... 4 Closed Captioning Even Field Data Register 1–0 (CED15– CED0).......................................................................................... 29 Specifications..................................................................................... 5 Closed Captioning Odd Field Data Register 1–0 (CCD15– 5 V Specifications......................................................................... 5 CCD0).......................................................................................... 29 3.3 V Specifications...................................................................... 6 Timing Register 1 (TR17–TR10) ............................................. 30 5 V Dynamic Specifications........................................................ 7 TR1 Bit Description................................................................... 30 3.3 V Dynamic Specifications..................................................... 8 Mode Register 2 MR2 (MR27–MR20).................................... 30 5 V Timing Specifications........................................................... 9 MR2 Bit Description.................................................................. 31 3.3 V Timing Specifications...................................................... 10 NTSC Pedestal Registers 3–0 PCE15–0, PCO15–0............... 31 Absolute Maximum Ratings.......................................................... 12 Mode Register 3 MR3 (MR37–MR30).................................... 31 Stress Ratings .............................................................................. 12 MR3 Bit Description.................................................................. 31 Package Thermal Performance................................................. 12 OSD Register 0–11..................................................................... 32 ESD Caution................................................................................ 12 Board Design and Layout Considerations .................................. 33 Pin Configuration and Function Descriptions........................... 13 Ground Planes ............................................................................ 33 Typical Performance Characteristics ........................................... 14 Power Planes ............................................................................... 33 Theory of Operation ...................................................................... 16 Supply Decoupling..................................................................... 33 Data Path Description ............................................................... 16 Digital Signal Interconnect....................................................... 33 Pixel Timing Description .......................................................... 16 Analog Signal Interconnect ...................................................... 33 Video Timing Description ........................................................ 17 Closed Captioning.......................................................................... 35 Timing and Control ................................................................... 18 Waveform Illustrations .................................................................. 36 Power-On Reset.......................................................................... 25 NTSC Waveforms With Pedestal ............................................. 36 MPU Port Description............................................................... 25 NTSC Waveforms Without Pedestal ....................................... 37 Registers........................................................................................... 27 PAL Waveforms.......................................................................... 38 Register Access............................................................................ 27 UV Waveforms ........................................................................... 39 Register Programming............................................................... 27 Register Values................................................................................ 40 Mode Register 0 MR0 (MR07–MR00).................................... 27 NTSC (FSC = 3.5795454 MHZ) ............................................... 40 MR0 Bit Description.................................................................. 27 PAL B, D, G, H, I (FSC = 4.43361875 MHZ).......................... 40 Mode Register 1 MR1 (MR17–MR10).................................... 28 PAL M (FSC = 3.57561149 MHZ)............................................ 40 MR1 Bit Description.................................................................. 28 Optional Output Filter................................................................... 41 Subcarrier Frequency Register 3–0.......................................... 28 Optional DAC Buffering ............................................................... 42 Subcarrier Phase Register (FP7–FP0)...................................... 29 Outline Dimensions....................................................................... 43 Timing Register 0 (TR07–TR00) ............................................. 29 Ordering Guide .......................................................................... 43 TR0 Bit Description ................................................................... 29 Rev. C | Page 2 of 44 ADV7177/ADV7178 REVISION HISTORY 3/05—Rev. B to Rev. C Updated Format.................................................................. Universal Changes to Figure 6.........................................................................13 Changes to Subcarrier Frequency Register 3–0 Section ............28 Changes to Register Values Section ..............................................40 Updated Outline Dimensions........................................................43 Changes to Ordering Guide...........................................................43 3/02—Rev. A to Rev. B Changed Figures 7–13 into TPC section .....................................10 Edits to Figures 20 and 21 ..............................................................21 Rev. C | Page 3 of 44 ADV7177/ADV7178 GENERAL DESCRIPTION The ADV7177/AD7178 are integrated digital video encoders