Versal ACAP Configurable Logic Block Architecture Manual AM005 (v1.1) April 8, 2021 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 04/08/2021 Version 1.1 IMUX Register Removed IMUX control sets. 07/16/2020 Version 1.0 Initial release. N/A AM005 (v1.1) April 8, 2021Send Feedback www.xilinx.com Versal ACAP CLB Architecture 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Overview......................................................................................................4 Introduction to Versal ACAP.......................................................................................................4 CLB Features................................................................................................................................ 5 CLB Architecture..........................................................................................................................6 Differences from Previous Generations................................................................................... 8 Chapter 2: CLB Resources.......................................................................................... 9 Overview.......................................................................................................................................9 CLB Resources............................................................................................................................. 9 Look-Up Table............................................................................................................................10 Storage Elements...................................................................................................................... 16 Carry Logic................................................................................................................................. 18 Primitives....................................................................................................................................20 Appendix A: Additional Resources and Legal Notices............................. 27 Xilinx Resources.........................................................................................................................27 Documentation Navigator and Design Hubs.........................................................................27 Please Read: Important Legal Notices................................................................................... 28 AM005 (v1.1) April 8, 2021Send Feedback www.xilinx.com Versal ACAP CLB Architecture 3 Chapter 1: Overview Chapter 1 Overview Introduction to Versal ACAP Versal™ adaptive compute acceleration platforms (ACAPs) combine Scalar Engines, Adaptable Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. Most importantly, Versal ACAP hardware and software are targeted for programming and optimization by data scientists and software and hardware developers. Versal ACAPs are enabled by a host of tools, software, libraries, IP, middleware, and frameworks to enable all industry-standard design flows. Built on the TSMC 7 nm FinFET process technology, the Versal portfolio is the first platform to combine software programmability and domain-specific hardware acceleration with the adaptability necessary to meet today's rapid pace of innovation. The portfolio includes six series of devices uniquely architected to deliver scalability and AI inference capabilities for a host of applications across different markets—from cloud—to networking—to wireless communications— to edge computing and endpoints. The Versal architecture combines different engine types with a wealth of connectivity and communication capability and a network on chip (NoC) to enable seamless memory-mapped access to the full height and width of the device. Intelligent Engines are SIMD VLIW AI Engines for adaptive inference and advanced signal processing compute, and DSP Engines for fixed point, floating point, and complex MAC operations. Adaptable Engines are a combination of programmable logic blocks and memory, architected for high-compute density. Scalar Engines, including Arm® Cortex®-A72 and Cortex-R5F processors, allow for intensive compute tasks. The Versal AI Core series delivers breakthrough AI inference acceleration with AI Engines that deliver over 100x greater compute performance than current server-class of CPUs. This series is designed for a breadth of applications, including cloud for dynamic workloads and network for massive bandwidth, all while delivering advanced safety and security features. AI and data scientists, as well as software and hardware developers, can all take advantage of the high- compute density to accelerate the performance of any application. AM005 (v1.1) April 8, 2021Send Feedback www.xilinx.com Versal ACAP CLB Architecture 4 Chapter 1: Overview The Versal Prime series is the foundation and the mid-range of the Versal platform, serving the broadest range of uses across multiple markets. These applications include 100G to 200G networking equipment, network and storage acceleration in the Data Center, communications test equipment, broadcast, and aerospace & defense. The series integrates mainstream 58G transceivers and optimized I/O and DDR connectivity, achieving low-latency acceleration and performance across diverse workloads. The Versal Premium series provides breakthrough heterogeneous integration, very high- performance compute, connectivity, and security in an adaptable platform with a minimized power and area footprint. The series is designed to exceed the demands of high-bandwidth, compute-intensive applications in wired communications, data center, test & measurement, and other applications. Versal Premium series ACAPs include 112G PAM4 transceivers and integrated blocks for 600G Ethernet, 600G Interlaken, PCI Express® Gen5, and high-speed cryptography. The Versal architecture documentation suite is available at: https://www.xilinx.com/versal. Navigating Content by Design Process Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. All Versal™ ACAP design process Design Hubs can be found on the Xilinx.com website. This document covers the following design processes: • Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware platform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include: • CLB Resources • Look-Up Table • Storage Elements • Carry Logic • Primitives CLB Features The configurable logic block (CLB) provides the most basic, flexible logic functionality in Versal™ adaptable computing acceleration platforms (ACAPs). It can map any arbitrary function into programmable resources. Features include: • Implementation of any arbitrary programmable logic function into functional units (LUTs) • Flip-flops and latches for state retention and pipelining AM005 (v1.1) April 8, 2021Send Feedback www.xilinx.com Versal ACAP CLB Architecture 5 Chapter 1: Overview • Acceleration of wide arithmetic/logic functions • Shift registers • Small (64-bit) distributed RAM CLB Architecture The CLB is the main resource in each Versal™ device and implements programmable combinational logic, sequential logic, and logic paths. These features enable high functionality and routability. The following figure shows a high-level block diagram of the CLB. There are two CLB types, one with super long line (SLL) connections, and one without. Each CLB contains equal numbers of LUTRAM and SRL-capable LUTs. Only one LUT type can be used in a SLICEM. Figure 1: CLB Block Diagram H_L H_M H_L H_M G_L G_M G_L G_M F_L F_M F_L F_M E_L E_M E_L E_M D_L D_M D_L D_M CLB interconnect interconnect CLB Carry Lookahead (8bit) CarryLookahead (8bit) Carry Lookahead (8bit) CarryLookahead (8bit) Carry Lookahead (8bit) CarryLookahead (8bit) C_L C_M CarryLookahead (8bit) C_L C_M B_L B_M B_L B_M A_L A_M A_L A_M Flip-flop LUT LUTRAM/SRL-capable LUT IMUX register X20616-030821 The following figure shows a Versal device SLICEL/SLICEM. Note the IMUX registers, the carry lookahead logic which now contain fast lookahead multiplexers, and input and output multiplexers before and after the flip-flops. The multiplexers after the flip-flops are new to Versal devices. Some of the inputs to the input multiplexer are from the SLL connections. AM005 (v1.1) April 8, 2021Send Feedback www.xilinx.com Versal ACAP CLB Architecture 6 Chapter 1: Overview Figure 2: SLICEL/SLICEM Block Diagram Key Replace asterisks in labels with cell name A-H * *X Primary input/output of slice CLK Input from CLK_MOD output *I Input from IMUX REG output LRAM_WE WE Features in SLICEM only indicated with blue outlines and text SOUT COUT COUT* CY* O6 *_O SOUT *_I *1-6 *1-6 A1-6 *Q2 A1-6 D Q *_I *_I DI O5 DI CLK CLK *X *X DI2WE2 PROP PROP* SR SR LRAM_WE WE WE CKEN4 CE *FF2 H1-6 WA1-6 WA1-6 *X CLK CLK CLK O5 *Q D Q CLK CASC CASC CLK CLK SR LAG_W1 *5LUT SR SR CKEN4 IMUX REGS CKEN4 CE *FF *6LUT SIN H CY* O6 *_O SOUT *_I *1-6 *1-6 A1-6 *Q2 A1-6 D Q *_I *_I DI O5 DI CLK CLK *X *X DI2WE2 PROP PROP* LAG_W1 SR SR LRAM_WE WE