LVDS Owner’s Manual Including High-Speed CML and Signal Conditioning High-Speed Interface Technologies Overview 9-13 Network Topology 15-17 SerDes Architectures 19-29 Termination and Translation 31-38 Design and Layout Guidelines 39-45 Jitter Overview 47-58 Interconnect Media and Signal Conditioning 59-75 I/O Models 77-82 Solutions for Design Challenges 83-101 www.ti.com/LVDS 2008 2 LVDS Owner’s Manual Including High-Speed CML and Signal Conditioning Fourth Edition 2008 www.ti.com/LVDS 3 Contents Introduction ..........................................................................7 Design and Layout Guidelines ........................................39 5.1 PCB Transmission Lines ......................................................39 High-Speed Interface Technologies Overview..............9 5.2 Transmission Loss ................................................................40 1.1 Differential Signaling Technology .......................................9 5.3 PCB Vias .................................................................................41 1.2 LVDS – Low-Voltage Differential Signaling .....................10 5.4 Backplane Subsystem .........................................................42 1.3 CML – Current-Mode Logic .................................................11 5.5 Decoupling .............................................................................44 1.4 Low-Voltage Positive-Emitter-Coupled Logic .................12 1.5 Selecting An Optimal Technology .....................................12 Jitter Overview ..................................................................47 6.1 Introduction ............................................................................47 Network Topology .............................................................15 Random Jitter Characteristics ......................................47 2.1 Point-to-Point ........................................................................15 Deterministic Jitter .........................................................48 2.2 Multipoint / Multidrop ..........................................................16 Duty Cycle Distortion ......................................................49 2.3 SerDes Architectures ...........................................................17 Inter-Symbol Interference .............................................50 2.4 Mixing Signaling Technologies .........................................17 Periodic Jitter ..................................................................52 2.5 Selecting an Interface Technology ...................................17 6.2 Additional Jitter Sources ....................................................52 SerDes Architectures .......................................................19 Effect of Input Capacitance ...........................................53 3.1 Introduction ............................................................................19 FEXT/NEXT ........................................................................53 3.2 Parallel Clock SerDes ..........................................................19 Systems Susceptible to Crosstalk ...............................54 3.3 Embedded Clock (Start-Stop) Bits SerDes .......................20 Bit Error Rate ....................................................................54 3.4 8b/10b SerDes ........................................................................21 6.3 Pattern Dependencies and Eye Diagrams ........................55 3.5 FPGA-Attach SerDes ............................................................22 Eye Masks ........................................................................57 3.6 Applications ...........................................................................23 Bathtub Curves and Eye Contours ................................57 Parallel Clock SerDes ....................................................23 Interconnect Media and Signal Conditioning ..............59 Embedded Clock (Start-Stop) Bits SerDes .................24 7.1 Physical and Electrical Cable Characteristics ...............59 8b/10b SerDes ..................................................................26 7.2 Signal-Conditioning Characteristics ................................63 FPGA-Attach SerDes ......................................................27 Media Losses in Cables and PCB Traces ...................63 3.7 Comparison Overview ..........................................................28 Pre-Emphasis and De-Emphasis Drivers ....................64 3.8 Summary .................................................................................29 Equalization ......................................................................65 Termination and Translation ............................................31 Two Types of Equalizer Circuits ...................................66 4.1 Terminations and Impedance Matching ...........................31 Passive: Power-Saver Equalizers ................................66 4.2 Multidrop and Multipoint ....................................................31 Active Equalizers ............................................................66 4.3 AC Coupling ...........................................................................32 Fixed Equalizers ..............................................................67 4.4 DC Balance ............................................................................33 Variable Equalizers Allow Control ...............................67 Selecting a Capacitor .....................................................34 Adaptive Equalizers ........................................................67 4.5 Translation .............................................................................35 Crosstalk ...........................................................................68 4.6 Failsafes .................................................................................37 Reflections ........................................................................68 M-LVDS Failsafes ............................................................38 4 Contents 7.3 Using Pre- and De-Emphasis and Equalizers Together .70 9.6 M-LVDS: A High-Speed, Short-Reach Alternative 7.4 Random Noise .......................................................................70 to RS-485...............................................................................96 7.5 Re-clocking Receivers (Re-clockers) ...............................71 9.7 Redundancy ...........................................................................97 7.6 Bit Error Rate (BER) and Jitter 9.8 Testability of High-Speed Differential Networks ...........98 (Random and Deterministic) ...............................................72 Functional Testing ...........................................................98 Lossy Media Compensated by Equalization ...............72 Loopback ..........................................................................98 Pre-Emphasis Eye Diagrams .........................................74 9.9 DVI / HDMI ............................................................................101 PE/EQ Combination .........................................................75 High Data Rates and Longer Cost-Effective Cables 101 Compensation for Skin Effects and Semiconductor I/O Models ..............................................77 Dielectric Losses ..........................................................101 8.1 Input/Output Buffer Information Specification ................77 8.2 Behavioral Diagram of IBIS ................................................78 Appendix of Technical References ..............................103 8.3 3-State Output Model ...........................................................78 10.1 Websites and LVDS Applications ..................................103 ® ® 8.4 Creating IBIS Models ...........................................................79 10.2 Analog Edge and Signal Path Designer Articles ...103 8.5 Scattering Parameters (S Parameters) .............................80 10.3 Outside Publications .......................................................104 10.4 Application Note References .........................................104 8.6 SPICE Models ........................................................................82 10.5 Index ...................................................................................105 Solutions for Design Challenges ....................................83 10.6 Acronyms ...........................................................................107 9.1 Clock Distribution and Signal Conditioning ....................83 10.7 Glossary of Common Datasheet Parameters ...............108 Point-to-Point Clock Distribution .................................83 Multipoint Clock Distribution .......................................83 Clock Conditioners .........................................................84 9.2 System Clock Distribution ...................................................86 ATCA-Synchronization Clock Interface ......................86 MicroTCA-Synchronization Clock Interface ..............87 9.3 Complementing FPGA Performance ..................................88 Extending SerDes Enables FPGAs ...............................88 Load Capacitance is Critical .........................................89 LVDS Translation .............................................................90 9.4 Broadcast Video ....................................................................91 9.5 Extending the Reach of SerDes ..........................................92