CA3140, CA3140A Datasheet

CA3140, CA3140A Datasheet

DATASHEET CA3140, CA3140A FN957 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output Rev.10.00 Jul 11, 2005 The CA3140A and CA3140 are integrated circuit operational Features amplifiers that combine the advantages of high voltage • MOSFET Input Stage PMOS transistors with high voltage bipolar transistors on a - Very High Input Impedance (Z ) -1.5T (Typ) single monolithic chip. IN - Very Low Input Current (Il) -10pA (Typ) at 15V The CA3140A and CA3140 BiMOS operational amplifiers - Wide Common Mode Input Voltage Range (VlCR) - Can be feature gate protected MOSFET (PMOS) transistors in the Swung 0.5V Below Negative Supply Voltage Rail input circuit to provide very high input impedance, very low - Output Swing Complements Input Common Mode input current, and high speed performance. The CA3140A Range and CA3140 operate at supply voltage from 4V to 36V • Directly Replaces Industry Type 741 in Most Applications (either single or dual supply). These operational amplifiers are internally phase compensated to achieve stable • Pb-Free Plus Anneal Available (RoHS Compliant) operation in unity gain follower operation, and additionally, have access terminal for a supplementary external capacitor Applications if additional frequency roll-off is desired. Terminals are also • Ground-Referenced Single Supply Amplifiers in provided for use in applications requiring input offset voltage Automobile and Portable Instrumentation nulling. The use of PMOS field effect transistors in the input • Sample and Hold Amplifiers stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important • Long Duration Timers/Multivibrators attribute for single supply applications. The output stage (seconds-Minutes-Hours) uses bipolar transistors and includes built-in protection • Photocurrent Instrumentation against damage from load terminal short circuiting to either • Peak Detectors supply rail or to ground. • Active Filters The CA3140A and CA3140 are intended for operation at supply voltages up to 36V (18V). • Comparators • Interface in 5V TTL Systems and Other Low Supply Voltage Systems • All Standard Operational Amplifier Applications • Function Generators • Tone Controls • Power Supplies • Portable Instruments • Intrusion Alarm Systems Pinout CA3140 (PDIP, SOIC) TOP VIEW OFFSET 1 8 NULL STROBE 2 7 INV. INPUT - V+ NON-INV. + 3 6 OUTPUT INPUT OFFSET V- 4 5 NULL FN957 Rev.10.00 Page 1 of 24 Jul 11, 2005 CA3140, CA3140A Ordering Information PART NUMBER TEMP. PKG. (BRAND) RANGE (°C) PACKAGE DWG. # CA3140AE -55 to 125 8 Ld PDIP E8.3 CA3140AEZ* -55 to 125 8 Ld PDIP E8.3 (See Note) (Pb-free) CA3140AM -55 to 125 8 Ld SOIC M8.15 (3140A) CA3140AM96 -55 to 125 8 Ld SOIC Tape and Reel (3140A) CA3140AMZ -55 to 125 8 Ld SOIC M8.15 (3140A) (See Note) (Pb-free) CA3140AMZ96 -55 to 125 8 Ld SOIC Tape and Reel (3140A) (See Note) (Pb-free) CA3140E -55 to 125 8 Ld PDIP E8.3 CA3140EZ* -55 to 125 8 Ld PDIP E8.3 (See Note) (Pb-free) CA3140M -55 to 125 8 Ld SOIC M8.15 (3140) CA3140M96 -55 to 125 8 Ld SOIC Tape and Reel (3140) CA3140MZ -55 to 125 8 Ld SOIC M8.15 (3140) (See Note) (Pb-free) CA3140MZ96 -55 to 125 8 Ld SOIC Tape and Reel (3140) (See Note) (Pb-free) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. FN957 Rev.10.00 Page 2 of 24 Jul 11, 2005 CA3140, CA3140A Absolute Maximum Ratings Thermal Information o o DC Supply Voltage (Between V+ and V- Terminals) . 36V Thermal Resistance (Typical, Note 1) JA ( C/W) JC ( C/W) Differential Mode Input Voltage . 8V PDIP Package* . 115 N/A DC Input Voltage . (V++8V) To (V- -0.5V) SOIC Package . 165 N/A Input Terminal Current . 1mA Maximum Junction Temperature (Plastic Package) . 150oC Output Short Circuit Duration (Note 2) . Indefinite Maximum Storage Temperature Range. -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . 300oC Operating Conditions (SOIC - Lead Tips Only) Temperature Range . -55oC to 125oC *Pb-free PDIPs can be used for through hole wave solder process- ing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details 2. Short circuit may be applied to ground or to either supply. o Electrical Specifications VSUPPLY = 15V, TA = 25 C TYPICAL VALUES PARAMETER SYMBOL TEST CONDITIONS CA3140 CA3140A UNITS Input Offset Voltage Adjustment Resistor Typical Value of Resistor 4.7 18 k Between Terminals 4 and 5 or 4 and 1 to Adjust Max VIO Input Resistance RI 1.5 1.5 T Input Capacitance CI 44pF Output Resistance RO 60 60 Equivalent Wideband Input Noise Voltage eN BW = 140kHz, RS = 1M 48 48 V (See Figure 27) Equivalent Input Noise Voltage (See Figure 35) eN RS = 100 f = 1kHz 40 40 nV/Hz f = 10kHz 12 12 nV/Hz Short Circuit Current to Opposite Supply IOM+ Source 40 40 mA IOM-Sink1818mA Gain-Bandwidth Product, (See Figures 6, 30) fT 4.5 4.5 MHz Slew Rate, (See Figure 31) SR 9 9 V/s Sink Current From Terminal 8 To Terminal 4 to 220 220 A Swing Output Low Transient Response (See Figure 28) tr RL = 2k Rise Time 0.08 0.08 s C = 100pF OSL Overshoot 10 10 % Settling Time at 10VP-P, (See Figure 5) tS RL = 2k To 1mV 4.5 4.5 s C = 100pF L 1.4 1.4 s Voltage Follower To 10mV o Electrical Specifications For Equipment Design, at VSUPPLY = 15V, TA = 25 C, Unless Otherwise Specified CA3140 CA3140A PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage |VIO|- 5 15- 2 5mV Input Offset Current |IIO| - 0.5 30 - 0.5 20 pA Input Current II - 10 50 - 10 40 pA FN957 Rev.10.00 Page 3 of 24 Jul 11, 2005 CA3140, CA3140A o Electrical Specifications For Equipment Design, at VSUPPLY = 15V, TA = 25 C, Unless Otherwise Specified (Continued) CA3140 CA3140A PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS Large Signal Voltage Gain (Note 3) AOL 20 100 - 20 100 - kV/V (See Figures 6, 29) 86 100 - 86 100 - dB Common Mode Rejection Ratio CMRR - 32 320 - 32 320 V/V (See Figure 34) 70 90 - 70 90 - dB Common Mode Input Voltage Range (See Figure 8) VICR -15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 V Power-Supply Rejection Ratio, PSRR - 100 150 - 100 150 V/V V /V (See Figure 36) IO S 76 80 - 76 80 - dB Max Output Voltage (Note 4) VOM+ +12 13 - +12 13 - V (See Figures 2, 8) VOM- -14 -14.4 - -14 -14.4 - V Supply Current (See Figure 32) I+ - 4 6 - 4 6 mA Device Dissipation PD - 120 180 - 120 180 mW o Input Offset Voltage Temperature Drift VIO/T- 8 - - 6 -V/ C NOTES: 3. At VO = 26VP-P, +12V, -14V and RL = 2k. 4. At RL = 2k. o Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25 C TYPICAL VALUES PARAMETER SYMBOL CA3140 CA3140A UNITS Input Offset Voltage |VIO|5 2mV Input Offset Current |IIO|0.10.1pA Input Current II 22pA Input Resistance RI 11T Large Signal Voltage Gain (See Figures 6, 29) AOL 100 100 kV/V 100 100 dB Common Mode Rejection Ratio CMRR 32 32 V/V 90 90 dB Common Mode Input Voltage Range (See Figure 8) VICR -0.5 -0.5 V 2.6 2.6 V Power Supply Rejection Ratio PSRR 100 100 V/V V /V IO S 80 80 dB Maximum Output Voltage (See Figures 2, 8) VOM+3 3 V VOM- 0.13 0.13 V Maximum Output Current: Source IOM+1010mA I Sink OM-1 1mA Slew Rate (See Figure 31) SR 7 7 V/s Gain-Bandwidth Product (See Figure 30) fT 3.7 3.7 MHz Supply Current (See Figure 32) I+ 1.6 1.6 mA Device Dissipation PD 88mW FN957 Rev.10.00 Page 4 of 24 Jul 11, 2005 CA3140, CA3140A o Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25 C (Continued) TYPICAL VALUES PARAMETER SYMBOL CA3140 CA3140A UNITS Sink Current from Terminal 8 to Terminal 4 to Swing Output Low 200 200 A Block Diagram 2mA 4mA 7 V+ BIAS CIRCUIT CURRENT SOURCES AND REGULATOR 200A2001.6mAA 2A2mA + 3 A INPUT A 10 A 1 6 OUTPUT - 10,000 2 C1 12pF 4 V- 5 1 8 STROBE OFFSET NULL FN957 Rev.10.00 Page 5 of 24 Jul 11, 2005 CA3140, CA3140A Schematic Diagram BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK 7 V+ D 1 D7 R13 5K Q3 R Q20 Q Q 9 1 2 50 D8 R10 Q4 1K Q6 Q5 R14 R 20K Q19 R11 12 12K Q7 20 Q21 Q17 R1 R 8K Q8 8 1K Q18 6 OUTPUT D 2 D3 D4 D5 INVERTING 2 INPUT - Q9 Q10 + NON-INVERTING 3 INPUT C1 R2 R3 500 500 12pF Q Q 14 Q15 16 Q13 Q11 Q12 D6 R4 R5 R6 R7 500 500 50 30 5 1 8 4 OFFSET NULL STROBE V- NOTE: All resistance values are in ohms.

View Full Text

Details

  • File Type
    pdf
  • Upload Time
    -
  • Content Languages
    English
  • Upload User
    Anonymous/Not logged-in
  • File Pages
    24 Page
  • File Size
    -

Download

Channel Download Status
Express Download Enable

Copyright

We respect the copyrights and intellectual property rights of all users. All uploaded documents are either original works of the uploader or authorized works of the rightful owners.

  • Not to be reproduced or distributed without explicit permission.
  • Not used for commercial purposes outside of approved use cases.
  • Not used to infringe on the rights of the original creators.
  • If you believe any content infringes your copyright, please contact us immediately.

Support

For help with questions, suggestions, or problems, please contact us