<p> ELECTRONIC DIGIT 1</p><p>LAB 6: J-K FLIP-FLOP </p><p>OBJECTIVES:</p><p>1. To investigate the basic circuit of J-K flip-flop constructed using basic gates. 2. To investigate the operation of J-K flip-flop and R-S flip-flop. 3. Determine input and output states of J-K flip-flop circuits.</p><p>EQUIPMENTS/COMPONENTS</p><p> Logic gates ( 74XX-series)  J-K flip- flop (7476)  LED monitor  Oscilloscope  Signal Generator</p><p>INTRODUCTION</p><p>Flip-flop is a basic memory element that is able to store binary information. Even though it is made up of a combinational logic gate that has no storage capability, the way it is connected permit information to be stored. It is called flip-flop because it can be flipped into its set condition in which it stores a binary 1, or flopped into its reset condition in which it stores a binary 0.</p><p>PROCEDURE</p><p>1. R-S flip-flop: Construct a circuit as shown in Figure 6.1. Connect switches to the input and complete Table 6.1 by monitoring the output using the LED display.</p><p>R Q</p><p>Q S</p><p>Figure 6.1</p><p>2. Make a modification on the previous circuit by connecting the circuit as illustrated at Figure 6.2. Connect another switch for the CLK input and complete Table 6.2.</p><p>KOLEJ UNIVERSITI KEJURUTERAAN UTARA MALAYSIA ELECTRONIC DIGIT 1</p><p>R Q</p><p>CLK</p><p>Q S</p><p>Figure 6.2</p><p>3. J-K flip-flop: Combine the circuit constructed in procedure 2 with gate AND as shown in Figure 6.3. Perform the following series of test on the circuit by completing Table 6.3.</p><p>Q K FigureFigure 6.25-2 CLK J (flip-flop RS) Q</p><p>Figure 6.3</p><p>4. Figure 6.4 shows IC 7476 which is a JK flip-flop. Verify the operation of JK flip-flop by ignoring the PRE and CLR input. Fill in the results at Table 6.4.</p><p>PRE</p><p>J Q CLK 7476 K Q</p><p>CLR</p><p>Figure 6.4</p><p>5. Experiment in procedure 4 is repeated but this time the PRE and CLR input are considered. Test all the possible input combination and complete Table 6.5.</p><p>KOLEJ UNIVERSITI KEJURUTERAAN UTARA MALAYSIA ELECTRONIC DIGIT 1</p><p>Name: ______Matrix No. : ______</p><p>RESULTS</p><p>Table 6.1</p><p>Input Output R S Q Q 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 </p><p>Table 6.2</p><p>Input Output R S CLK Q Q 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 </p><p>Table 6.3</p><p>KOLEJ UNIVERSITI KEJURUTERAAN UTARA MALAYSIA ELECTRONIC DIGIT 1</p><p>Input Output J K CLK Q Q 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 1 1 0 </p><p>Table 6.4</p><p>Input Output J K CLK Q Q 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 1 1 0 </p><p>Table 6.5</p><p>KOLEJ UNIVERSITI KEJURUTERAAN UTARA MALAYSIA ELECTRONIC DIGIT 1</p><p>Input Output</p><p>KOLEJ UNIVERSITI KEJURUTERAAN UTARA MALAYSIA ELECTRONIC DIGIT 1</p><p>CLR PRE J K CLK Q Q 1 1 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 1 </p><p>CONCLUSIONS</p><p>1. Based on your observations, explain the different between RS flip-flop and JK flip- flop in term of its operation.</p><p>KOLEJ UNIVERSITI KEJURUTERAAN UTARA MALAYSIA ELECTRONIC DIGIT 1</p><p>2. Discuss the effect of PRE and CLR in JK flip-flop.</p><p>APPENDIX</p><p>KOLEJ UNIVERSITI KEJURUTERAAN UTARA MALAYSIA ELECTRONIC DIGIT 1</p><p>KOLEJ UNIVERSITI KEJURUTERAAN UTARA MALAYSIA</p>