See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/241637649 Power-Management Architecture of the Intel Microarchitecture Code-Named Sandy Bridge Article in IEEE Micro · March 2012 DOI: 10.1109/MM.2012.12 CITATIONS READS 107 126 5 authors, including: Effi Rotem Alon Naveh Intel Technion - Israel Institute of Technology 31 PUBLICATIONS 232 CITATIONS 14 PUBLICATIONS 248 CITATIONS SEE PROFILE SEE PROFILE All content following this page was uploaded by Effi Rotem on 01 May 2016. The user has requested enhancement of the downloaded file. All in-text references underlined in blue are added to the original document and are linked to publications on ResearchGate, letting you access and read them immediately. [3B2-9] mmi2012020020.3d 12/3/012 14:20 Page 20 .......................................................................................................................................................................................................................... POWER-MANAGEMENT ARCHITECTURE OF THE INTEL MICROARCHITECTURE CODE-NAMED SANDY BRIDGE .......................................................................................................................................................................................................................... MODERN MICROPROCESSORS ARE EVOLVING INTO SYSTEM-ON-A-CHIP DESIGNS WITH HIGH INTEGRATION LEVELS, CATERING TO EVER-SHRINKING FORM FACTORS.PORTABILITY WITHOUT COMPROMISING PERFORMANCE IS A DRIVING MARKET NEED.AN ARCHITEC- TURAL APPROACH THAT’S ADAPTIVE TO AND COGNIZANT OF WORKLOAD BEHAVIOR AND PLATFORM PHYSICAL CONSTRAINTS IS INDISPENSABLE TO MEETING THESE PERFORMANCE AND EFFICIENCY GOALS.THIS ARTICLE DESCRIBES POWER-MANAGEMENT INNOVATIONS INTRODUCED ON INTEL’S SANDY BRIDGE MICROPROCESSOR. ......Continuous advances in process multithreading capabilities and improved technology let designers integrate an ever- power management and energy efficiency. increasing number of transistors onto a single We also introduced several architectural die. This increased transistor density has en- changes, most notably the 256-bit Advanced abled system-on-a-chip (SoC) functionality Vector Extension (AVX). by integrating graphics engines, memory con- In addition, we moved the processor graph- Efraim Rotem trollers, and other platform components into ics from the chip set or discrete graphics onto modern CPU dies. The Sandy Bridge client the lead CPU process technology, resulting in Alon Naveh CPU contains just over 1 billion transistors, much higher transistor counts, lower power, and the Sandy Bridge server contains up to and higher frequencies. We also significantly Doron Rajwan 3 times as many on a single monolithic die. improved the internal microarchitecture of The second-generation Sandy Bridge core the processor graphics and media, resulting Avinash Ananthakrishnan processor has five main domains: Intel archi- in much higher-performance execution units tecture cores, a ring interconnect, a shared and high-performance media functionality. Eliezer Weissmann last-level cache (LLC), a system agent, and The ring interconnect and LLC architec- processor graphics. Figure 1 describes the ture provide high modularity and feature- Intel Sandy Bridge die. rich general-purpose, graphics, media, and system integration. Sandy Bridge redesign The transistor count increase and integra- We significantly redesigned Sandy Bridge tion of platform components into a mono- from the previous generation, providing lithic die, together with the increase in core increased instruction-level parallelism and frequency, introduce demanding power and .............................................................. 20 Published by the IEEE Computer Society 0272-1732/12/$31.00 c 2012 IEEE [3B2-9] mmi2012020020.3d 12/3/012 14:20 Page 21 energy challenges to modern computers. Be- cause computer systems’ power and thermal envelopes aren’t increasing, addressing these challenges requires a highly energy-efficient design. Sandy Bridge power management builds on the existing SpeedStep and Turbo Boost technologies significantly increasing performance and energy efficiency. Sandy Bridge’s power-management features provide the maximum performance possible within the package and system physical constraints when needed, while consuming very low power and energy when full performance isn’t needed. Furthermore, we expanded Figure 1. The Sandy Bridge die photo. the power-management features implemented in previous generations of Intel CPUs on Sandy Bridge to give the rest of the SoC power budgeting and prioritization capabilities. DMI PCI Express Power-management architecture Voltage System agent The Package Control Unit (PCU) is regulator SVID IMC the brain behind the Sandy Bridge power- Embedded PECI PCU management features. The power-management controller Display architecture is highlighted over the block Core PMA LLC diagram in Figure 2. The PCU resides in Core LLC the system agent and is a combination of dedi- Core LLC cated hardware state machines and an inte- grated microcontroller. A power-management Core LLC link connects the PCU to different cores Processor graphics and functional blocks on the die via power- management agents (PMAs). PMAs collect te- lemetry information such as power consump- Figure 2. Sandy Bridge’s power-management tion and junction temperature, and perform architecture. Sandy Bridge block diagram control functions such as P-state and C-state showing the major functional blocks and transitions. The PCU communicates to the ex- the power-management control blocks ternal voltage regulator and embedded control- and interconnect. The platform power- ler that perform system power-management management components and the associated functions. The PCU runs firmware that con- platform interconnect are also shown. stantly collects power and thermal informa- tion, communicates with the system, and performs various power-management func- tions and optimization algorithms. independent power plane, whose voltage and Sandy Bridge’s package implements two frequency can be varied independently. It independent variable power planes. One can also be turned off completely when the shared power plane feeds all CPU cores, the graphics are inactive. Additional fixed power ring, and the LLC. Embedded power gates planes control the system agent and I/O. turn each core on and off individually. The The Sandy Bridge power management LLC’s power gates can turn on or off portions maximizes the user experience under multi- of the cache in shallow package sleep states or ple constraints. The user experience has the all of the cache in deeper sleep states. All the following attributes: cores and the ring share the same clock and perform dynamic voltage and frequency scal- throughput performance, ing together. The graphics processor has an responsiveness (burst performance), .................................................................... MARCH/APRIL 2012 21 [3B2-9] mmi2012020020.3d 12/3/012 14:20 Page 22 ............................................................................................................................................................................................... HOT CHIPS same time at worst-case conditions.1 In 45 most cases, the CPU is running a less- 40 35 demanding application and the Intel Turbo 30 Boost technology uses this power headroom 25 to extract higher performance when possi- 20 ble.2,3 Sandy Bridge’s power performance Power (W) 15 control is performed primarily through 10 dynamic voltage and frequency scaling 5 (DVFS). When the operating system identi- 0 0 50 100 150 200 250 fies a need for high performance, it issues a Time (s) high P-state request. Whenever power and thermal headroom exist, the PCU increases CPU–predicted CPU–actual PG–predicted PG–actual the voltage and frequency to the highest Package–predicted Package–actual point that is lower than or equal to the oper- ating system request, that still meets all phys- Figure 3. Power meter: predicted and actual power of the CPU, processor ical constraints. Sandy Bridge implements graphics, and total package. The figure shows a power snapshot of architectural power meters. It collects a set combined CPU and graphics workload. The chart presents the actual of architectural events from each Intel archi- measured power and the architectural power meter reporting for the IA tecture core, the processor graphics, and I/O, core, processor graphics, and total package. The actual and reported and combines them with energy weights to power correlate accurately. predict the package’s active power consump- tion. Leakage information is coded into the die and is scaled with operating conditions such as voltage and temperature to provide CPU and graphics performance, the package’s total power consumption. battery life and energy bills, and The system uses architectural power predic- ergonomics (acoustic noise, heat, and tor output, which is also exposed externally so on). to software, to decide the amount of turbo To meet user preferences, the power- upside available for the current workload management algorithms optimize around (turbo upside is available higher frequency the following physical constraints: that the CPU can go up to and use for higher performance).4,5 The architectural power silicon capabilities, including voltage, predictor provides a consistent turbo behavior frequency and power characteristics; while minimizing the die-to-die variations system thermomechanical