University of Montana ScholarWorks at University of Montana Graduate Student Theses, Dissertations, & Professional Papers Graduate School 1984 Modula-2 concurrency Philip E. Rosine The University of Montana Follow this and additional works at: https://scholarworks.umt.edu/etd Let us know how access to this document benefits ou.y Recommended Citation Rosine, Philip E., "Modula-2 concurrency" (1984). Graduate Student Theses, Dissertations, & Professional Papers. 5540. https://scholarworks.umt.edu/etd/5540 This Thesis is brought to you for free and open access by the Graduate School at ScholarWorks at University of Montana. It has been accepted for inclusion in Graduate Student Theses, Dissertations, & Professional Papers by an authorized administrator of ScholarWorks at University of Montana. For more information, please contact [email protected]. COPYRIGHT ACT OF 1976 Th i s is a n unpublished m a n u s c r i p t in w h i c h c o p y r i g h t s u b ­ s i s t s . An y f u r t h e r r e p r i n t i n g o f its c o n t e n t s m u s t b e a p p r o v e d BY THE AUTHOR. Ma n s f i e l d L i b r a r y Un i v e r s i t y o f Mo n t a n a Modula-2 Concurrency by Philip E. Rosine B.S., University of Idaho, 1969 Presented in partial fulfillment of the requirements for the degree of Master of Science UNIVERSITY OF MONTANA 1984 oA)u i |, , i >i imim ~ ~ ................................ Chairman, Board of Examiners D Date UMI Number: EP41004 All rights reserved INFORMATION TO ALL USERS The quality of this reproduction is dependent upon the quality of the copy submitted. In the unlikely event that the author did not send a complete manuscript and there are missing pages, these will be noted. Also, if material had to be removed, a note will indicate the deletion. UMI* - D is s ifta lto RaMstwig UMI EP41004 Published by ProQuest LLC (2014). Copyright in the Dissertation held by the Author. Microform Edition © ProQuest LLC. All rights reserved. This work is protected against unauthorized copying under Title 17, United States Code ProQuest LLC. 789 East Eisenhower Parkway P.O. Box 1346 Ann Arbor, Ml 48106- 1346 Rosine, Philip E.r M.S., June 1984 Computer Science Modula-2 Concurrency (431+vii pp.) Advisor: Dr. John R. Barr Modula-2, a language developed by Niklaus Wirth, is par­ ticularly well suited for teaching computer programming. Since it allows use of low level machine facilities it can be used for experimentation in many areas of comput­ er science. One particular area of interest is that of concurrent programming, in which several parts of a pro­ gram are executed simultaneously. Several methods and programming constructs for concurrent programming have been suggested and are of interest to the student. This paper deals with the development of a system in Modula-2 which is primarily designed for classroom use in teach­ ing concurrent programming concepts and techniques. Since the available computer is a PDP-11/23, a single processor system, a time-sharing concurrency scheduler was developed to simulate concurrent execution of processes. Semaphores were implemented as control structures for concurrent programs. The scheduler pack­ age includes a trace feature which allows a programmer to follow the execution of a concurrent program. A >pre-processor to convert Modula-2 modules into monitors has been developed. This allows programming of con­ current programs using higher level constructs than are allowed by using the scheduler alone. ii TABLE OF CONTENTS. Abstract .......................................... ii 1 Project Formulation ................................... .1 1.1 Background ...................... 1 1.2 Overview of the Problem.......................... 4 1.3 Components of a Teaching Package .......... 5 1.4 Methodology .................... 6 1.4.1 Analysis ...................................... 7 1.4.2 Design ................... 8 1.4.3 Implementation ............................... 8 1.4.4 Analysis ......... 9 1.4.5 Documentation ............. 9 1.4.6 Project Review ............................... 9 1.5 Proposed Work Plan ....................... 10 1.6 Preliminary Analysis ............................. 12 2 Concurrency — an Overview ........................... 14 2.1 Problems Associated with Concurrency ............ 18 2.2 Proposed Solutions ............................. 19 2.3 Co-routines ........... 19 2.4 Semaphores ........... 20 2.5 Monitors ........... 21 2.6 Message Passing ................................... 22 2.7 Rendezvous ......................................... 22 2.8 Path Expressions ........... 23 2.9 Communicating Sequential Processes .......... 24 2.10 Eventcounts and Sequencers ............. 24 3 Phase One — the basic modules ...................... 26 3.1 Input/Output ...................................... 27 3.1.1 Module InOut ............. 28 iii 3.1.2 Module ReallnOut ........................ 29 3.1.3 Module IOControl ............................. 30 3.2 Concurrent Processes — • Module Preemp- tiveScheduler ..... 31 3.2.1 Requirements & Specifications .............. 32 3.2.2 Design & Implementation ......... 35 3.2.2.1 Module Data Structures ................. 37 3.2.2.2 Procedure start ...................... 40 3.2.2.4 Procedure Clock .......................... 42 3.2.2.5 Procedure HaltProcess .......... 44 3.2.2.6 Procedure HaltScheduler ................ 45 3.2.2.7 Function StatusOfScheduler ............. 46 3.2.2.8 Function ProcessID ........... 46 3.2.2.9 Operations on type SIGNAL ......... 46 3.2.2.10 Operations on type SEMAPHORE ......... 47 3.3 Compiler Bugs .......... 48 4 Phase Two — a Monitor Pre-Processor ........... 51 4.1 Analysis ............ 54 4.2 Design ......................... 57 4.2.1 Initial Design ........................ 57 4.2.2 Monitor Algorithm ............................ 61 4.2.3 Final Design .................................. 65 4.3 Implementation ........................ 68 4.3.1 Preliminaries ...... 68 4.3.2 Implementation and Test Plan ............... 69 4.3.3 Implementation ...... 72 5 Phase Three — Scheduler Trace ...................... 77 5.1 General Discussion ............................... 77 5.2 Design of the Trace Feature ..................... 78 5.3 Implementation of the Trace Feature ............ 80 5.4 Data Structures ........ .......................... 80 5.5 Procedure TraceOutput ........ 81 6 Project Discussion .............................. 82 6.1 Project Review ................ 82 6.1.1 Phase One ..................................... 83 6.1.2 Phase Two ................ 84 6.1.3 Phase Three ................................... 84 6.2 Project Development .............................. 85 6.2.1 Analysis ...................................... 85 6.2.2 Design .................. 87 6.2.2.1 Hueristic Design ........................ 87 6.2.2.2 Formal Design ............................ 88 6.2.3 Implementation and Testing ................. 89 6.2.4 Tools ................................. 90 6.2.4.1 Modula-2 System .................. 90 6.2.4.2 ISDOS Tools ............................. 91 6.2.4.3 Local Network ...... 93 iv 6.3 Conclusions and Lessons Learned ................ 93 Appendix A — Source Code .............................. 96 Module InOut Module ReallnOut Module IOControl Module PreemptiveScheduler Module PreemptiveScheduler with Trace Program MONITR — Monitor Pre-Processor Appendix B — User's Guides ................. 97 I/O User's Guide ...... 97 Scheduler User's Guide ............................... 112 Monitor Pre-Processor User's Guide 136 Appendix C — Test Programs ............................ 146 General Tests I/O Tests Scheduler Tests Monitor Pre-Processor Tests Scheduler Trace Tests Appendix D — Analysis and Design Documents ........... 152 Level 0 PSA Formatted Problem Statement Level-1 PSA Formatted Problem Statement Level-2 PSA Formatted Problem Statement Monitor Pre-Processor Design — pdsl document .. 156 REFERENCES .................... 157 v LIST OF TABLES Monitor Algorithm Table ................................. 61 vi LIST OF ILLUSTRATIONS Level 0 Data Flow Diagram .............................. 12 Level-1 Data Flow Diagram ....................... 52 Level-2 Data Flow Diagram ...................... 57 Monitor Pre-Processor Design ...................... 66 Monitor Pre-Processor Implementation ............ 75 Chapter 1 Project Formulation 1.JL. Background The primary rationale for this project is that multi­ tasking and multi-processing are becoming increasingly important to applications programming on computers. In the past these topics and their associated problems have been primarily the concern of specialists dealing with operating systems and computer design, and for systems analysts on larger mainframe computer systems. Two of the current trends in computer science, both in terms of research and in terms of application, are distributed processing systems and multi-tasking programming languages. In order to better prepare students for these challenges, a programming language which allows 1 2 easy implementation of concurrent processes[1] and the associated control/data structures is needed. One such language is Modula-2, a computer programming language developed by Niklaus Wirth. Modula-2 is descended from the languages Pascal [Jen- sen,1978] and Modula [Wirth,1977], which were also developed by Wirth. It is essentially an extension of Pascal to include the concepts of modules and multipro­ gramming. The module concept implies both the idea of separate compilation units for program parts, and the concept of information hiding. There