86CM65 Dual Display Accelerator 83 Incorporated 86CM65 Aurora64V+ Dual Display Accelerator February 1996 S3 Incorporated P.O. Box 58058 Santa Clara, CA 95052-8058 86CM65 Dual Display Accelerator S3 Incorponted NOTATIONAL CONVENTIONS The following notational conventions are used in this data book: Signal names are shown in all uppercase letters. For exall)ple, XD. A bar over a signal name indicatas an active low signal. For example, OE. n-lll indicates a bit field from bit n to bit m. For example, 7-0 specifies bits 7 through 0, inclusive. n:m indicates a signal (pin) range from n to m. For example 0[7:0] specifies data lines 7 through 0, inclusive Use of a treiling letter H indicates a hexadecimal number. For example, 7AH is a hexadecimal number. Use of a trailing lettar b indicates a binary number. For example, 010b is a binary number. When numerical modifiers such as K or M are used, they refer to binary rather than decimal form. Thus, for example, 1 KByte would be equivalent to 1024, not 1.000 bytes. NOTICES IC Copyright 1995, 199653 Incorporated. All rights reserved. If you have received this document from S3 Incorporated in electric form, you are permitted to make the following copies for business use related to products of S3 Incorporated: one copy onto your computer for the purpose of on-line viewing, and one printed copy. With respect to ell documents, whether received in hard copy or electronic form, other use, copying or storage, in whole or in part, by any means electronic, mechanical, photocopying or otherwise, is permitted withoutthe prior written consentofS31ncorporated, P.O. Box 58058., Santa Clara CA95052-8058. 53 and True Acceleration are registered trademarks of 53 Incorporated. The 53 Corporate Logo, S3 on Board, S3 on Board design, S3d design, Vision96B, Trio, Trio64, Trio64V+, Trio64UV+, ViRGE, ViRGEN><, S3d, Scenic, Scenic/MX1, Scenic/MX2, Scenic Highway, Sonic, Sonic/AD, Aurora64V+, DuoView, Coopera­ tive Accelerator Architecture, Streams Processor, MIC, Galileo, Native-MPEG, No Compromise Integration, No Compromise Acceleration and Innovations in Acceleration are trademarks of S3 Incorporated. Other trademarks referenced in this document are owned by their respective companies. The material in this document Is for information only and is subject to change without notice. S3 Incorporated reserves the right to make changes in the product design without reservation and without notice to its users. Additional information may be obtained from: S31ncorporated, Uterature Department P.O. Box 58058, Santa Clara, CA 95052-8058. Telephone: 408-980'5400, Fax: 408·980-5444 86CM65 Dual Display Accelerator Table of Contents List of Figures vi Section 6: PCI Bus Interface ..•. 6-1 6.1 PCI CONFIGURATION ....... 6-1 List of Tables . vii 6.2 PCI CONTROLS ........... 6-1 Section 1: Introduction . 1-1 Section 7: Display Memory . • . 7-1 7.1 DISPLAY MEMORY CONFIGURATIONS. 7-1 Section 2: Mechanical Data .... 2-1 7.2 DISPLAY MEMORY REFRESH . 7-2 2.1 THERMAL SPECIFICATIONS. .. 2-1 7.3 DISPLAY MEMORY FUNCTIONAL 2.2 MECHANICAL DIMENSIONS .•. 2-1 TIMING ............... 7-2 7.4 DISPLAY MEMORY ACCESS Section 3: Pins • . 3-1 CONTROL. .. 7-10 3.1 PINOUT DIAGRAMS . .• 3-1 3.2 PIN DESCRIPTIONS .......• 3-3 Section 8: Clock Synthesis and 3.3 PIN LISTS. .. 3-8 Control ............... 8-1 8.1 CLOCK SYNTHESIS ......... 8-1 Section 4: Electrical Data ..... 4-1 8.2 CLOCK REPROGRAMMING .... 8-2 4.1 MAXIMUM RATINGS ......• 4-1 8.3 CLOCK SELECTION AND CONTROL 8-3 4.2 DC SPECIFICATIONS. .• 4-1 4.3 AC SPECIFICATIONS . .. 4-3 Section 9: Streams Processor .•. 9-1 4.3.1 RAMDAC AC Specifications .. 4-3 9.1 INPUT STREAMS .•........ 9-1 4.3.2 Clock Timing • • . 4-4 9.1.1 Primary Stream Input. 9-2 4.3.3 Input/Output Timing . .. 4-5 9.1.2 Secondary Stream Input . 9-2 9.1.3 Hardware Icon and Cursor Section 5: Reset and Power Generation ........... 9-2 Control .••...•........ 5-1 9.1.4 Frame Buffer Organization/ Double Buffering . 9-2 5.1 CONFIGURATION STRAPPING .. 5-1 9.2 INPUT PROCESSING ........ 9-4 5.2 BOUNDARY SCAN. .. 5-1 9.2.1 Primary Stream Processing .. 9-4 5.3 FLAT PANEL POWER SEQUENCING 5-4 9.2.2 Secondary Stream Processing. 9-5 5.4 POWER MANAGEMENT . .• 5-4 9.3 COMPOSiTION/OUTPUT...... 9-5 5.4.1 Normal Mode • . .. 5-4 9.3.1 Opaque Rectangular Overlaying 9-6 5.4.2 Standby Mode .. .. 5-4 9.3.2 Blending............. 9-7 5.4.3 Suspend Mode . .. 5-6 9.3.3 Color/Chroma Keying. 9-8 5.5 MIXED 3.3 VOLT AND 5 VOLT 9.3.4 Window Location . • . 9-8 OPERATION ............. 5-6 9.4 STREAMS FIFO CONTROL . 9-8 5.6 GREEN PC SUPPORT. .. 5-7 iii 86CM65 Dual Display Accelerator S3 Incorpomed Section 10: CRT/TV Interface .• 10-1 12.2.2 SAA7110 Video Input. • .. 12-7 10.1 CRT OUTPUT •....••..... 10-1 12.3 HOST PASS-THROUGH ..... 12-8 10.1.1 Operating Modes ........ 10-1 12.4 ZV PORT INTERFACE. • . .. 12-9 10.1.2 Color Modes •......... 10-2 10.1.2.1 8 Bits/Pixel - Mode 0 ..•. 10-2 Section 13: Miscellaneous 10.1.2.2 Output-doubled 8 Bits/Pixel - Functions • • . • . 13-1 Mode 8 ..•.•...•... 10-2 13.1 VIDEO BIOS ROM INTERFACE.. 13-1 10.1.2.3 15/16-Bits/Pixel - Modes 9 13.2 GENERAL INPUT PORT. .• 13-1 and 10 •........... 10-3 13.3 GENERAL OUTPUT PORT . .• 13-2 10.1.2.4 Packed 24 Bits/Pixel- Mode 121Q-3 13.4 SERIAL COMMUNICATIONS PORT 13-2 10.1.2.5 24 Bits/Pixel - Mode 13 .•. 10-3 13.5 INTERRUPT GENERATION. • •. 13-2 10.2 RAMDAC REGISTER ACCESS .•. 10-3 10.3 RAMDAC SNOOPING .....•. 10-3 10.4 SENSE GENERATION ....... 10-3 Section 14: Basic Software 10.5 TV OUTPUT ...•.•....... 10-3 Functions •...•...• 14-1 14.1 CHIP WAKEUP ..•.•..... 14-1 Section 11: Flat Panel Interface . 11-1 14.2 REGISTER ACCESS 11.1 STN PANEL SUPPORT ...••.• 11-1 14.2.1 Unlocking the S3 Registers . 14-1 11.1.1 STN Panel Selection ..•... 11-1 14.2.2 Locking the S3 Registers . .. 14-3 11.1.2 STN Panel Timing ....... 11-1 14.3 TESTING FOR THE PRESENCE OF 11.1.3 STN Panel Control .....•. 11-1 AN 86CM65 CHIP . .• 14-3 11.1.4 STN Frame Rate Control .•.. 11-3 14.4 GRAPHICS MODE SETUP ..•. 14-3 11.1.5 STN Panel Dithering . 11-3 11.1.6 Dual-Scan STN Frame Buffer .11-6 Section 15: VGA Compatibility 11.2 TFT PANEL SUPPORT ....... 11-9 Support ............ 15-1 11.2.1 TFT Panel Selection ••.... 11-9 15.1 VGA COMPATIBILITY. .. 15-1 11.2.2 TFT Panel Timing .....•.. 11~9 15.2 VESA SUPER VGA SUPPORT 15-2 11.2.3 TFT Panel Control ....... 11-9 11.2.4 TFT Panel Dithering ...•. 11-11 11.3 FLAT PANEL DISPLAY Section 16: Enhanced Mode ENHANCEMENTS ........ 11-11 Programming .......... 16-1 11.3.1 Automatic Centering . 11-11 16.1 LINEAR ADDRESSING FOR DIRECT 11.3.2 Horizontal Compensation .. 11-11 VIDEO MEMORY CPU ACCESSES 16-1 11.3.3 Vertical Compensation .... 11-11 16.2 VIDEO MEMORY ACCESS 11.3.4 Pulse Width Modulation •.. 11-11 THROUGH THE GRAPHICS ENGINE 16-2 11.3.5 Blinking ............ 11-12 16.3 MEMORY MAPPING OF 11.4 DuoView DISPLAY •......• 11-12 REGISTERS • . • . .. 16-4 11.4.1 DuoView Display Setup ... 11-12 16.3.1 Backward-Compatible MMIO 16-4 11.4.2 DuoView Programming ... 11-14 16.3.2 New MMIO . • . .. 16-6 11.4.3 DuoView Programming 16.4 PROGRAMMING . .. 16-7 Example ...........• 11-14 16.4.1 Notational Conventions ... 16-7 16.4.2 Initial Setup . .. 16-8 Section 12: Local Peripheral Bus 12-1 16.4.3 Programming Examples . .. 16-8 12.1 SceniC/MX2INTERFACE .....• 12-1 16.4.3.1 Solid Line ......... 16-9 12.1.1 SceniC/MX2 Register/Memory 16.4.3.2 Textured Line ....... 16-10 Access .............. 12-2 16.4.3.3 Rectangle Fill Solid .... 16-12 12.1.2 SceniC/MX2 Compressed Data 16.4.3.4 Image Transfer-Through Transfer ......•...... 12-4 the Plane .......... 16-13 12.1.3 SceniC/MX2 Video Capture .. 12-5 16.4.3.5 Image Transfer-Across 12.2 DIGITIZER INTERFACE ••..... 12-7 the Plane .......... 16-15 12.2.1 12C Interface for SAA7110 ., . 12-7 16.4.3.6 BitBLT-Throughthe Plane 16-17 iv 86CM65 Dual Display Accelerator 53 Incorporated 16.4.3.7 BitBLT-Across the Plane. 16-18 Section 22: Local Peripheral Bus 16.4.3.8 PatBLT-Pattern Fill Register Descriptions ..•..• 22-1 Through the Plane .... 16-20 16.4.3.9 PatBLT-Pattern Fill Across the Plane. 16-21 Section 23: PCI Register 16.4.3.10 Short Stroke Vectors ... 16-22 Descriptions ..........• 23-1 16.4.3.11 Programmable Hardware Cursor ..•......•. 16-23 16.4.3.12 Programmable Hardware Appendix A: Register Reference A-1 Icon ...•....•.•. 16-25 A.1 VGA REGISTERS. • . A-2 16.5 RECOMMENDED READING 16-26 A,2 EXTENDED SEQUENCER REGISTERS ............ A-10 A.3 EXTENDED CRTC REGISTERS .. A-21 Section 17: Standard VGA A.4 ENHANCED COMMANDS Register Descriptions .•.... 17-1 REGISTERS ............ A-30 17.1 GENERAL REGISTERS ....•.. 17-1 A,5 STREAMS PROCESSOR 17.2 SEQUENCER REGISTERS ..... 17-5 REGISTERS ....•....... A-34 17.3 CRT CONTROLLER REGISTERS . 17-10 A,6 LOCAL PERIPHERAL BUS 17.4 GRAPHICS CONTROLLER REGISTERS ............ A-38 REGISTERS •........... 17-25 A.7 PCI CONFIGURATION SPACE 17.5 ATIRIBUTE CONTROLLER REGISTERS .......•...