Layout Regularity for Design and Manufacturability Marc Pons Sol´e Directors: Francesc Moll i Jaume Abella Tesi presentada per obtenir el t´ıtolde Doctor per la Universitat Polit`ecnicade Catalunya Programa: Enginyeria Electr`onica Barcelona, 08{07{2012 To my Mother, Loles. Contents Contentsi Acknowledgmentsv Abstract vii 1 Introduction1 1.1 History of technology scaling ..................... 1 1.2 Integrated circuit manufacturing process............... 3 1.2.1 Overview ............................ 3 1.2.2 Lithography........................... 4 1.2.3 Resolution enhancement techniques.............. 7 1.2.4 Electroplating and chemical mechanical polishing...... 7 1.3 Challenges of semiconductor industry................. 11 1.3.1 Manufacturing challenges ................... 11 1.3.2 Design challenges........................ 17 1.4 Layout regularity solution....................... 19 2 Related work 21 2.1 The need for layout regularity..................... 21 2.1.1 Regularity for manufacturing................. 21 2.1.2 Regularity for design...................... 24 2.2 Regular layout fabrics ......................... 26 i ii CONTENTS 2.2.1 Gate Arrays........................... 26 2.2.2 Standard Cells ......................... 31 2.2.3 Structured ASICs ....................... 37 2.3 Existing layout analysis tools ..................... 39 2.3.1 Standard DFM flow ...................... 40 2.3.2 Mentor Graphics DFM tools ................. 41 2.3.3 Systematic manufacturing variability models . 42 2.3.4 Evaluating layout regularity.................. 44 2.4 Thesis works motivation........................ 45 3 Unique contributions of the thesis 47 3.1 VCTA regular fabric.......................... 47 3.2 VCTA automation tool......................... 48 3.3 FOCSI layout regularity metric tool ................. 49 3.4 Thesis dissemination.......................... 49 3.4.1 Books.............................. 49 3.4.2 Conferences........................... 50 3.4.3 Scientific Reports........................ 51 3.4.4 Workshops ........................... 51 4 Evaluation framework 53 4.1 Computation resources......................... 53 4.2 Electronic design automation tools.................. 54 4.2.1 Commercial tools........................ 54 4.2.2 Data treatment......................... 54 4.2.3 C programming......................... 55 4.3 Benchmark circuits and evaluations.................. 55 4.3.1 Circuits............................. 55 4.3.2 Technology nodes........................ 58 4.3.3 Layout versions......................... 59 4.3.4 Evaluations........................... 60 CONTENTS iii 5 VCTA regular fabric 63 5.1 VCTA physical design......................... 64 5.1.1 Maximizing layout regularity ................. 64 5.1.2 Basic cell Front-end design .................. 64 5.1.3 Basic cell Back-end design................... 68 5.1.4 Basic cell configuration .................... 70 5.2 VCTA Basic cell impact on design .................. 71 5.2.1 Basic cell parameters...................... 71 5.2.2 Basic cell impact on area and routability........... 72 5.2.3 Basic cell impact on energy and delay ............ 81 5.3 VCTA manual layouts evaluation................... 84 5.3.1 32-bit adders evaluation.................... 85 5.3.2 Delay-locked loop evaluation ................. 90 5.4 Conclusion ............................... 97 6 VCTA Automation 99 6.1 VCTA Physical Design Flow......................100 6.1.1 Flow overview .........................100 6.1.2 VCTA Grouping ........................101 6.1.3 VCTA Place ..........................114 6.1.4 VCTA Routing.........................115 6.1.5 VCTA Layout Generation and Verification . 123 6.2 Results and Simulations........................125 6.2.1 Manual VCTA versus Automatic VCTA Flow . 125 6.2.2 Standard Flow versus VCTA Flow . 125 6.3 Conclusion ...............................130 7 FOCSI Layout Regularity Metric 133 7.1 FOCSI formulation...........................134 7.1.1 Problem Statement.......................134 7.1.2 Layout Regularity Definition . 135 iv CONTENTS 7.1.3 FOCSI Proposal ........................136 7.1.4 Single Layout Layer FOCSI..................137 7.1.5 Complete Layout FOCSI ...................137 7.2 FOCSI for single layers.........................138 7.2.1 Granularities considered....................138 7.2.2 ISCAS'85 layout results....................138 7.3 FOCSI for the complete layout ....................144 7.3.1 FOCSI Layout Area sizing selection . 145 7.3.2 ISCAS'85 layout results....................146 7.4 FOCSI regularity and variability ...................148 7.4.1 Variability model........................148 7.4.2 ISCAS'85 layout results....................150 7.5 Conclusion ...............................152 8 Conclusion 155 8.1 Summary of contributions.......................156 8.2 Future works ..............................157 Bibliography 161 List of Figures 169 List of Tables 172 Acknowledgments The thesis started thanks to the collaboration project \Variations-Aware Cir- cuit Designs for Microprocessors" between the Intel Barcelona Research Cen- ter and the Electronic Engineering Department of the Universitat Polit`ecnica de Catalunya. Then it was supported by the 2008 FI-B 00557 grant from the Generalitat de Catalunya and after by the FPU AP2007-04125 grant from the Spanish Ministry of Education and Science, the European Community's Seventh Framework Programme (FP7/2007-2013) under grant agreement number 248538 (Synaptic project) and by MODERN project of the Spanish Ministry of Science and Innovation (ENIAC-120003 and PLE2009-0024). I would like also to thank the HiPICS research group (SGR 1497) from the Electronic Engineering Department and the ARCO research group (SGR 1250) from the Computer Architecture Department, both from the Universitat Polit`ecnicade Catalunya, the Barcelona Supercomputing Center, and the Centre Suisse d'Electronique´ et de Microtechnique (CSEM), from Neuch^atelin Switzer- land, that helped me during my thesis. v Abstract In nowadays nanometer technology nodes, the semiconductor industry has to deal with the new challenges associated to technology scaling. On one hand, process developers face increasing manufacturing cost and variability, but also decreasing manufacturing yield. On the other hand, circuit designers and elec- tronic design automation (EDA) developers have to reduce design turnaround time and provide the tools to cope with increasing design complexity and reduce the time-to-market. In this scenario, closer collaboration between all the actors involved is required. New approaches considering both design and manufacturing need to be explored. These are the so called design for manufacturability (DFM) techniques. A DFM trend that is becoming dominant is to make circuit layouts more regular and repetitive. The regular layout fabrics are based on the configuration of a simplified mask set, therefore reducing the manufacturing cost. Moreover, a reduced number of layout patterns is used, allowing better process variabil- ity control and optimization. Hence, regularity reduces layout complexity and therefore design complexity, allowing faster time-to-market. In this thesis, we explore forcing maximum layout regularity focusing on future technology nodes, with increasing design and manufacturability issues, where we expect layout regularity to be mandatory. With this objective, we have developed a new regular layout fabric called Via-Configurable Transistor Array (VCTA). The physical design is fully explained involving layout and geometrical vii viii ABSTRACT considerations for transistors and interconnects. Initially, VCTA layouts developed manually have been evaluated in terms of manufacturability, but also in terms of area, energy and delay. For digital design, 32-bit binary adders designed with VCTA have been compared to standard cell layouts. For analog design, a delay-locked loop design using VCTA has been compared to its full custom version. We have also developed a physical synthesis tool that allows us to obtain VCTA circuit layouts in an automated way. Developing our own automation tool lets us controlling all the decisions made during the physical design flow to ensure that maximum layout regularity is respected. In this case the work is based on several algorithms, for instance for routing, that we have oriented to the area optimization of the layouts. Finally, in order to demonstrate the benefits of layout regularity, we have proposed a new layout regularity metric called Fixed Origin Corner Square In- spection (FOCSI). It is based on the geometrical inspection of the patterns in the layouts and it allows designers to compare regularity of designs but also how their regularity will impact their manufacturability. The FOCSI layout analysis tool can be used to optimize manufacturability. Chapter 1 Introduction Integrated circuits are more and more present in our life. From personal com- puters to smart-phones, or hidden electronics in cars, we are all using integrated circuits in our daily life. There are infinite examples. As layout minimum fea- ture sizes shrink, more elements can be integrated in a single chip allowing new applications and capabilities. However, this is a challenging trend that requires enormous efforts from the semiconductor industry including manufacturers, de- signers and electronic design automation (EDA) developers. In section 1.1 we first present an historical overview of technology scaling. Then, in section 1.2 we explain the integrated circuit manufacturing flow. In section