AMD Confidential – Advance Information Socket AM3 Processor Functional Data Sheet Publication # 40778 Revision: 1.13 Issue Date: January 2009 Advanced Micro Devices AMD Confidential – Advance Information © 2007 – 2009 Advanced Micro Devices, Inc. All rights reserved. The contents of this document are provided in connection with Advanced Micro Devices, Inc. (“AMD”) products. AMD makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. The information contained herein may be of a preliminary or advance nature and is subject to change without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this publication. 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HyperTransport is a licensed trademark of the HyperTransport Technology Consortium. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. AMD Confidential – Advance Information PID: 40778 Rev. 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet Contents Revision History . 6 1 Pins . 7 1.1 Connection Diagram (Left Half) . 7 1.2 Connection Diagram (Right Half) . 8 1.3 Pin Types . 9 1.4 Pin Descriptions . 9 1.5 Alphabetical Pin List . 13 1.6 Color-Coded Connection Diagram (Left Half) . 18 1.7 Color-Coded Connection Diagram (Right Half) . 19 2 Package Specifications . 20 2.1 Mechanical Loading for Lidded Parts . 20 2.2 Package Insertions . 20 2.3 Package Diagram . 21 Contents 3 AMD Confidential – Advance Information PID: 40778 Rev. 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet List of Figures Figure 1. Connection Diagram (Left Half) .........................................................................................7 Figure 2. Connection Diagram (Right Half) ......................................................................................8 Figure 3. Color-Coded Connection Diagram (Left Half) .................................................................18 Figure 4. Color-Coded Connection Diagram (Right Half) ...............................................................19 Figure 5. Organic Micro Pin Grid Array Package(UOF): Top, Side, and Bottom Views (Lidded) .............................................................................................................................21 4 List of Figures AMD Confidential – Advance Information PID: 40778 Rev. 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet List of Tables Table 1. Pin Types . 9 Table 2. HyperTransport™ Technology Pin Descriptions . 9 Table 3. DDR2 SDRAM Memory Interface Pin Descriptions (Supports DDR2 and DDR3) . 10 Table 4. Clock Pin Descriptions . 10 Table 5. Thermal Observation/Control Pin Descriptions . 11 Table 6. Power Supply/Voltage Regulator Interface Pin Descriptions . 11 Table 7. JTAG Pin Descriptions . 12 Table 8. Debug Pin Descriptions . 12 Table 9. Miscellaneous Pin Descriptions . 12 Table 10. Mechanical Loading for Lidded Parts . 20 Table 11. Recommended Number of Insertions . 20 List of Tables 5 AMD Confidential – Advance Information PID: 40778 Rev. 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet Revision History Date Revision Description January 2009 1.13 Third NDA release. • M_VDDIO_PWRGD changed to not supported. (See Table 3 on page 10.) June 2008 1.11 Second NDA release. • Added MA/B_EVENT_L pins. • Added NP/VSS and NP/RSVD pins. August 2007 1.07 Initial NDA release. Revision History 6 AMD Confidential – Advance Information PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet 1Pins 1.1 Connection Diagram (Left Half) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 MB_DATA[1 MB_DATA[6 MB_DATA[2 MB_DATA[8 A VOID VOID VSS VDDNB DBREQ_L VDDNB VSS CLKIN_H VSS TEST25_H VSS VDDR A ] ] ] ] MB_DATA[7 B VOID NP/ RSVD VDD VSS VDDNB DBRDY VDDNB CLKIN_L VSS TEST25_L VSS VDDR MB_DM[0] VSS VSS B ] MB_DQS_L[ MB_DQS_H[ MB_DATA[3 MB_DATA[1 C SVC/ VID[3] VDD VSS VDD TEST14 VDDNB RESET_L VDDNB PWROK VDDA TEST29_H VDDR C 0] 0] ] 3] MB_DATA[0 MB_DATA[1 D VID[4] VID[5] VDD TEST8 VDD TEST17 VDDNB LDTSTOP_L VDDNB VDDA TEST29_L VDDR VSS VSS D ] 2] PVIEN/ VID[ VDDR_SENS MB_DATA[5 MA_DATA[1 MA_DATA[6 MA_DATA[2 E VID[0] SVD/ VID[2] VDD TEST7 VDD TEST16 VDDNB TEST18 VDDNB VSS E 1] E ] ] ] ] M_VDDIO_P MB_DATA[4 MA_DQS_H[ F PSI_L RSVD VSS VDD TEST9 VDD TEST15 VDDNB TEST19 VDDNB M_VREF VSS VSS F WRGD ] 0] VDDNB_FB_ VDDNB_FB_ CORE_TYP MA_DATA[5 MA_DATA[0 MA_DQS_L[ MA_DATA[7 G VDD_FB_L VDD_FB_H VDD TEST10 VDD VSS VDDNB VSS VDDNB G L H E ] ] 0] ] MA_DATA[4 H VLDT_B VLDT_B VOID VOID VLDT_B VLDT_B VDD VSS TEST28_L VSS VDD VSS VSS MA_DM[0] VSS H ] L0_CADIN_ L0_CADIN_L L0_CADI N_ L0_CADI N_ J VSS VSS VSS VDD VSS TEST28_H VSS VDD VSS VDD VSS VDD J H[1] [0] H[0] H[8] L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CADIN_L K VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS K [1] H[9] [9] [8] L0_CADIN_ L0_CADIN_L L0_CADI N_ L0_CADI N_ L VDD VDD VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDL H[3] [2] H[2] H[10] L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CADIN_L M VDD VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS M [3] H[ 11] [11] [10] L0_CADIN_ L0_CLKI N_L L0_CLKIN_H L0_CLKIN_H N VSS VSS VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDN H[4] [0] [0] [1] L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CLKIN_L P VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS P [4] H[ 12] [12] [1] L0_CADIN_ L0_CADIN_L L0_CADI N_ L0_CADI N_ R VDD VDD VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDR H[6] [5] H[5] H[13] L0_CADIN_L L0_CADIN_ L0_CADIN_L L0_CADIN_L T VDD VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS T [6] H[ 14] [14] [13] L0_CTLIN_H L0_CADIN_L L0_CADI N_ L0_CADI N_ U VSS VSS VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDU [0] [7] H[7] H[15] L0_CTLIN_L L0_CTLIN_H L0_CTLI N_L L0_CADIN_L V VSS VSS HTREF0 HTREF1 VDD VSS VDD VSS VDD VSS VDD VSS V [0] [1] [1] [15] L0_CADOUT L0_CTLOUT L0_CTLOUT L0_CTLOUT W VDD VDD VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDW _L[7] _H[0] _L[0] _L[1] L0_CADOUT L0_CADOUT L0_CADOUT L0_CTLOUT Y VDD VDD VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Y _H[ 7] _L[15] _H[15] _H[1] L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT AA VSS VSS VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDAA _L[5] _H[6] _L[6] _L[14] L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT AB VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS AB _H[ 5] _L[13] _H[13] _H[14] L0_CLKOUT L0_CADOUT L0_CADOUT L0_CADOUT AC VDD VDD VSSVDDVSSVDDVSSVDDVSSVDDVSSVDDAC _L[0] _H[4] _L[4] _L[12] L0_CLKOUT L0_CLKOUT L0_CLKOUT L0_CADOUT MA_DATA[5 MA_DQS_H[ AD VDD VDD VDD VSS VDD VSS VDD VSS VSS VSS AD _H[0] _L[1] _H[1] _H[12] 9] 7] L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MA_DATA[5 MA_DATA[6 MA_DQS_L[ MA_DATA[5 AE VSS VSS NP/ VSS VOID VOID VDD VSS VDD AE _L[2] _H[3] _L[3] _L[11] 8] 3] 7] 6] L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MB_DATA[5 AF VSS VSS VDD VSS VDD VSS VDD VSS VSS MA_DM[7] VSS AF _H[ 2] _L[10] _H[10] _H[11] 9] L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MB_DATA[5 MA_DATA[6 MA_DATA[5 MA_DATA[6 AG VDD VDD VDD THERMDA THERMDC VSS VSS VDDR AG _L[0] _H[1] _L[1] _L[9] 8] 2] 7] 1] L0_CADOUT L0_CADOUT L0_CADOUT L0_CADOUT MB_DATA[6 MB_DATA[5 AH VDD VDD TEST3 TEST23 TEST12 TCK M_ZN VDDR VSS VSS AH _H[ 0] _L[8] _H[8] _H[9] 3] 1] MB_DQS_L[ MB_DATA[6 MB_DATA[5 AJ VLDT_A VLDT_A VLDT_A VLDT_A TEST6 TEST2 TEST13 TEST20 TEST22 TRST_L M_ZP VDDR MB_DM[7] AJ 7] 0] 0] THERMTRI VDDIO_FB_ MB_DQS_H[ MB_DATA[5 AK VOID VSS RSVD SA[0] TEST26 SID TEST24 TEST27 TDO VDDR VSS VSS AK P_L H 7] 6] CPU_PRES PROCHOT_ VDDIO_FB_ MB_DATA[6 MB_DATA[5 MB_DATA[6 MB_DATA[5 AL VOID VOID A LE RT _L V SS SI C TEST21 TMS TDI VDDR AL ENT_L L L 2] 7] 1] 5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 1. Connection Diagram (Left Half) Pins 7 AMD Confidential – Advance Information PID:40778 Rev 1.13 – January 2009 Socket AM3 Processor Functional Data Sheet 1.2 Connection Diagram (Right Half) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 MB_DATA[9 MB_CLK_H[ MB_CLK_L[1 MB_DATA[1 MB_DATA[1 MB_DATA[1 MB_DATA[2 MB_DATA[2 MB_DATA[1 MB_DATA[2 MB_DATA[2 MB_DATA[2 A MB_DM[2] VOID VOID A ] 1] ] 4] 0] 6] 2] 3] 9] 8] 4] 5] MB_RESET_ MB_DATA[1 MB_DATA[1 MB_DATA[1 MB_DATA[2 B MB_DM[1] VSS VSS VSS VSS VSS VSS MA_DM[3] VSS VOID B L 5] 7] 8] 9] MB_DQS_L[1 MB_CLK_H[ MB_DATA[1 MB_DATA[2 MB_DQS_L[2 MB_DQS_H[ MA_DQS_H[ MA_DATA[1 MA_DATA[2 MA_DATA[2 MA_DQS_L[3 MB_DQS_L[3 C RSVD RSVD MB_DM[3] C ] 0] 1] 1] ] 2] 2] 8] 8] 5] ] ] MB_DQS_H[ MB_CLK_L[0 MB_DATA[2 MA_DATA[2 MA_DQS_L[2 MA_DATA[2 MA_DQS_H[ MB_DQS_H[ D VSS VSS VSS VSS VSS VSS VSS D 1] ] 0] 0] ] 9] 3] 3] MA_DATA[8 MA_DQS_H[ MA_RESET_ MA_DATA[1 MA_DATA[1 MA_DATA[2 MA_DATA[2 MA_DATA[1 MA_DATA[2 MA_DATA[3 MA_DATA[3 MB_DATA[3 MB_DATA[3 E MA_DM[1] MA_DM[2] E ] 1] L 4] 5] 1]