Clock Jitter Effects on the Performance of ADC Devices Roberto J. Vega Luis Geraldo P. Meloni Universidade Estadual de Campinas - UNICAMP Universidade Estadual de Campinas - UNICAMP P.O. Box 05 - 13083-852 P.O. Box 05 - 13083-852 Campinas - SP - Brazil Campinas - SP - Brazil [email protected] [email protected] Karlo G. Lenzi Centro de Pesquisa e Desenvolvimento em Telecomunicac¸oes˜ - CPqD P.O. Box 05 - 13083-852 Campinas - SP - Brazil [email protected] Abstract— This paper aims to demonstrate the effect of jitter power near the full scale of the ADC, the noise power is on the performance of Analog-to-digital converters and how computed by all FFT bins except the DC bin value (it is it degrades the quality of the signal being sampled. If not common to exclude up to 8 bins after the DC zero-bin to carefully controlled, jitter effects on data acquisition may severely impacted the outcome of the sampling process. This analysis avoid any spectral leakage of the DC component). is of great importance for applications that demands a very This measure includes the effect of all types of noise, the good signal to noise ratio, such as high-performance wireless distortion and harmonics introduced by the converter. The rms standards, such as DTV, WiMAX and LTE. error is given by (1), as defined by IEEE standard [5], where Index Terms— ADC Performance, Jitter, Phase Noise, SNR. J is an exact integer multiple of fs=N: I. INTRODUCTION 1 s X = jX(k)j2 (1) With the advance of the technology and the migration of the rms N signal processing from analog to digital, the use of analog-to- k6=0;J;N−J digital converters (ADC) became essential. This conversion SINAD is the ratio between the rms level of the input is not free errors. These errors can have a major influence sinusoid and the rms, usually expressed in dBc. anufactures on overall system performance. In the previous paper [1], commonly plot SINAD as a function of frequency to shows it was found divergence between the simulations and the high frequency device degradation [2], since it represents the measurements of approximately about 2 dB, which were ADC overall performance (including all types of noise and attributed to the clock jitter, aperture time and electromagnetic distortions). interference effects present in the printed circuit board (PCB). This paper is an extension of [1], where it is shown theo- B. Total Harmonic Distortion - THD retical aspects, simulation and measurements of the sampling The total harmonic distortion is the ratio of the rms value clock. These performance metrics are very important when of the input sinusoid to the mean value of the first main har- one wants to assess the quality of and ADC device. The main monics produced by the analog-to-digital conversion. Practical goal of this paper is to offer a study of the effects of jitter in number of harmonics is 6 [2], although IEEE standard use ADC performance. other default value [5]. II. METRICS USED TO EVALUATE THE ADC Although the quantity of harmonics considered in the PERFORMANCE computation may change, the first and the second harmonic In this section, common measurements of analog-to-digital distortion will always be specified by manufactures, since they conversion performance are reviewed. These metrics are used tend to be the largest ones. This metric is relevant because it on experimental results with a commercial analog-to-digital measures the ADC nonlinearity intrinsic to the converter as converter on the next section. Other important measure is the well as external conditioning signal circuitry. For high-speed thermal noise salso simulated, although not presented here, it instrumentation and RF applications this is the most important may be found at [4]. figure of merit, since it includes out-of-band distortions. A. Signal to Noise Ratio plus Distortion - SINAD C. SNR due to quantization noise One of the most important ADC metrics is called SINAD - The Fig. 1 shows an illustration a uniform memoryless Signal-to-Noise Ratio plus Distortion. Using as input a sinus midrise quantization and illustrates deterministic nature of the p noise q. As the number of levels L of the ADC is large, a the pdf is also 2 [3], so the maximum SNR for a sine-wave good supposition is to consider the q power density function is given by: (pdf) as uniform inside an input step size δ: SNR (db) = 6:0206R + 1:7609 (10) 1 δ q P (q) = ; j q |≤ (2) p δ 2 Another important parameter for frequency analysis is called So, the minimum variance of the quantization error is: DFT noise floor. The DFT may also be considered a bank of matched filters, each filter defined by its basis function of Z δ=2 δ2 the DFT as band-pass filters and one low-pass DC filter. In σ2 = q2P (q); dq = (3) qmin p practical applications, the input signal is usually band-limited −δ=2 12 and sampled at higher frequency than Nyquist. And the minimum rms quantization error: In these situation it is possible to filter the noise outside the δ δ band of interest improving the SNR which is called processing σqmin = p = p (4) gain [2]. Processing techniques such as oversampling, quanti- 12 2 3 zation noise shaping and filtering are the basis of sigma-delta converters [2]. The filter selectivity of the DFT rises with the DFT size. Here we are using a coherent signal, a sine-wave, with the DFT basis functions. The DFT noise floor will be function of the DFT size, reducing with N much bellow the sinusoid power. For computing the processing gain, one can use a simple rule of three: if we consider all digital frequencies, all quan- 2 tization noise σq must be taken in computing the SNR up to fN , for a sinusoid coherent with a DFT band-pass filter B σ2 with bandwidth W , the noise will be qg , a small fraction of the overall noise. Therefore, rewriting (7) and redoing the calculations: 2 Bw σ = σ 2 qg q (11) min fN The processing gain can be expressed by replacing (3) and Fig. 1. Uniform quantization with 8 levels (L = 8) [1]. (4), defining (8): This is a white noise that spreads on the whole band up fN to the Nyquist frequency fN . The step size δ may also be SNRg = 6:0206R + 1:7609 + 10 log10 (12) Bw expressed by the number of levels L, i.e., ththe number of bits R of the ADC: Where fN = fs=2. One can consider the DFT band-pass bandwidth Bw = fs=N, , which increases as function of the 2x 2x δ = ol = ol (5) DFT size: L 2R Where xol = xmax is the maximum peak value of the input N SNR = 6:0206R + 1:7609 + 10 log (13) signal without overload. From (3), (4) and (5): g 10 2 2−2Rx2 Thus, to improve the noise floor by 3 dB, it is necessary σ2 = max (6) qmin 3 to double the DFT size. Considering a coherent-sampling, it xmax would also imply an oversampling effect of 2 times of the fl = (7) input signal. σx This ratio is called loading factor [2], where σx is the rms D. Effective Number of Bits - ENOB input value. From (4) and (5), gives the maximum SNR, as it There is no common definition for the effective number of is used the minimum variance of the quantization noise. bits (ENOB). Here, it is used the definition proposed by IEC [1], in which ENOB is directly computed from SINAD as σ2 σ2 22R x x follows: SNRq = = −2R 2 = (8) σ 2 2 x =3 fl=3 qmin max SINAD − 1:76 SNR (db) = 6:0206R − 10 log (f 2=3) (9) ENOB = (14) q 10 l 6:02 For ap sine-wave with peak value equalp to xol, the rms value This represents a practical limit of the ADC resolution due is xol= 2, so the loading factor is fl = 2. The factor fl for to inherent noise and linearity errors, and it aims to specify the number of effective bits of a digitalized signal above the noise This SNR due jitter must include the quantization noise floor, giving the ADC accuracy at a specific input frequency calculed by (9). The overall SNR achieved (SNRtotal) [4], and sampling rate. that includes both limitations can be expressed by: This equation is easily computed by substituting SINAD in (9) and solving it for R, assuming an input at full-scale. q ! SNRq SNRJ To compensate any attenuation on the input signal applied to − 10 − 10 SNRtotal(dB) = −20 log 10 + 10 protect it from clipping, the following normalization of the FS amplitude by the input amplitude should be used: (21) SINAD − 1:76 + 20log( F Samplitude ) F. Phase noise ENOB = Inputamplitude (15) 6:02 To measure jitter directly is very difficult because the E. Sampling error due to jitter fluctuation is small with respect to the sample. Unlike the jitter, the phase noise of the clock signal is easier to measure. The jitter is the time variation for each clock cycle. This A common spectrum analyzer can be used. variation is usually generated by thermal noise due electrical current. The sample time variations generate voltage errors as The phase noise of the clock signal is the phase modulation shown in Fig. 2. This variation is called aperture jitter [2] and due the time-domain instabilities (or jitter). From (16), the is usually measured in rms picoseconds.