Pontifícia Universidade Católica do Rio Grande do Sul Faculdade de Informática Pós-Graduação em Ciência da Computação Non-Volatile Memory: Emerging Technologies And Their Impacts on Memory Systems Taciano Perez, César A. F. De Rose Technical Report Nº 060 Porto Alegre,PPGCC September 2010 Abstract For almost 30 years, computer memory systems have been essentially the same: volatile, high speed memory technologies like SRAM and DRAM used for cache and main memory; magnetic disks for high-end data storage; and persistent, low speed ash memory for storage with low capacity/low energy consumption requirements such as embedded/mobile devices. Today we watch the emergence of new non-volatile memory technologies, such as Phase- Change RAM (PCRAM), Magnetoresistive RAM (MRAM) and Resistive RAM (RRAM), that promise to radically change the landscape of memory systems. This paper summarizes the current state of memory system design, presents these new memory technologies and surveys the current proposals on how to apply these technologies to improve memory hierarchies. We conclude that the introduction of these new technologies will probably result in more complex memory hierarchies, but is likely to allow the construction of memory chips that are non-volatile, low-energy and have density and latency close to or better than current DRAM chips, improving performance/eciency and allowing memory systems to continue to scale up. 2 Contents ABSTRACT 2 Chapter 1: Introduction 5 Chapter 2: Memory Systems: Current Landscape 6 2.1 Processor Cache: SRAM . .7 2.2 Main Memory: DRAM . .9 2.3 Persistent Storage: Disk, Flash . 11 2.4 Limitations of Current Memory Technologies . 13 2.4.1 A Note on Energy-Proportional Computing . 15 Chapter 3: Emerging Memory Technologies 17 3.1 Phase-Change RAM (PCRAM) . 17 3.2 Resistive RAM (RRAM) . 18 3.2.1 Memristor . 19 3.3 Magnetoresistive RAM (MRAM) . 21 3.3.1 STT-RAM . 22 3.4 Comparison Between Memory Technologies . 23 Chapter 4: Impacts on Memory Systems 25 4.1 Cache . 25 4.1.1 MRAM as L2 and L3 cache . 25 4.1.2 Hybrid SRAM/MRAM and SRAM/PCRAM as L2 and L3 caches . 26 4.1.3 Fault-tolerant architecture for NVM caches . 27 4.2 Main Memory . 27 4.2.1 Pioneer work: ash-based main memory . 27 4.2.2 PCRAM as main memory . 28 4.2.2.1 Improving latency, energy and endurance through buer organization and partial writes . 28 3 4.2.2.2 Improving endurance and energy consumption through 3D stacking . 29 4.2.2.3 Combining both approaches . 30 4.2.3 Hybrid PCRAM-DRAM main memory . 30 4.2.3.1 Qureshi et al. hybrid approach . 30 4.2.3.2 FLAM hybrid approach . 31 4.2.3.3 BPRAM hybrid approach . 32 4.3 Persistent Storage . 33 4.3.1 PCRAM as a disk replacement . 33 4.3.2 PCRAM or STT-MRAM as disk replacement . 34 4.4 Other Memory Systems . 36 4.4.1 PCRAM for MPP checkpointing . 36 4.4.2 MRAM in GPU. 37 4.5 Operating System . 37 4.5.1 OS improvements to support FLAM. 37 4.5.2 BPFS le system . 38 Chapter 5: Conclusion 40 BIBLIOGRAPHY 42 4 1 Introduction For almost 30 years the memory hierarchy used in computer design has been essentially the same: volatile, high speed memory technologies like SRAM and DRAM used for cache and main memory; magnetic disks for high-end data storage; and persistent, low speed ash memory for storage with low capacity/low energy consumption requirements, such as embedded/mobile devices [13]. Today we watch the emergence of new memory technologies under research that promise to change signicantly the landscape of memory systems. Non-Volatile Memory (NVM) technologies such as Phase-Change RAM (PCRAM), Magnetic RAM (MRAM) and Re- sistive RAM (RRAM) will possibly enable memory chips that are non-volatile, require low-energy and have density and latency closer to current DRAM chips [4]. Even though most of these technologies are still in early prototyping stages, their ex- pected properties in terms of density, latency, energy and endurance are already estimated. Based on these estimations, several papers have been published proposing practical appli- cations for these new NVM technologies. These papers provide initial insight on what the impacts on memory systems should be if such technologies evolve to be competitive in the market. The memory system is one of the most critical components of modern computers. It has attained a high level of complexity due to the many layers involved in memory hierarchy: application software, operating system, cache, main memory and disk. Any relevant change in one level of the memory hierarchy (such as the introduction of the aforementioned NVM technologies) can potentially impact several other layers and overall system behavior. For this reason, it is essential to consider the dierent possible scenarios for using these new memory technologies from a broad perspective. There are several studies that explore the impact of new NVM technologies on specic parts of the memory system, but we are not aware of any comprehensive survey of the literature on potential applications of new NVM technologies. The intention of the present work is to provide such comprehensive survey. To attain this goal, it is divided in four sections: 1. A review of the current technologies used in memory systems. 2. A presentation of the most relevant NVM technologies currently under research: PCRAM, RRAM and MRAM. 3. A survey of the practical applications proposed so far for these technologies. 4. A discussion of their implications for memory system design. 5 2 Memory Systems: Current Landscape In order to discuss the emergent NVM technologies, we need to start by summarizing the current state of memory systems. This is a well-known subject, and we have extracted most of the information present in this section from the comprehensive textbook Memory Systems: Cache, DRAM, Disk by Bruce Jacob, Spencer W. Ng and David T. Wang [13] and Ulrich Drepper's online paper What Every Programmer Should Know About Memory [9]. An ideal memory system would be fast, cheap, persistent and big (highly dense). Until now, all known memory/storage technologies address only some of these characteristics. Static RAM (SRAM) is very fast, but it's expensive, has low density and is not persistent. Dynamic RAM (DRAM) has better densities and is cheaper (but still expensive) at the cost of being a little slower, and it's not persistent as well. Disks are cheap, highly dense and persistent, but very slow. Flash memory is between DRAM and disk; it is a persistent solid-state memory with higher densities than DRAM, but its write latency is much higher than the latter. Fortunately, it is possible to design a memory system that incorporates all these dier- ent technologies in a single memory hierarchy. Such hierarchy allows the creation of a system that approaches the performance of the fastest component, the cost of the cheapest component and energy consumption of the most power-ecient component. This is pos- sible due to a phenomenon known as locality of reference, so named because memory references tend to be localized in time and space. This can be so summarized: If you use something once, you are likely to use it again (temporal locality). If you use something once, you are likely to use its neighbor (spatial locality) [13]. This phenomenon can be exploited by creating dierent memory levels; the rst levels are smaller and more expensive, but have fastest access, and the other layers are progressively bigger and cheaper, but have slower access times. Appropriate heuristics are then applied to decide which data will be accessed more often and place them at the rst levels, and move the data down on the hierarchy as it ceases to be used frequently. Figure 2.1 depicts the concept of memory hierarchy. For at least the last 30 years, we have been building memory hierarchies that rely on SRAM for caches, DRAM for main memory and disk or ash as persistent storage. In the next sections we will describe these technologies in more detail. 6 Figure 2.1: Diagram illustrating the concept of memory hierarchy. 2.1 Processor Cache: SRAM Caches are used to store frequently used information close to who needs it. They are used at several layers of computer architecture, but probably the most important are processor caches. In order to explore locality of reference, we need to place memory with very fast access close to the processor. The result is that processor caches reside between the processor and main memory, as depicted in Figure 2.2a. Processor caches usually are transparent caches, meaning that the same addressing space is shared between the cache and the backing storage. When the processor asks for the contents of a specic memory address, these contents are rst searched in the cache. If they are found (a cache hit), they are immediately returned. If they are not found (a cache miss), the memory system goes on to the next hierarchy level (e.g., main memory) and fetches the result. If there is a high probability that the returned result will be used again in the future, it is stored in the cache as well. Diverse heuristics can be used to manage cache content [13]. The speed of a cache is typically in inverse proportion to its size. This happens because the more addresses a cache can contain, more search needs to be done in order to determine whether there is a cache hit or miss. For this reason, modern computers have more than one cache level, frequently up to 3 levels.