ADVANCED CHIP MANUFACTURING WITH NEW MATERIALS ASM International Analyst and Investor Technology Seminar Semicon West July 13, 2016 CAUTIONARY NOTE Cautionary Note Regarding Forward-Looking Statements: All matters discussed in this press release, except for any historical data, are forward-looking statements. Forward- looking statements involve risks and uncertainties that could cause actual results to differ materially from those in the forward-lookingstatements.Theseinclude,butarenotlimited to, economic conditions and trends in the semiconductor industry generally and the timing of the industry cycles specifically, currency fluctuations, corporate transactions, financing and liquidity matters, the success of restructurings, the timing of significant orders, market acceptance of new products, competitive factors, litigation involving intellectual property, shareholders or other issues, commercialandeconomicdisruptionduetonatural disasters, terrorist activity, armed conflict orpoliticalinstability,epidemicsandotherrisks indicated in the Company's reports and financial statements. The Company assumes no obligation nor intends to update or revise any forward-looking statements to reflect future developments or circumstances. | 2 OUTLINE › Exponentials in the industry › New Materials and 3D: Moore’s law enablers › ASM and New Materials • ALD as enabler of new materials • ASM New Materials development strategy • ALD supply chain components › ASM Products and selected applications › Summary and Conclusions | 3 OUTLINE › Exponentials in the industry › New Materials and 3D: Moore’s law enablers › ASM and New Materials • ALD as enabler of new materials • ASM New Materials development strategy • ALD supply chain components › ASM Products and selected applications › Summary and Conclusions | 4 EXPONENTIALS IN THE INDUSTRY Moore’s Law Density (xtor/chip) Memory Density (Mb/mm2) Complexity (Mask Count) Top: G. Moore, Electronics (1965); www.intel.com. | 5 Bottom: ASM; Techinsights and ASM (2013); OUTLINE › Exponentials in the industry › New Materials and 3D: Moore’s law enablers › ASM and New Materials • ALD as enabler of new materials • ASM New Materials development strategy • ALD supply chain components › ASM Products and selected applications › Summary and Conclusions | 6 SCALING IS INCREASINGLY ENABLED BY NEW MATERIALS AND 3D TECHNOLOGIES 19901995 2000 2005 2010 2015 2020 2025 Scaling enabled by Litho Patterning IEDM 2002 Spacers IEDM 2003 Scaling enabled by Materials IEDM 2007 High-mobility Low-k Materials Strained Si Scaling enabled by 3D High-k FinFET 3D TSV 3D Memory GAA | 7 Confidential and Proprietary Information SCALING BY MATERIALS AND 3D 2011 • Density scaling (continuing Moore’s law) driving towards higher mobility materials and alternate device architectures • Future systems will SiGe Si integrate much wider variety of materials and device structures ~2023 | 8 NEW MATERIALS AND PROCESSES: MOORE’S LAW ENABLERS Higher Capacitance, Lower Leakage Higher Mobility, Lower Resistance High-k / S/D metal gate High-k / contact Metal Gate DRAM, RF, STI decoupling STI Si capacitors Mitard et al., VLSI ‘16 Strain and new Channel Materials New metal contacts Less Cross Talk, Faster Interconnect Smaller Feature Sizes (C) Intel SDQP for N7 and N5 (Porous) Low-k Materials Improved Metals E. Altamirano-Sánchez et al., SPIE Newsroom, 14 May ’16 | 9 NEW MATERIALS: MOORE’S LAW ENABLERS sSOI/GeOI (IL: Interface Layer) Ge IL III‐V IL * GaN (PM: Patterning Materials) InSb InGaAs Ge STO Ru Other PM's Other PM's EUV EUV Co Co Si(C)P Si(C)P Patterning Related FDSOI FDSOI SiC SiC BEOL Air Air SiCO SiCO FEOL LaO LaO LT SiO LT SiO Starting Materials SiCN SiCN SiCN TiAlC MG TiAlC MG TiAlC MG ZrO ZrO ZrO (*): Projection Hf(Si)O Hf(Si)O Hf(Si)O AlO AlO AlO pSiOC pSiOC pSiOC SOI SOI SOI SiGe(B) SiGe(B) SiGe(B) TaO TaO TaO TaO SOG SOG SOG SOG SiOC SiOC SiOC SiOC Ta/TaN Ta/TaN Ta/TaN Ta/TaN Cu Cu Cu Cu SiOF SiOF SiOF SiOF TiSi TiSi TiSi TiSi TiSi PtSi PtSi PtSi PtSi PtSi TiW TiW TiW/TiN TiN TiN TiN WSi, MoSi WSi, WWSi, WW W W BPSG BPSG BPSG BPSG BPSG BPSG BPSG Al Al Al Al Al Al Al Al SiO, SiN SiO, SiN SiO, SiN SiO, SiN SiO, SiN SiO, SiN SiO, SiN SiO, SiN Si Si Si Si Si Si Si Si 1960 1970 1980 1990 2000 2010 2015 2020(*) | 10 10 OUTLINE › Exponentials in the industry › New Materials and 3D: Moore’s law enablers › ASM and New Materials • ALD as enabler of new materials • ASM New Materials development strategy • ALD supply chain components › ASM Products and selected applications › Summary and Conclusions | 11 ASM AND NEW MATERIALS › ASM technology focuses on enabling new materials and new device integration roadmaps 3D transistor formation (FinFET & beyond FinFET) DRAM, Flash –planar and 3D NAND - and emerging memory More than Moore / IoT applications (MEMS, Sensors, Power) › ALD (Atomic Layer Deposition) separates reactive precursors in time (or space), and grows materials one “atomic” layer at a time Superb control of uniformity, quality, and composition Conformal to any topography › Enabling high quality materials at lower temperatures high-k metal gates low temp spacers for multi-patterning Other emerging applications | 12 ALD AS ENABLER OF NEW MATERIALS - KEY STRENGTHS OF ALD Uniformity Step Coverage 42nm AlN 30.5 nm AlN 0.51% 3 0.25% Full range 43nm Interface Control Composition Control Excellent Atomically composition engineered control for interfaces to ternary alloys; optimize leakage all ALD current, reliability solution and work-functions demonstrated for GST Ritala, E/Pcos 2012; | 13 CRITICAL ALD SUPPLY CHAIN COMPONENTS Fundamental Process Integrated Final Product Productivity Capability Performance Process Capability Pre-cursors Reactors High productivity tools Pre-cursor Fab facilities, Delivery, Valves pumps & abatement and Vessels | 14 OUTLINE › Exponentials in the industry › New Materials and 3D: Moore’s law enablers › ASM and New Materials • ALD as enabler of new materials • ASM New Materials development strategy • ALD supply chain components › ASM Products and selected applications › Summary and Conclusions | 15 ASM PRODUCTS ALD › Pulsar® XP ALD for high-k Cross-flow reactor Solid source delivery system › EmerALD® XP Pulsar® XP ALD for metal gates Showerhead reactor EmerALD® XP | 16 16 FINFET CHALLENGES: ALD ENABLES FURTHER SCALING IN 3D Source: Intel •Materials properties and channel length must be uniform over fin height •Conformal coverage required •Aspect ratios increase going from 22nm to 14nm to 10nm • ALD technology has become critical for HK and MG layers | 17 EXTENDIBILITY OF HAFNIUM BASED OXIDES chipworks chipworks chipworks chipworks 45nm HK first RPMG 32 nm HK last RPMG 28nm HK first RPMG 22nm HK last RPMG Planar FET Planar FET Planar FET FinFET chipworks 14nm HK last RPMG FinFET 16 nm HK last RPMG FinFET | 18 ASM PRODUCTS PEALD AND PECVD ›XP8-DCM High productivity single wafer tool for both PEALD and PECVD applications Accommodates up to 8 chambers by DCM PEALD and PECVD can be integrated on the same platform DCM (Dual Chamber Module) | 19 ALD ENABLING LITHOGRAPHY: SPACER DEFINED DOUBLE/QUADRUPLE PATTERNING Pitch: P ALD SiO2 on resist 80nm Hard Mask Etch Pitch: 1/2 P 40nm In-situ trimming 2nd ALD Spacer Spacer Defined Double Patterning PEALD SiO2 Spacer (SDDP) with ALD in production since 3x nm DRAM and Flash Spacer Defined Quadruple Pattering (SDQP) in production for 1x nm Flash 2nd Anisotropic Etch SDDP/SDQP qualified with 10nm Logic Anisotropic Etch customers Key enablers brought by ALD •Uniformity: CD control •Low temperatures (<100C) Pitch: 1/2 P Pitch: 1/4 P 20nm •Good step coverage •Dense film •In-situ trimming capability •Extendible to other materialswith etch selectivity | 20 CD UNIFORMITY CONTROL Trimming SiODeposition Cond A Cond B Cond C Arbitrary Units Arbitrary Arbitrary Units Arbitrary Position on wafer [mm] Position on wafer [mm] After lithography After trimming After SiO deposition & etch Critical Critical Critical Dimension Dimension Dimension Position on wafer Position on wafer Position on wafer WiW uniformity is controlled by trimming and deposition Trimming and deposition can mitigate the initial non-uniform resist pattern, which is to help within wafer CD uniformity | 21 LINERS AND SPACERS FOR BEYOND 15nm FinFETs ALD SiO2 and Si3N4 permanent spacers Low temperature (260 ~ 550 C) Conformal High quality (low WER, low leakage current) 40nm pitch ALD SiO ALD SiN | 22 HIGH QUALITY SIO Single Wafer ALD › Conformal thickness deposition is necessary for high-AR trench › The film quality of the sidewall needs to be equal to that of top/blanket › Deliver required electrical performance Potential Applications: IO gate SiO Si Fin 4. FinFET I/O Transistor Gate Oxide Development of High-temperature ALD SiO | 23 METAL OXIDE ADVANCED HARD MASK FOR PATTERING ALD Mox Etching Hard Mask Photo Resist Mox Low/Tunable stress capable LT deposition: PR compatible Extension of etch selectivity portfolio 50 50 40 40 30 30 20 20 (Arb. Units) (Arb. (Arb. Units) (Arb. 10 10 Dry Etch Rate by Gas A Dry Etch Rate by Gas 0 Dry Etch Rate by Gas B 0 SiO 0.1 0.5 0.8 0.9 TiO SiO 0.1 0.5 0.8 0.9 TiO SiO SiO/Mox mix Mox SiO SiO/Mox mix Mox | 24 ADVANCED ALD DOPING FinFET requires conformal doping Limitations of conventional doping techniques like beam line: Low conformality (beam directionality, shadowing effect) Silicon damage Shadowing effect ALD Doping Benefits Conformal & no silicon damage Ion beam Hard Mask SiO2 Si 50nm BSG 2nm + cap 2nm un-doped region Si substrateDoped Oxide Anneal Oxide removal