Full text available at: http://dx.doi.org/10.1561/1000000016 Three-dimensional Integrated Circuits: Design, EDA, and Architecture Full text available at: http://dx.doi.org/10.1561/1000000016 Three-dimensional Integrated Circuits: Design, EDA, and Architecture Guangyu Sun Yibo Chen Xiangyu Dong Jin Ouyang Yuan Xie Pennsylvania State University USA fgsun, yxc236, xydong, jouyang, [email protected] Boston { Delft Full text available at: http://dx.doi.org/10.1561/1000000016 Foundations and Trends R in Electronic Design Automation Published, sold and distributed by: now Publishers Inc. PO Box 1024 Hanover, MA 02339 USA Tel. +1-781-985-4510 www.nowpublishers.com [email protected] Outside North America: now Publishers Inc. PO Box 179 2600 AD Delft The Netherlands Tel. +31-6-51115274 The preferred citation for this publication is G. Sun, Y. Chen, X. Dong, J. Ouyang and Y. Xie, Three-dimensional Integrated Circuits: Design, EDA, and Architec- ture, Foundations and Trends R in Electronic Design Automation, vol 5, nos 1{2, pp 1{151, 2011 ISBN: 978-1-60198-462-3 c 2011 G. Sun, Y. Chen, X. Dong, J. Ouyang and Y. Xie All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, mechanical, photocopying, recording or otherwise, without prior written permission of the publishers. Photocopying. In the USA: This journal is registered at the Copyright Clearance Cen- ter, Inc., 222 Rosewood Drive, Danvers, MA 01923. Authorization to photocopy items for internal or personal use, or the internal or personal use of specific clients, is granted by now Publishers Inc for users registered with the Copyright Clearance Center (CCC). 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Please apply to now Publishers, PO Box 179, 2600 AD Delft, The Netherlands, www.nowpublishers.com; e-mail: [email protected] Full text available at: http://dx.doi.org/10.1561/1000000016 Foundations and Trends R in Electronic Design Automation Volume 5 Issues 1{2, 2011 Editorial Board Editor-in-Chief: Sharad Malik Department of Electrical Engineering Princeton University Princeton, NJ 08544 Editors Robert K. Brayton (UC Berkeley) Raul Camposano (Synopsys) K.T. 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Full text available at: http://dx.doi.org/10.1561/1000000016 Foundations and Trends R in Electronic Design Automation Vol. 5, Nos. 1{2 (2011) 1{151 c 2011 G. Sun, Y. Chen, X. Dong, J. Ouyang and Y. Xie DOI: 10.1561/1000000016 Three-dimensional Integrated Circuits: Design, EDA, and Architecture Guangyu Sun, Yibo Chen, Xiangyu Dong, Jin Ouyang, Yuan Xie1 1 Pennsylvania State University, Computer Science and Engineering Department, University Park, PA 16802, USA, fgsun, yxc236, xydong, jouyang, [email protected] Abstract The emerging three-dimensional (3D) integration technology is one of the promising solutions to overcome the barriers in interconnection scal- ing, thereby offering an opportunity to continue performance improve- ments using CMOS technology. As the fabrication of 3D integrated circuits has become viable, developing CAD tools and architectural techniques are imperative for the successful adoption of 3D integration technology. In this article, we first give a brief introduction on the 3D integration technology, and then review the EDA challenges and solu- tions that can enable the adoption of 3D ICs, and finally present design and architectural techniques on the application of 3D ICs, including a survey of various approaches to design future 3D ICs, leveraging the benefits of fast latency, higher bandwidth, and heterogeneous integra- tion capability that are offered by 3D technology. Full text available at: http://dx.doi.org/10.1561/1000000016 Contents 1 Introduction 1 2 3D Integration Technology 3 2.1 The Impact of 3D Technology on 3D IC Design Partitioning 5 3 Benefits of 3D Integrated Circuits 7 3.1 Wire Length Reduction 7 3.2 Memory Bandwidth Improvement 9 3.3 Heterogenous Integration 11 3.4 Cost-effective Architecture 13 4 3D IC EDA Design Tools and Methodologies 15 4.1 Thermal Analysis for 3D ICs 15 4.2 Physical Design Tools and Algorithms for 3D ICs 20 4.3 3D Testing 34 4.4 3DCacti: an Early Analysis Tools for 3D Cache design 37 5 3D FPGA Design 47 5.1 FPGA Background 47 5.2 3D FPGA Design 48 5.3 PCM-Based 3D Non-Volatile FPGA 49 5.4 Summary 59 ix Full text available at: http://dx.doi.org/10.1561/1000000016 6 3D Architecture Exploration 61 6.1 Single-core Fine-Granularity Design 62 6.2 Multi-core Memory Stacking 69 6.3 3D Network-on-Chip 76 7 Cost Analysis for 3D ICs 87 7.1 Introduction 87 7.2 Early Design Estimation for 3D ICs 91 7.3 3D Cost Model 99 7.4 Cost Evaluation for Fully-Customized ASICs 106 7.5 Cost Evaluation for Many-Core Microprocessor Designs 114 7.6 3D IC Testing Cost Analysis 125 7.7 Conclusion 138 8 Challenges for 3D IC Design 141 Acknowledgments 143 References 145 Full text available at: http://dx.doi.org/10.1561/1000000016 1 Introduction With continued technology scaling, interconnection has emerged as the dominant source of circuit delay and power consumption. The reduc- tion of interconnect delays and power consumption are of paramount importance for deep-sub-micron designs. Three-dimensional integrated circuits (3D ICs) [1] are attractive options for overcoming the barriers in interconnection scaling, thereby offering an opportunity to continue performance improvements using CMOS technology. 3D integration technologies offer many benefits for future micropro- cessor designs. Such benefits include: (1) The reduction in interconnec- tion wire length, which results in improved performance and reduced power consumption; (2)Improved memory bandwidth, by stacking mem- ory on microprocessor cores with TSV connections between the memory layer and the core layer; (3) The support for realization of heterogeneous integration, which could result in novel architecture designs. (4)Smaller form factor, which results in higher packing density and smaller foot- print due to the addition of a third dimension to the conventional two dimensional layout, and potentially results in a lower cost design. This monograph first presents the background on 3D integration technologies, and shows the major benefits offered by 3D integration. 1 Full text available at: http://dx.doi.org/10.1561/1000000016 2 Introduction As a key part, EDA design tools and methodologies for 3D ICs are reviewed. The designs of 3D FPGAs and micro-architectures are then discussed, which leverage the benefits of fast latency, higher bandwidth, and heterogeneous integration capability that are offered by 3D tech- nologies. The cost of 3D integration is also analyzed in the last section. Full text available at: http://dx.doi.org/10.1561/1000000016 References [1] W. R. Davis, J. Wilson, S. Mick, et al. Demystifying 3D ICs: the pros and cons of going vertical. IEEE Design and Test of Computers, 22(6):498{510, 2005. [2] Y. Xie, G Loh, B Black, and K. Bernstein. Design space exploration for 3D architectures. ACM Journal of Emerging Technologies in Compuing Systems, 2006. [3] Yuan Xie, Jason Cong, and Sachin Sapatnekar. Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures. Springer, 2009. [4] Yuan Xie. Processor architecture design using 3D integration technology. In VLSI Design, 2010. VLSID '10. 23rd International Conference on, pages 446{451, jan. 2010. [5] P. Garrou. Handbook of 3D Integration: Technology and Applications using 3D Integrated Circuits, chapter Introduction to 3D Integration. Wiley-CVH, 2008. [6] J.W. Joyner, P. Zarkesh-Ha, and J.D. Meindl. A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC). In Proc. 14th Annual IEEE International ASIC/SOC Conference, September 2001. [7] Yuh-fang Tsai, Feng Wang, Yuan Xie, N. Vijaykrishnan, and M. J. Irwin. Design space exploration for three-dimensional cache. IEEE Transactions on Very Large Scale Integration Systems, 2008. [8] Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Vijaykrishnan Narayanan, and Mary Jane Irwin. Architecting microprocessor components in 3D design space. In Intl. Conf. on VLSI Design, pages 103{108, 2007. 145 Full text available at: http://dx.doi.org/10.1561/1000000016 146 References [9] Kiran Puttaswamy and Gabriel H.