An Effective Verification Solution for Modern Microprocessors by Ilya Wagner A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Computer Science and Engineering) in The University of Michigan 2008 Doctoral Committee: Assistant Professor Valeria M. Bertacco, Chair Professor Nilton O. Renno Associate Professor Todd M. Austin Associate Professor Scott Mahlke c Ilya Wagner 2008 All Rights Reserved To my Mom and Dad ii ACKNOWLEDGEMENTS I would like to thank my advisor Professor Valeria Bertacco, who guided me on the path towards my degree. For every project, paper and presentation that we worked on together she provided priceless advice, ensuring that the work was performed on time and with the best possible quality. I am also infinitely grateful to her for all the patience and tenacity with which she helped me improve my writing and presentation skills. I feel very fortunate to have her as my academic advisor, teacher and mentor. I would also like to thank my committee members: Professor Todd Austin, Professor Scott Mahlke and Professor Nilton Renno. Throughout the years of graduate school I’ve enjoyed working with Professor Austin personally on several projects and always appre- ciated his brilliant ideas and advise. Likewise, I’d like to thank Professor Nilton Renno who supervised the Mars Rover Design Team - an extracurricular project that have been a major part of my life for four years. Although I have not worked personally with Profes- sor Mahlke, I have always respected his opinion and advise, and would like to thank him for providing valuable comments that made the completion of this dissertation possible. Additionally, I thank Mark Brehob, one of the best teachers and lecturers I met in my life; it was his classes that sparked my interest to microprocessor design in the last year of un- dergraduate school. I am deeply grateful to the all the people who collaborated with me on several of the projects: Andrew DeOrio, Kai-hui Chang, Joseph Greathouse and David Ramos. I also would like to thank all of the fellow Computer Science and Engineering students, who did not formally work with me, yet have become my good friends: Steven Plaza, Smitha Shyam, Kypros Constantinides, Andreas Moustakas, Andrea Pellegrini, Jin Hu, Jeff Hao, David Papa, Jarrod Roy, David Roberts, Adam Bauserman, Debapriya Chatterjee, David Meisner, Shobana Sudhakar, Bashar Al-Rawi, James Anderson, Hector Garsia and Geoff Blake. To those of you who have graduated already and those who remain in the lab – I bid you farewell and the best of luck. Likewise, I thank my friends in Russia, who, despite of being far away, still remain in my heart. iii Finally, I’d like to thank my entire family, especially my brother Dmitriy and my sisters Vera and Anna, who always stood by me. I’d like to specially thank my sister-in-law Vita, whose help, hospitality and culinary skills I enjoyed on so many occasions, while living in Ann Arbor. I wish her the best of luck with her Ph.D. research and dissertation. Last, but not least, completion of this work would not be possible without the support of my mother and father who always encouraged me to follow the path of learning and discovery, supported me in the times of failure and celebrated my successes. iv PREFACE Over the past four decades microprocessors have come to be a vital and inseparable part of the modern world, becoming the digital brain of numerous electronic devices and gadgets that make today’s lifestyle possible. Processors are capable of performing com- putation at astonishingly high speeds and are extremely integrated, occupying only a few square centimeters of silicon die. However, this computational power comes at a price: the task of verifying a modern microprocessor and guaranteeing correctness of its operation is increasingly challenging, even for most established processor vendors. Always attempting to deliver higher performance to end-users, processor manufacturers are forced to design progressively more complex circuits and employ immense verification teams to eliminate critical design bugs in a timely manner. Unfortunately, too often size doesn’t seem to mat- ter in verification, as schedules continue to slipandmicroprocessorsfindtheirwaytothe marketplace with design errors. This work describes a novel verification framework targeting specifically today’s com- plex microprocessors. The scope of the work spans many levels of verification and dif- ferent phases of the processor life-cycle, from validation of individual sub-modules to complete multi-core system, and from pre-silicon design verification to in-the-field hard- ware patching. In particular, our StressTest and MCjammer approaches enable efficient generation of high-quality tests at the pre-silicon level for individual cores and multi-core systems, respectively, using machine learning techniques and making the process as au- tomatic as possible. On the other hand, Reversi and Dacota enable low cost validation in post-silicon, while delivering even higher coverage than pre-silicon techniques. Finally, the Field-repairable control logic (FRCL) and Caspar techniques allow designers to patch different classes of escaped errors in processors that are deployed in the field. The integrated set of solutions that we introduce with this thesis empowers processor vendors to drastically shorten their development timeline and, at the same time, to deliver more reliable and correct systems to their customers at a lower cost. Altogether, this work has the potential to solve the long-standing challenge of guaranteeing the complete functional correctness of modern microprocessors. v TABLE OF CONTENTS DEDICATION ................................... ii ACKNOWLEDGEMENTS ............................ iii PREFACE ...................................... v LIST OF FIGURES ................................ x LIST OF TABLES ................................. xv Chapter I. Introduction ............................. 1 1.1Microprocessordesignandverification:ashorttutorial........ 4 1.2OverviewofthisThesis......................... 6 1.3GuidingPrinciplesinDevelopingtheVerificationSolutions...... 8 1.3.1 AdherencetoTraditionalFlow................. 8 1.3.2 MinimizationofHumanInvolvement............. 9 1.3.3 MinimizationofAreaandPerformanceOverhead....... 9 Chapter II. Pre-silicon Verification of a Single Core ............. 11 2.1StressTestStructure........................... 12 2.2StimulusGenerator........................... 13 2.2.1 MarkovModel......................... 14 2.2.2 TemplateFiles.......................... 16 2.2.3 DependencyVariables..................... 18 2.2.4 HierarchicalMarkovModels.................. 20 2.3ActivityMonitorsandFeedback.................... 22 2.3.1 ActivityMonitors........................ 22 2.3.2 Depth-DrivenActivityMonitors................ 25 2.4CaseStudy................................ 26 2.5ExperimentalResults.......................... 28 2.5.1 ExperimentalTestbeds..................... 28 2.5.2 DependencyVariables:ParametricEvaluation......... 30 2.5.3 StabilityoftheActivityMonitors................ 31 vi 2.5.4 StressTest Coverage Density and Performance . 33 2.5.5 Depth-drivenActivityMonitors................ 37 2.5.6 EvaluationofHierarchicalMarkovModels.......... 37 2.6RelatedWork.............................. 39 2.7Summary................................ 41 Chapter III. Post-silicon Verification of a Single Core ............ 42 3.1ReversiTestGenerationSystem.................... 43 3.1.1 ReversibleandNon-reversibleInstructions........... 45 3.1.2 Limitations........................... 50 3.1.3 ReversiGenerator........................ 50 3.2Example................................. 52 3.2.1 ExperimentalFramework.................... 54 3.3ExperimentalEvaluation........................ 54 3.3.1 PerformanceEvaluation..................... 54 3.3.2 DesignErrorCoverage..................... 56 3.4Summary................................ 57 Chapter IV. Hardware Patching of a Single Core .............. 59 4.1 Background . ............................. 60 4.1.1 AnalysisofEscapedErrorsinCommercialProcessors..... 60 4.1.2 Hardwarepatchingapproaches................. 62 4.2Field-repairableControlLogic(FRCL)flowofOperation....... 64 4.2.1 PatternGeneration....................... 64 4.2.2 MatchingFlawedConfigurations................ 65 4.2.3 PatternCompressionAlgorithm................ 67 4.2.4 ProcessorRecovery....................... 70 4.2.5 Example............................. 72 4.3DesignFlow............................... 73 4.3.1 OverviewoftheDesignFramework.............. 73 4.3.2 Verification Methodology . ............... 74 4.3.3 ControlSignalSelection.................... 75 4.3.4 AutomaticSignalSelection................... 76 4.3.5 Performance-criticalExecution................. 77 4.4TrustedHardwareDesignwithSemanticGuardians.......... 78 4.4.1 Combining Semantic Guardians and Hardware Patching . 80 4.5ExperimentalEvaluation........................ 81 4.5.1 ExperimentalFramework.................... 82 4.5.2 DesignDefects......................... 85 4.5.3 SpecificityoftheMatcher.................... 86 4.5.4 StateMatcherAreaandTimingOverheads........... 88 4.5.5 PerformanceImpactofDegradedMode............ 89 vii 4.5.6 SemanticGuardianFrameworkAnalysis............ 90 4.6Summary................................ 94 Chapter V. Pre-silicon Verification of Multi-Cores .............. 96 5.1 Background . ............................. 97 5.2MCjammerTool............................. 99 5.2.1 OverallStructure.......................