VMEbus FAQ- Frequently Asked Questions for the Beginning VMEbus User John Rynearson, Technical Director, through an extender board in a fully proposed in March and Drew Berding, VITA loaded system. Arizona Digital, compared the various Much speculation ensued as to how approaches and presented arguments Question: Recently I've been hearing the backplane was constructed. While regarding the advantages of the star back- about new high performance VME many ideas were put forth, the method plane approach. backplanes. How are they different employed by Drew was both elegant and Drew's original announcement in from traditional VME backplanes and straightforward. A standard backplane January 1997 has unleased new research how will they enhance VME perfor- trace goes from slot 1 to slot 2 to slot 3 into backplane characteristics and has mance? and so on through slot 21. In the spurred many companies to reconsider VME320 backplane each slot trace is the way backplanes are built. Introduction- The VMEbus back- wired directly to slot 11 in a basic star 2eSST- To take advantage of these plane provides the transport media for configuration so that a signal from slot 1 new backplane technologies, the VITA electrical signals between modules. As to slot 2 goes from slot 1 to slot 11 and Standards Organization (VSO) set up a originally defined a VME backplane can then back to slot 2. Wiring the backplane task group early in 1997 to begin work on contain up to 21 slots. Why was 21 slots in this manner changes the backplane sig- a new protocol. The task group decided selected? Because if you space connec- nal characteristics dramatically. Instead to specify a synchronous protocol that tors at 0.8 inch you can just get 21 slots of looking like a transmission line, the would provide data transfer rates of 320 into a chassis which will fit into a 19 inch VME320 backplane looks like a lumped Mbytes/second and greater. rack. Backplanes can contain less than capacitance. As a result signal lines are The 2eSST protocol, is based on the 21 slots and sizes such as 5, 7, 9, 12, and cleaner, noise is reduced, and data trans- asynchronous 2eVME protocol. The main 15 slots are popular. For really small sys- fer rates can be effectively increased. exception to this is that during its data tems even 3 slot backplanes can be used. While Drew's announcement created phases, 2eSST is a source synchronous The VMEbus defines an asynchro- a lot of interest from users, it also caused protocol. No acknowledgment is expected nous backplane protocol which uses the VMEbus community to revisit the from the receiver of the data. Hence, the handshaking signals rather than a clock original assumptions for backplane design theoretical performance of 2eSST is lim- to transfer data. Since the backplane is and to see what other design changes ited only by the skew between receiver viewed as a transmission line, certain could be made to enhance backplane per- and transmitter of data. Like 2eVME it time delays are defined to assure that sig- formance. uses incident wave switching to guaran- nals reach a known state before they are A Second Look- At the March 1998 tee fast switching times and minimize deemed valid. These time delays were VSO meeting in Geneva, Switzerland, skew. The result is a protocol that as cur- determined by taking into account a fully Andreas Lenkisch, Trenew, presented rently defined doubles the theoretical loaded 21 slot backplane and characteris- research he had done to enhance back- bandwidth of VME to 320Mbytes/sec. tics of specific TTL logic available when plane performance in a paper titled; VME The protocol can be broken into three the VMEbus was developed in the early Breaks Performance Barrier Again - main phases: address broadcast, data 1980s. 1000 Mbytes/s Range Possible. In the phase and termination. These delays have stood the test of paper he noted that a reduction in trace The address broadcast phase for time and have provided reliable operation impedance improved signal waveforms 2eSST is identical to the address broad- for VMEbus systems in a variety of con- and might allow higher speed transfers in cast phase for 2eVME. However, the data figurations and applications. a traditional stitched backplane. phase is synchronous rather than asyn- VME320- At the January 1997 Real In May, Bob Sullivan, Hybricon, pre- chronous. Time Computer Show in Santa Clara, CA. sented work he had to done showing the Traditional VME utilizes a handshake a revolutionary announcement was possiblity of moving data at 560 protocol whereby data strobes (DS1* and made. Drew Berding, Arizona Digital, dis- Mbytes/sec with existing ABTE ETL DS0*) are acknowledged by DTACK* played a 21 slot VMEbus backplane that transceivers. Hybricon's approach was to which then allows the data strobes to be could transfer data at a 320 Mbyte/second use diode terminations and a modified removed which in turn allows the data rate. His demonstration was even bus topology to increase the effective DTACK* to be removed. Once DTACK* is more dramatic because one of the mod- impedance of the backplane. deasserted, a new cycle can begin. ules was on a standard extender board. The battle of the backplanes contin- Traditional VME protocol requires Scope traces showed the signals to be ued at the July VSO meeting where four delays through the drivers, back- very clean even though signals were run- Andreas Lenkisch, Trenew, presented plane and receivers plus the settling time ning from slot 1 to slot 21 and then additional results to the approach he had of the backplane. 2eVME protocol continued on page 23 October / November / December 1998 17 (continued from page 19) the VMEbus and CompactPCI ‘PVIC’ (continued from page 14) embedded markets. The Model found in three devices, the sin- VFX-M brings a 128-bit graph- gle bridge ASIC allows place- ics engine to the PMC bus. Uti- PVIC MirroredMemory (MM) ment of more functionality on a lizing the Number Nine 1128 single board computer. The 2D/3D graphics engine, it com- The PVIC implements a local read and global write Mirrored MVME2400 supports 32 to 256 bines VGA compatibility and Memory concept. The first part of the MM is reserved for the MB of ECC SDRAM. Other fea- unmatched performance with a write and read buffers of the PVIC system. The rest is available tures include 10/100Mb Ether- flexible graphics interface for the user. Apart from the previously mentioned PVIC message net, two PCI Mezzanine Card which can cover a wide range of FIFO for efficient interrupt dispatching, it also implements a (PMC) slots with front panel 8, 16, and 24-bit display appli- global reservation mechanism. This mechanism allows the and P2 I/O, one serial port and cations. Peritek is on the web implementation of hardware semaphores, test-and-set opera- at; www.peritek.com. 9MB of onboard FLASH. The tions and other atomic operations in a flexible and efficient way. MVME2400 is scheduled for January 1999 production avail- Systran Corp. has introduced This feature was especially added for distributed processing, ability. Motorola Computer the FibreXpress Simplex Link, farming etc. Group is on the web at; a system that allows Front www.mcg.mot.com/ Panel Data Port (FPDP) con- PVIC Implementations nections to be extended over Myriad Logic Inc. has distances up to l0 km. The Sim- The following PVIC products are available: announced the FC-2930/R, a plex Link maintains the sim- PVIC8426 CES RIO8062 [2] - PVIC Interface with PVIC high performance dual port plicity, high-bandwidth and low Bridge. fibre channel interface for the latency of FPDP connections, PVIC8425 PMC-PVIC single slot PMC with embedded while supporting long-distance Mercury RACE Series VME and GTL+ physical interface. Mulitport 9U four-port mother- and multiple destination broad- boards. The double-deep cast capabilities. The Simplex PVIC4025 CompactPCI - PVIC System Slot or Peripher- daughtercard has two l- Link is implemented by sets of al Slot (3U and 6U versions). Gigabit/second fiber optic con- Simplex Link Source Cards PVIC7225 PCI - PVIC 32-bit 33 MHz. nections for high-bandwidth (SLSCs) and corresponding PVIC8025 VME64x - PVIC interface with PVIC Bridge. arbitrated loop, point-to-point. Simplex Link Destination PIB6800 GTL+ 0.025” ribbon flat cable, up to 2 meters or switched topology network- Cards (SLDCs). In a standard at 66 MHz. ing. Designed to interconnect point-to-point configuration, all PIB6801 Differential Interface, 68pin SCSI cable type, high-throughput realtime sys- data is transmitted from a single up to 15m at 66MHz or 30m at 33 MHz. tems, RAIDs and general-pur- Source Card to a single Destina- PIB6802 Optical Link up to 200 meters, 1.4 Gbit/s. pose computers, the FC-2930/R tion Card, and the Destination is built to sustain 180 Card can provide flow control Mbytes/second, 90 Mbytes/sec- commands back to the Source PVIC System Example ond per channel, throughput to Card. Systran is on the web at; disk arrays and for peer-to-peer www.systran.com Figures 6 and 7 (page 14) show two typical PVIC system exam- comunications. Myriad Logic is ples. It is possible to mix PVIC DIFF with PVIC GTL+ through on the web at; www.myriadlog- VMETRO has announced a bridge elements. The PVIC bridge is only translating the electri- ic.com new member of its popular Bus cal levels. The PVIC protocol remains identical and the system Analyzer family: The PBTC-415 remains completely transparent. North Atlantic Instruments, CompactPCI Bus Analyzer & Inc. has introduced the new Exerciser. With its sampling REFERENCES speed up to 66.7MHz, optional- VME 5410-158 with up to 32 [1] CES, PVIC 8426 Technical Specification.