Voltage Representation NMOS Transistor as a Switch • MOSFET: Metal Oxide Semiconductor Field-Effect Transistor of Logic Values V DD • NMOS: n-channel MOSFET by Voltage Levels Logic value 1 x = "low" x = "high" (Positive logic V (a) A simple switch controlled by the input x system) 1,min Gate Undefined VG Source Drain V 0,max Substrate (Body) VS VD (c) Simplified symbol for Logic value 0 (b) NMOS transistor an NMOS transistor V SS (Gnd) 1 2 PMOS Transistor as a Switch Structure of a CMOS Circuit • PMOS: p-channel MOSFET •CMOS: V DD Complementary MOS Technology x = "high" x = "low" (a) A switch with the opposite behavior of previous slide Pull-up network PMOS (PUN) Gate V G V f Drain Source V V V S D x 1 V DD Substrate (Body) Pull-down network NMOS (c) Simplified symbol for (PDN) V (b) PMOS transistor an PMOS transistor x n 3 4 CMOS Realization of a NOT Gate CMOS Realization of a NOR Gate V DD VDD V x 1 T 1 T1 V V x Vf x 2 T 2 x T T f 1 2 x x T T T T f T2 1 2 1 2 3 4 V f 0 onoff 1 1 off on 0 0 0 on on off off 1 T 3 T 4 0 1 on off off on 0 off on on off (a) Circuit (b) Truth table and transistor states 1 0 0 1 1 off off on on 0 (a) Circuit (b) Truth table and transistor states 5 6 CprE 281 1 CMOS Realization of a NAND Gate CMOS Realization of a AND Gate V DD V DD V DD T 1 T 2 V f V f V x x x T T T T f 1 T 3 1 2 1 2 3 4 V x 1 0 0 on on off off 1 0 1 on off off on 1 V x 2 T 4 1 0 off on on off 1 V x 1 1 off off on on 0 2 (a) Circuit (b) Truth table and transistor states 7 8 Implement Compound Function Directly MOS (Metal-Oxide-Silicon) Transistor V • All variables need to DD appear in their complemented form. • PUN can be derived by looking at f directly. • PDN can be derived by looking at f’. V f V • Example: x 1 f = x1’+ x2’x3’ V x f’ = x1 (x2 + x3) 2 V x 3 9 10 MOS Transistor Operation Printed Circuit Board and Packaging • Printed Circuit Board (PCB) • Packaging Technology: – Dual Inline Package (DIP) – Quad Flat Package (QFP) – Pin Grid Array (PGA) Package NMOS 11 12 CprE 281 2 SEM Photo of Metal Layers Printed Circuit Board and Packaging • Printed Circuit Board (PCB) • Packaging Technology: – Dual Inline Package (DIP) – Quad Flat Package (QFP) – Pin Grid Array (PGA) Package 13 14 Types of Integrated Circuits (ICs) Standard Chips • Standard Chips • A collection of specific gates in a chip • Programmable Logic Devices (PLDs): • Popular until mid-80s – Programmable Logic Array (PLA) • 7400-Series Standard Chips – Programmable Array Logic (PAL) – 7404 : NOT gates – Complex Programmable Logic Device (CPLD) VDD – Field-Programmable Gate Array (FPGA) • Non-Programmable Devices: Gnd – Custom Design – Standard-Cell Design – 7408 : AND gates • Application Specific Integrated Circuit (ASIC) – 7432 : OR gates – Gate-Array Design – 74244 : Tri-State Buffers 15 16 Implementation of f = x1x2 + x2’x3 Programmable Logic Array (PLA) VDD x1 x2 xn 7404 Input buffers and inverters x1 x1 xn xn P1 7408 7432 AND plane OR plane Pk x1 x2 x3 f f f 17 1 m 18 CprE 281 3 Gate-Level Diagram of a PLA Customary Schematic for PLA x x x 1 2 3 x1 x2 x3 Programmable connections OR plane OR plane P1 P1 P P2 2 P3 P3 P4 P4 AND plane AND plane f f f1 f2 19 1 2 20 Programmable Array Logic (PAL) A PLD Programming Unit x1 x2 x3 P1 f1 P2 P3 f2 P4 AND plane 21 22 Complex Programmable Logic Device (CPLD) Field-Programmable Gate Array (FPGA) Logic block Interconnection switches I/O block I/O block PAL-like PAL-like block block I/O block I/O block I/O block Interconnection wires I/O block I/O block I/O block PAL-like PAL-like block block I/O block I/O block 23 24 CprE 281 4 x Lookup Table 1 Custom Design 0/1 (LUT) 0/1 x 1 x 2 f f 1 0/1 0 0 1 0 1 0 0/1 1 0 0 x 2 1 1 1 (a) Circuit for a two-input LUT (b) f 1 = x 1 x 2 + x 1 x 2 x 1 1 0 f 1 Intel 4004 Microprocessor 0 1971 1 x 2 Intel Pentium 4 Processor 2000 (c) Storage cell contents in the LUT 25 26 Standard-Cell Design Standard-Cell Design x 1 f 2 x 2 x 3 f 1 27 28 Gate Array Design 29 CprE 281 5.