Appendix – Demonstration Processors To validate the suitability of proposed on-line BISC-units and the micro rollback principle, different example processors were designed. The attention was focussed on COTS-processors. Designs should represent characteristics of embedded processor- cores in various applications. In order to cover a widespread similarity with real ar- chitectures, exemplary designs are redesigns – respective derivatives of microproces- sors, micro-controller CPU-cores and digital signal-processors. The following sec- tions of this appendix should give a short overview of used processors. Circuits were in most cases designed in a mixed manner: logic-, RTL-design and synthesized VHDL-descriptions. As design environments, Viewlogic’s WorkviewOf- fice – respective Innoveda’s Electronic Design Center and SYNOPSYS hardware- compiler were mainly and CADENCE was partly used. Designs are available as schematic, EDIF-netlist or structural VHDL-description. A.1 Microprocessor t4008 As an example for a simple 8-bit microprocessor class, the core t4008 was imple- mented. The top hierarchy of the design is built with the control- (CP) and the data- path (DP). As a ″von-Neumann″ architecture, the CP reads instructions and data from memory and controls the DP with the control-word CW. M. Pflanz, On-line Error Detection and Fast Recover Techniques, LNCS 2270, pp. 87–115, 2002. © Springer-Verlag Berlin Heidelberg 2002 88 Appendix – Demonstration Processors 8 bit 8 bit 8 bit Data Memory memory memory from memory read / write address data 8 bit Input data Data bits from Control path Data path state register sch: control_path.1 15 bit sch: proc_data_path.1 sym: control_path.1 control sym: proc_data_path.1 word 8 bit data from data path Clock & 8 bit Output Run data from processor Fig. 57. Top-hierarchy view of the t4008 The DP contains an arithmetic-logical-unit (ALU) for common integer operations. The combinatorial shifter serves to carry out simple shift and rotate operations. A register-file with seven registers represents basic processor-registers. The flag-register is used for conditional instructions and ′rotate with carry′ operations. Input- and out- put-ports are directly connected to CP. A.1 Microprocessor t4008 89 Destination D2 D1 IN_DATA[7:0] select D0 sch: destination_sel.1 sym: destination_sel.1 /QE_D A2 Bus A select Bus B select B2 A1 sch: mux8_1.1 sch: mux8_1.1 B1 A0 sym: mux8_1.1 sym: mux8_1.1 B0 Register file /QE_A Reg.1 - Reg.7 ALU_F2 Arithmetic-Logical Unit sch: 8bit_register ALU_F1 sch: 8bit_alu.1 ALU_F0 sym: 8bit_register sym: 8bit_alu.1 Cin V Z S C Shifter H2 State register sch: shifter.1 H1 sch: statusregister.1 sym: shifter.1 H0 sym: statusregister.1 State S[7:0] Control word 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B D (= A) ALU_F C H A2 A1 A0 B2 B1 B0 F2 F1 F0 C H2 H1 H0 /QE_A /QE_D Fig. 58. Data-Path and Control-word Definition 90 Appendix – Demonstration Processors Table 17. Destination Select Table 18. Source Select Signals D[2:0] load reg. A_sel[2:0] ALU A- B_sel[2:0] ALU B- CW bits CW bits INPUT CW bits INPUT 9|8|7 15|14|13 15|14|13 000 - 000 IN_DATA 000 IN_DATA 001 Reg. 1 001 Reg. 1 001 Reg. 1 010 Reg. 2 010 Reg. 2 010 Reg. 2 011 Reg. 3 011 Reg. 3 011 Reg. 3 100 Reg. 4 100 Reg. 4 100 Reg. 4 101 Reg. 5 101 Reg. 5 101 Reg. 5 110 Reg. 6 110 Reg. 6 110 Reg. 6 111 Reg. 7 111 Reg. 7 111 Reg. 7 Table 19. ALU Function Select Signals ALU_F[2:0], Cin Function ALU_F[2:0], Function CW bits 6|5|4|3 ALU output Cin ALU output CW bits 6|5|4|3 0000 F = A 100X F = A OR B 0001 F = A+1 101X F = A XOR B 0010 F = A+B 110X F = A AND B 0011 F = A+B+1 111X F = NOT A 0100 F = A-B-1 0101 F = A-B 0110 F = A-1 0111 F = A; C←1 Table 20. Shifter Control Shifter control function CW bits 2|1|0 000 transfer 001 Shift right 010 Shift left 011 Clear data 100 - 101 Rotate right 110 Rotate left 111 Clear data The CP contains control- and buffer-registers. A hardwired control-logic generates control-signals and the CW for the DP according micro-instructions. An instruction flow of this sequential processor starts always with the fetch phase: The initialized program-counter PC is loaded into the memory-address register MAR. It addresses the first instruction within the memory. In the next cycle, the memory-buffer register A.1 Microprocessor t4008 91 MBR is loaded with the first instruction-op-code. I will be moved to instruction- register IR, where the decoder generates the instruction variable for control-logic. After instruction decoding, different time-signal-controlled micro-instruction flows can be started. The instruction set covers 61 instructions (ι0,ι1,...,ι60) which are addressed with a 6-bit op-code (00H to 3FH). The processor was specified as a three-address- machine, that means: Destination register (A) Ä Source register 1 (D) <operation> Source register 2 (B) For a reduction of the effort for addressing, a pseudo-two-address-mode was intro- duced: Destination register A is equal to Source register D. The consequence of this mode is similar to the operation of processors with an accumulator. The addressing is organized as follow: with A=D: Destination register (A) Ä Source register(A) <operation> Source register(B) This method needs an adaptation of the available move-instructions <MVIN x>, <MOV x y>, <MVX x> und <MVM x m>. Because the ALU can execute a data transfer without operation (AÄA) only at bus-port A, the destination register must also be A. In order to realize a transfer to an other register, instead of an ALU- operation transfer A (F=011, C=1 or F=000, C=0), an operation addition of B and blocked A (bus-select = disable Å all A-ALU-Inputs = 0) is exe- cuted: A Ä 0 + B = A Ä B. In the DP, there are seven processor registers are available. They are addressable with 3-bit variables A and B (control-bits 15 to 10 at bus-selectors A and B; CW-bits 9, 8, 7 = D). Table 21. t4008 Register addresses 000 Register INP or OUT 001 Register 1 (or a) 010 Register 2 (or b) 011 Register 3 (or c) 100 Register 4 (or d) 101 Register 5 (or e) 110 Register 6 (or f) 111 Register 7 (or g) 92 Appendix – Demonstration Processors Memory out data M_[7:0] Y2 sel Y3 Y7 Register Address inc load Programm Counter Register RAR MUX 1 PC Y1 + Y6 Y0 A2 A1 A0 B2 B1 B0 sel sel Source & target Memory Buffer Memory Address register Register MBR Register MAR addresses Y14 sel Instruction MUX 2 Register IR Y8 /Y54 Reset Halt Sequencer T0...T10 Instruction Decoder C /Y12 & Y9+Y5 /Y13 Control logic & S sel sel Z Control word Data path input Data path output V generator buffer register INP buffer register OUT /Y4 +Y1+Y2 OR CW[6:0] Y[54:0] R_W INP_[7:0] OUT_[7:0] Data path Processor Memory Input data Output data control control read/write to data path from data path word signals signal Fig. 59. Control Path of t4008 With the currently used 8-bit MAR a space of 256 memory cells is addressable. The memory width is 8-bit. For every instruction-′block′ (opcode+operand), 3 bytes are provided. The following figure illustrates the used instruction format: 00H MAR-pointer with PC-value from fetch-phase INSTRUCTION 2D Ä Pointer PC PC + 1 ADDRESS 2EH Ä Pointer PC PC + 1 OPERAND 2FH FFH A.1 Microprocessor t4008 93 Format of instruction-block bytes: 1. INSTRUCTION-Byte 7 0123456 r/pr/p I5 I4 I3 I2 I1 I0 Reserve / Parity-Bits op-code (00H ... 3FH) 2. Address-Byte 7 0123456 r/p A2 A1 A0 r/p B2 B1 B0 B-bus- selector Reserve / Parity-Bits address A-bus- and D-selector address 3. Operand 7 0123456 D7 D6 D5 D4 D3 D2 D1 D0 8-bit data- or address Example 1: Two stored 8-bit numbers should be added . The result should be written back to the memory. (start address = 2DH): JMP g 2d # rescue old address in register 7 (=g) and jump to 2dH MVX a 2f # write data at 2fH to register 1 MVX b 32 # write data at 32H to register 2 ADD a b # add a and b, write result to a MVM a 14 # write a to memory cell 14H RET g # return to address[g] The binary code in the memory is as follows: Start address =00H JMP x X 110000 gx111x000 2d 00101101 ... ... ... ... ... ... ... ... ... Jump address =2dH MVX xx000010 ax001x000 2f 01011101 94 Appendix – Demonstration Processors MVX xx000010 bx010x000 32 10100010 ADD xx001000 a b x 0 0 1 x 0 1 0 xxxXxxxx MVM xx000011 ax000x001 14 00010100 RET xx110111 gx000x111 xxxXxxxx ... ... ... Result at 14H result 11111111 The following table contains the instruction set of processor t4008: Table 22. t4008 Instruction Set Mnemonic Format Register transfer I5 ... I0 A2 A1 A0 B2 B1 B0 00 MVIN x x = a,b,c,d,e,f,g Rx ← Input-Port 000000AAAxxx 01 MOV x y x,y=a,b,c,d,e,f,g Rx ← Ry 000001AAABBB 02 MVX x m x=a,b,..,g; m=XXH Rx ← M 000010AAA000 03 MVM x m x=a,b,..,g; m=XXH M ← Rx 000011000BBB 04 INCX x x=a,b,..,g Rx ← Rx+1 000100AAAxxx 05 INCM m m=XXH M ← M+1 000101000xxx 06 DECX x x=a,b,..,g Rx ← Rx-1 000110AAAxxx 07 DECM m m=XXH M ← M-1 000111000xxx 08 ADD x y x,y=a,b,c,d,e,f,g Rx ← Rx+Ry 001000AAABBB 09 ADX x m x=a,b,..,g; m=XXH Rx ← Rx+M 001001AAA000 0A ADM x m x=a,b,..,g; m=XXH M ← M+Rx 001010000BBB 0B ADC x y x,y=a,b,c,d,e,f,g Rx ← Rx+Ry+C 001011AAABBB 0C ACX x m x=a,b,..,g; m=XXH Rx ← Rx+M+C 001100AAA000 0D ACM x m x=a,b,..,g; m=XXH M ← M+Rx+C 001101000BBB 0E SUB x y x,y=a,b,c,d,e,f,g Rx ← Rx-Ry 001110AAABBB 0F SUX x m x=a,b,..,g; m=XXH Rx ← Rx-M 001111AAA000 10 SUM x m x=a,b,..,g; m=XXH M ← M-Rx 010000000BBB 11 SBB x y x,y=a,b,c,d,e,f,g Rx ← Rx-Ry-1 010001AAABBB 12 SBX x m x=a,b,..,g; m=XXH Rx ← Rx-M-1 010010AAA000 13 SBM x m x=a,b,..,g; m=XXH M ← M-Rx-1 010011000BBB 14 not used 010100 15 not used 010101 16 AND x y x,y=a,b,c,d,e,f,g Rx ← Rx ∧ Ry 010110AAABBB 17 ANX x m x=a,b,..,g; m=XXH Rx ← Rx ∧ M 010111AAA000 18 ANM x m x=a,b,..,g; m=XXH M ← M ∧ Rx 011000000BBB 19 OR x y x,y=a,b,c,d,e,f,g Rx ← Rx ∨ Ry 011001AAABBB 1A ORX x m x=a,b,..,g; m=XXH Rx ← Rx ∨ M 011010AAA000 1B ORM x m x=a,b,..,g; m=XXH M ← M ∨ Rx 011011000BBB 1C XOR x y x,y=a,b,c,d,e,f,g Rx ← Rx ⊕ Ry 011100AAABBB A.1 Microprocessor t4008 95 Table 22.