ARMv8-A/-R Debugger TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents ...................................................................................................................... ICD In-Circuit Debugger ................................................................................................................ Processor Architecture Manuals .............................................................................................. ARM/CORTEX/XSCALE ........................................................................................................... ARMv8-A/-R Debugger ......................................................................................................... 1 History ................................................................................................................................ 7 Warning .............................................................................................................................. 8 Introduction ....................................................................................................................... 9 Brief Overview of Documents for New Users 9 Demo and Start-up Scripts 10 Quick Start of the JTAG Debugger .................................................................................. 12 Configure Debugger for SoC Specific Reset Behavior 16 Troubleshooting ................................................................................................................ 30 Communication between Debugger and Processor cannot be established 30 FAQ ..................................................................................................................................... 31 Trace Extensions 31 Quick Start for Multicore Debugging ............................................................................... 32 SMP Debugging - Quick Start 33 1. How to Debug a System with Multiple Identical Cores 33 2. Set up the SMP Debug Scenario 34 3. Enter Debug Mode 35 4. Switch Debug View between Cores 35 5. Write a Start-up Script Summary 35 AMP Debugging - Quick Start 36 1. How to Debug a System with Multiple Heterogenous Cores 36 2. Starting the TRACE32 PowerView GUIs 36 3. Master-Slave Concept 37 4. Setting up the Multicore Environment 37 5. Synchronized Go / Step / Break 38 6. Write a Start-up Script Summary 38 ARM Specific Implementations ........................................................................................ 39 AArch Mode Support 39 ©1989-2021 Lauterbach GmbH ARMv8-A/-R Debugger 1 AArch64 and AArch32 Debugging 39 AArch64 and AArch32 Switching 40 TrustZone Technology 42 AArch64 Secure Model 42 AArch32 Secure Model 43 Debug Permission 43 Checking Debug Permission 43 Checking Secure State 44 Changing the Secure State from within TRACE32 44 AArch64 System Registers Access 45 AArch32 Coprocessor Registers Access 45 Accessing Cache and TLB Contents 45 Breakpoints and Vector Catch Register 45 Breakpoints and Secure Modes 45 big.LITTLE 46 Debugger Setup 46 Consequence for Debugging 47 Requirements for the Target Software 47 big.LITTLE MP 47 Breakpoints 48 Software Breakpoints 48 On-chip Breakpoints for Instructions 48 On-chip Breakpoints for Data 48 Example for Standard Breakpoints 49 Secure, Non-Secure, Hypervisor Breakpoints 50 Example for ETM Stopping Breakpoints 55 Access Classes 56 System Registers (AArch64 Mode) 64 Coprocessors (AArch32 Mode) 67 Accessing Memory at Run-time 71 Semihosting 75 AArch64 HLT Emulation Mode 76 AArch64 DCC Communication Mode (DCC = Debug Communication Channel) 77 AArch32 SVC (SWI) Emulation Mode 78 AArch32 DCC Communication Mode (DCC = Debug Communication Channel) 79 Virtual Terminal 81 Large Physical Address Extension (LPAE) 82 Consequence for Debugging 82 Virtualization Extension, Hypervisor 83 Consequence for Debugging 83 Debug Field 84 Run Mode 84 Run-time Measurements 85 ©1989-2021 Lauterbach GmbH ARMv8-A/-R Debugger 2 Trigger 85 ARM specific SYStem Commands ...................................................................................86 SYStem.CLOCK Inform debugger about core clock 86 SYStem.CONFIG.state Display target configuration 86 SYStem.CONFIG Configure debugger according to target topology 87 <parameters> describing the “DebugPort” 95 <parameters> describing the “JTAG” scan chain and signal behavior 100 <parameters> describing a system level TAP “Multitap” 104 <parameters> configuring a CoreSight Debug Access Port “DAP” 106 <parameters> describing debug and trace “Components” 110 <parameters> which are “Deprecated” 121 SYStem.CONFIG.EXTWDTDIS Disable external watchdog 125 SYStem.CONFIG GICD Generic Interrupt Controller Distributor (GIC) 127 SYStem.CONFIG GICR Generic Interrupt Controller Redistributor 130 SYStem.CONFIG GICC Generic Interrupt Controller physical CPU interface 131 SYStem.CONFIG GICH Generic Interrupt Controller virtual interface control 132 SYStem.CONFIG GICV Generic Interrupt Controller virtual CPU interface 133 SYStem.CONFIG SMMU Internal use 134 SYStem.CPU Select the used CPU 136 SYStem.JtagClock Define the frequency of the debug port 136 SYStem.LOCK Tristate the JTAG port 138 SYStem.MemAccess Run-time memory access 139 SYStem.Mode Establish the communication with the target 142 SYStem.Option Special setup 144 SYStem.Option Address32 Define address format display 144 SYStem.Option AHBHPROT Select AHB-AP HPROT bits 144 SYStem.Option AXI32 Use 32-bit atomic AXI accesses instead of 64-bit 145 SYStem.Option AXIACEEnable ACE enable flag of the AXI-AP 145 SYStem.Option AXICACHEFLAGS Select AXI-AP CACHE bits 145 SYStem.Option AXIHPROT Select AXI-AP HPROT bits 146 SYStem.Option BreakOS Allow break during OS-unlock 147 SYStem.Option CacheStatusCheck Check status bits during cache access 148 SYStem.Option CFLUSH FLUSH the cache before step/go 148 SYStem.Option CLTAPKEY Set key values for CLTAP operation 148 SYStem.Option CoreSightRESet Assert CPU reset via CTRL/STAT 148 SYStem.Option CTITimerStop Stop system timer when CPU stops 149 SYStem.Option DACRBYPASS Ignore DACR access permission settings 150 SYStem.Option DAPDBGPWRUPREQ Force debug power in DAP 150 SYStem.Option DAP2DBGPWRUPREQ Force debug power in DAP2 151 SYStem.Option DAPNOIRCHECK No DAP instruction register check 151 SYStem.Option DAPREMAP Rearrange DAP memory map 152 SYStem.Option DAPSYSPWRUPREQ Force system power in DAP 152 SYStem.Option DAP2SYSPWRUPREQ Force system power in DAP2 153 ©1989-2021 Lauterbach GmbH ARMv8-A/-R Debugger 3 SYStem.Option DBGSPR Use debugger view for SPR access 153 SYStem.Option DBGUNLOCK Unlock debug register via OSLAR 153 SYStem.Option DCacheMaintenance Data cache maintenance strategy 154 SYStem.Option DEBUGPORTOptions Options for debug port handling 154 SYStem.Option DIAG Activate more log messages 155 SYStem.Option DUALPORT Implicitly use run-time memory access 156 SYStem.Option DisMode Define disassembler mode 156 SYStem.Option EnReset Allow the debugger to drive nRESET (nSRST) 157 SYStem.Option eXclusiveMONitor Support for exclusive monitors 157 SYStem.Option HRCWOVerRide Enable override mechanism 157 SYStem.Option ICacheMaintenance I-Cache maintenance strategy 158 SYStem.Option IMASKASM Disable interrupts while single stepping 158 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 159 SYStem.Option INTDIS Disable all interrupts 159 SYStem.Option IntelSOC Slave core is part of Intel® SoC 159 SYStem.Option KEYCODE Define key code to unsecure processor 160 SYStem.Option MACHINESPACES Address extension for guest OSes 161 SYStem.Option MEMORYHPROT Select memory-AP HPROT bits 161 SYStem.Option MemStatusCheck Check status bits during memory access 162 SYStem.Option MMUPhysLogMemaccess Memory access preferences 162 SYStem.Option MMUSPACES Separate address spaces by space IDs 163 SYStem.Option MPUBYPASS Ignore MPU access permission settings 164 SYStem.Option NOMA Use alternative memory access 164 SYStem.Option NoPRCRReset Disable warm reset via PRCR 165 SYStem.Option OSUnlockCatch Use the 'OS Unlock Catch' debug event 165 SYStem.Option OVERLAY Enable overlay support 166 SYStem.Option PALLADIUM Extend debugger timeout 166 SYStem.Option PWRDWN Allow power-down mode 167 SYStem.Option PAN Overwrite CPSR.PAN setting 167 SYStem.Option PWRREQ Request core power 167 SYStem.Option ResBreak Halt the core after reset 168 SYStem.Option ResetDetection Choose method to detect a target reset 169 SYStem.RESetOut Assert nRESET/nSRST on JTAG connector 169 SYStem.Option RESetREGister Generic software reset 170 SYStem.Option RisingTDO Target outputs TDO on rising edge 170 SYStem.Option SLaVeSOFTRESet Allow soft reset of slave cores 171 SYStem.Option SMPMultipleCall Send start event to each SMP core 171 SYStem.Option SOFTLONG Use 32-bit access to set breakpoint 171 SYStem.Option SOFTQUAD Use 64-bit access to set breakpoint 171 SYStem.Option STEPSOFT Use software breakpoints for ASM stepping 172 SYStem.Option SOFTWORD Use 16-bit access to set breakpoint 172 SYStem.Option TURBO Disable cache maintenance during memory access 172 SYStem.state Display SYStem window 173 ©1989-2021 Lauterbach GmbH ARMv8-A/-R Debugger 4 SYStem.Option SYSPWRUPREQ Force system power 173 SYStem.Option TRST Allow debugger to drive TRST 174 SYStem.Option WaitDAPPWR Wait for DAP power after DAP power request 174 SYStem.Option WaitDBGREG Wait for core debug registers after reset 175 SYStem.Option WaitIDCODE IDCODE polling after deasserting reset 176 SYStem.Option WaitReset Wait with JTAG activities after deasserting reset 177 SYStem.Option ZoneSPACES Enable symbol management for ARM