Reveal Troubleshooting Guide Lattice Semiconductor Corporation 5555 NE Moore Court Hillsboro, OR 97124 (503) 268-8000 April 2008 Copyright Copyright © 2008 Lattice Semiconductor Corporation. This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine- readable form without prior written consent from Lattice Semiconductor Corporation. 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LSC reserves the right to discontinue any product or service without notice and assumes no obligation Reveal Troubleshooting Guide ii to correct any errors contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. Type Conventions Used in This Document Convention Meaning or Use Bold Items in the user interface that you select or click. Text that you type into the user interface. <Italic> Variables in commands, code syntax, and path names. Ctrl+L Press the two keys at the same time. Courier Code examples. Messages, reports, and prompts from the software. ... Omitted material in a line of code. Omitted lines in code and report examples. [ ] Optional items in syntax descriptions. In bus specifications, the brackets are required. ( ) Grouped items in syntax descriptions. { } Repeatable items in syntax descriptions. | A choice between items in syntax descriptions. Reveal Troubleshooting Guide iii Reveal Troubleshooting Guide iv Contents Reveal Troubleshooting Guide 1 HDL Language Restrictions 1 EDIF Support 2 Reveal Inserter and Project Navigator Errors 3 Design Parsing Problems in Reveal Inserter 3 Project Navigator Flow Messages 3 Signals Unavailable for Tracing and Triggering 4 JTAG Restrictions 6 Interface with LatticeMico32 7 Sample Clock 7 Unexpected Reveal Logic Analyzer Results 7 Performance 7 Creating a Reveal Logic Analyzer Project 9 REveal Troubleshooting Guide v Contents REveal Troubleshooting Guide vi Reveal Troubleshooting Guide This document describes the design restrictions for using on-chip debug. HDL Language Restrictions The following features are valid in the VHDL and Verilog languages but are not supported in Reveal Inserter when you use the RTL flow: Array types of two dimensions or more are not shown in the port or node section. Undeclared wires attached to instantiated component instances are not shown in the hierarchical design tree. You must declare these wires explicitly if you want to trace or trigger with them. Variables used in generate statements are not available for tracing and triggering. Variables used in conditional statements like if-then-else statements are not available for tracing and triggering. Variables used in selection statements like the case statement are not available for tracing and triggering. If function calls are used in the array declaration, the actual size of the array is unknown to Reveal Inserter. Entity and architecture of the same design cannot be in different files. In Verilog, you must explicitly declare variables at the very beginning of a module body to avoid obtaining different results from various synthesis tools. In VHDL, you must declare synthesis attributes within an entity, not within an architecture, to avoid obtaining different results from various synthesis tools. Reveal Troubleshooting Guide 1 Reveal Troubleshooting Guide EDIF Support In VHDL, always define the syn_keep and preserve_signal attributes as Boolean types when you declare them in your design. Synplify defines them as Boolean types, and Reveal Inserter will issue an error message if you define them as strings. EDIF Support The EDIF flow is fully supported in Reveal. However, you must be aware of the following: Reveal Inserter must be started from a Project Navigator project. In order to use the EDIF flow with Reveal Inserter, you must start Reveal Inserter from a Project Navigator EDIF project. You cannot start the EDIF flow from a Project Navigator project that is schematic, VHDL/schematic, VHDL, Verilog/schematic, or Verilog. In the EDIF flow, the representation in Reveal Inserter is of the EDIF hierarchy and signal names. Buses appear as individual signals instead of buses, as in the RTL flow. Reveal Troubleshooting Guide 2 Reveal Troubleshooting Guide Reveal Inserter and Project Navigator Errors Reveal Inserter and Project Navigator Errors This section discusses errors that can occur when you run Reveal Inserter from the Project Navigator. Design Parsing Problems in Reveal Inserter When you start Reveal Inserter from the Project Navigator, it parses and statically elaborates the design in order to build the hierarchy representation and signal list to make them available for debugging. If the design cannot be parsed and elaborated because of syntax errors, Reveal Inserter’s graphical user interface will not open. Instead, a message box opens with an error message similar to that shown in Figure 1 and the location of the reveal_error.log file. This file contains all the information, warning, and error messages issued by the compiler when it tries to read the design. Figure 1: Reveal Inserter Design Parsing Error Message Project Navigator Flow Messages After Reveal Inserter inserts the debug logic, it generates the debug logic cores and passes the information to the Project Navigator for building the design. Several issues could potentially cause the implementation flow to fail because of the debug insertion. Three types of problems could occur: Problems with debug design generation Problems with connecting JTAG functionality Problems with design implementation Reveal Troubleshooting Guide 3 Reveal Troubleshooting Guide Signals Unavailable for Tracing and Triggering Debug Design Messages The debug cores are generated in Reveal Inserter. However, the design must also be modified to allow the debug cores to be connected to the appropriate signals. The modified design is generated during the Build Database step in the Project Navigator. The design is modified with the necessary connections for the debug cores, a temporary HDL file is generated, and the files are synthesized and converted to the Lattice Semiconductor netlist format. Errors generated during this stage are displayed in the automake.log file. JTAG Messages A second step occurs during the Build Database process when Reveal Inserter connects the debug cores to the JTAG functionality on the FPGA. During this step, a module called JTAGhub is generated, and any Reveal debug cores are connected to it. If other modules that use JTAG, such as ispTRACY or ORCAstra, have already been connected to the JTAG functionality, an error results. In the ispLEVER 7.1 release, you cannot use Reveal on a design if these other modules are used. To use Reveal, you would have to remove any of these other modules from the design. In addition, some design elements may have some of these modules embedded in them, causing the design to be unusable with Reveal. One example