This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Quaternary Logic Lookup Table in Standard CMOS Diogo Brito, Student Member, IEEE,TaimurG.Rabuske,Student Member, IEEE, Jorge R. Fernandes, Senior Member, IEEE, Paulo Flores, Senior Member, IEEE, and José Monteiro, Senior Member, IEEE Abstract— Interconnections are increasingly the dominant con- wires connecting the logic gates. It has been reported that tributor to delay, area and energy consumption in CMOS routing is exceeding transistors contributions for latency and digital circuits. Multiple-valued logic can decrease the average power dissipation of designs in modern CMOS processes [1]. power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of This is particularly compelling in modern field-programmable interconnections on overall energy consumption. In this paper, we gate arrays (FPGAs), where the power spent in routing may propose a quaternary lookup table (LUT) structure, designed to reach up to 70% of the overall consumption [2]. Due to its replace or complement binary LUTs in field programmable gate reconfigurability, FPGAs play an important role in modern arrays. The circuit is compatible with standard CMOS processes, digital systems design, as they allow an earlier time-to-market with a single voltage supply and employing only simple voltage- mode structures. A clock boosting technique is used to optimize and reduced engineering change order costs when compared the switches resistance and power consumption. The proposed with application-specific integrated circuits (ASICs). implementation overcomes several limitations found in previous An approach to mitigate the impact of interconnections is to quaternary implementations published so far, such as the need use multiple-valued logic (MVL) [3], hence, more information for special features in the CMOS process or power-hungry can be carried in each wire, reducing the routing network. current-mode cells. We present a full adder prototype based on the designed LUT, fabricated in a standard 130-nm CMOS Therefore, a single wire carrying a signal with N logic levels technology, able to work at 100 MHz while consuming 122 µW. can replace log2 N wires carrying binary signals. Reducing The experimental results demonstrate the correct quaternary the routing leads to a direct reduction of the line capacitances operation and confirm the power efficiency of the proposed and the overall circuit area. Therefore, this enables increasing design. the maximum operation frequency and reducing the power Index Terms— Field-programmable gate array (FPGA), lookup consumption. Moreover, logic levels become closer to each table (LUT), multiple-valued logic (MVL), quaternary logic, other, further reducing the average power needed for level standard CMOS technology. transitions. The new power consumption can be determined by (2), where Vav is the average voltage distance between I. INTRODUCTION logic levels N CONVENTIONAL binary CMOS digital circuits, static P D ∝ CVDDVav. (2) Ipower consumption is tightly related to leakage currents, and dynamic power consumption is determined by (1), where A more detailed analysis of the energy consumption in quaternary (base 4 representation) buses and a comparison to C is the capacitance of the nodes being driven and VDD is the power supply voltage their binary counterparts is shown in [4]. However, in spite of these advantages, it is known that the use of MVL comes at the ∝ 2 . P D CVDD (1) price of having relatively lower noise margin than the binary, therefore its use is commonly not trusted. While there is still The CMOS process has evolved by shrinking the transis- large and foreseeable room for power optimization exploiting C tors (thus reducing ) and employing lower supply voltages the shrinking and supply voltage reduction of CMOS devices, (lower VDD), therefore saving power and integrating more MOSFET shrinking is expected to saturate as transistors C functionality into the same area. However, capacitance approach atomic dimensions, imposing a fundamental barrier. also includes the routing capacitance associated with the Furthermore, supply voltage reduction is limited by practical Manuscript received June 17, 2013; revised December 8, 2013; accepted boundaries; the transistors threshold voltage (Vth) cannot be February 3, 2014. This work was supported by the National Funds reduced proportionally to the power supply voltage as it through FCT-Fundação para a Ciência e Tecnologia under Project leads to an increasing leakage current, therefore increasing PEst-OE/EEI/LA0021/2013 and Project QCell EXPL/EEI-ELC/1016/2012. D. Brito, T. G. Rabuske, and J. R. Fernandes are with GCAM, INESC- the static consumption of CMOS circuits. The exposed limi- ID/Instituto Superior Técnico - TU Lisbon, Lisbon 1000-029, Portugal (e-mail: tations encourage the exploration of circuit and system-level [email protected]; [email protected]; jorge.fernandes@ techniques to achieve higher energy efficiency. This may inesc-id.pt). P. Flores and J. Monteiro are with ALGOS, INESC-ID/Instituto Superior include dropping conventional noise margins of binary levels Técnico - TU Lisbon, Lisbon 1049-001, Portugal (e-mail: [email protected]; and, therefore, dealing with less-comfortable noise margins [email protected]). of the MVL logic should be considered. However, previously Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. reported implementations of MVL either present high power Digital Object Identifier 10.1109/TVLSI.2014.2308302 consumption, due to current-mode circuit elements [5]–[7], 1063-8210 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Fig. 1. Quaternary logic and reference voltages levels. or require nonstandard multithreshold CMOS technologies [8]. These drawbacks have prevented MVL from being competitive Fig. 2. Proposed quaternary LUT. when compared with binary logic. achieved for LUTs, as demonstrated in [9]. A LUT is an This paper proposes a novel view of MVL circuits through array indexing operator, where the output is mapped by the the design of a look up table (LUT) based on the quater- input, based on the configuration memory. The configuration nary representation that exploits simple voltage-mode standard values are initially stored in the LUT configuration memory, CMOS circuits and optimized switches using a simplified and according to the input, the logic value in the addressed clock boosting (CB) technique. The proposed MVL LUT can position is assigned to the output. By properly programming replace or complement conventional binary logic, since the the LUT configuration memory, the LUT can implement any designed circuit is simple, efficient and we can combine both; logic function with the given number of inputs and outputs, i.e., they use the same implementation/fabrication technology. making it very practical to implement reconfigurable hardware, We have implemented and fabricated a circuit in a standard such as FPGAs. 130-nm CMOS technology, requiring a single supply voltage A quaternary function implemented by a QLUT is defined of 1.2 V. We present experimentally measured results to as g : Qk → Q, over a set of quaternary input variables support the proposed ideas. Y = (y0,...,yk−1), where the values of a variable yi and the This paper is organized as follows. In Section II, we review function g(Y ) are defined in Q ={0, 1, 2, 3}. In general, if l the basic concepts of quaternary logic and LUTs. Then, is the number of logic levels, the total number of different in Section III the quaternary LUT (QLUT) topology and functions |F| that can be implemented in a LUT is given by circuits are proposed, together with some design guidelines. | × k | In Section IV, the QLUT circuits dimensioning is described |F|=l n l (4) and the simulation results are presented. In Section V, a full where n is the number of outputs and k is the number of adder prototype based on the proposed QLUT is developed. inputs. For a LUT with a single output (n = 1), the number Section VI presents the experimental results obtained for of different functions for binary (l = 2) and quaternary (l = 4) the fabricated circuit followed by a brief discussion. Finally, representations is given, respectively, by Section VII summarizes and concludes this paper. 2k k 4k k |F2|=2 = 4 |F4|=4 = 256 . (5) II. QUATERNARY LOGIC AND LUTS The number of possible functions that may be represented A quaternary variable can assume four different logic levels. in a quaternary LUT is much larger than in a binary LUT with Assuming a rail-to-rail voltage range and equal noise margins the same number of inputs and outputs. Therefore, apart from for the four logic levels, three different reference voltage val- reducing the total number of connections, MVL also leads to ues are required, 1/6VDD,3/6VDD,and5/6VDD, to determine a reduction of the total number of gates when compared with a quaternary value. This is shown in Fig. 1. Since a quaternary a binary implementation. variable (Q) is able to carry twice as much information as a binary variable (B), we have the following relation: III. PROPOSED QLUT TOPOLOGY AND IMPLEMENTATION |Q|=2 ×|B|. (3) The proposed 2-input 1-output QLUT is shown in Fig. 2. For this given QLUT complexity, 16 quaternary configuration Therefore, two binary variables may be grouped into one inputs are necessary, one for each possible combination of quaternary variable without information loss, merging two the two quaternary inputs.