Quaternary Logic Lookup Table in Standard CMOS Diogo Brito, Student Member, IEEE,Taimurg.Rabuske,Student Member, IEEE, Jorge R

Total Page:16

File Type:pdf, Size:1020Kb

Load more

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Quaternary Logic Lookup Table in Standard CMOS Diogo Brito, Student Member, IEEE,TaimurG.Rabuske,Student Member, IEEE, Jorge R. Fernandes, Senior Member, IEEE, Paulo Flores, Senior Member, IEEE, and José Monteiro, Senior Member, IEEE Abstract— Interconnections are increasingly the dominant con- wires connecting the logic gates. It has been reported that tributor to delay, area and energy consumption in CMOS routing is exceeding transistors contributions for latency and digital circuits. Multiple-valued logic can decrease the average power dissipation of designs in modern CMOS processes [1]. power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of This is particularly compelling in modern field-programmable interconnections on overall energy consumption. In this paper, we gate arrays (FPGAs), where the power spent in routing may propose a quaternary lookup table (LUT) structure, designed to reach up to 70% of the overall consumption [2]. Due to its replace or complement binary LUTs in field programmable gate reconfigurability, FPGAs play an important role in modern arrays. The circuit is compatible with standard CMOS processes, digital systems design, as they allow an earlier time-to-market with a single voltage supply and employing only simple voltage- mode structures. A clock boosting technique is used to optimize and reduced engineering change order costs when compared the switches resistance and power consumption. The proposed with application-specific integrated circuits (ASICs). implementation overcomes several limitations found in previous An approach to mitigate the impact of interconnections is to quaternary implementations published so far, such as the need use multiple-valued logic (MVL) [3], hence, more information for special features in the CMOS process or power-hungry can be carried in each wire, reducing the routing network. current-mode cells. We present a full adder prototype based on the designed LUT, fabricated in a standard 130-nm CMOS Therefore, a single wire carrying a signal with N logic levels technology, able to work at 100 MHz while consuming 122 µW. can replace log2 N wires carrying binary signals. Reducing The experimental results demonstrate the correct quaternary the routing leads to a direct reduction of the line capacitances operation and confirm the power efficiency of the proposed and the overall circuit area. Therefore, this enables increasing design. the maximum operation frequency and reducing the power Index Terms— Field-programmable gate array (FPGA), lookup consumption. Moreover, logic levels become closer to each table (LUT), multiple-valued logic (MVL), quaternary logic, other, further reducing the average power needed for level standard CMOS technology. transitions. The new power consumption can be determined by (2), where Vav is the average voltage distance between I. INTRODUCTION logic levels N CONVENTIONAL binary CMOS digital circuits, static P D ∝ CVDDVav. (2) Ipower consumption is tightly related to leakage currents, and dynamic power consumption is determined by (1), where A more detailed analysis of the energy consumption in quaternary (base 4 representation) buses and a comparison to C is the capacitance of the nodes being driven and VDD is the power supply voltage their binary counterparts is shown in [4]. However, in spite of these advantages, it is known that the use of MVL comes at the ∝ 2 . P D CVDD (1) price of having relatively lower noise margin than the binary, therefore its use is commonly not trusted. While there is still The CMOS process has evolved by shrinking the transis- large and foreseeable room for power optimization exploiting C tors (thus reducing ) and employing lower supply voltages the shrinking and supply voltage reduction of CMOS devices, (lower VDD), therefore saving power and integrating more MOSFET shrinking is expected to saturate as transistors C functionality into the same area. However, capacitance approach atomic dimensions, imposing a fundamental barrier. also includes the routing capacitance associated with the Furthermore, supply voltage reduction is limited by practical Manuscript received June 17, 2013; revised December 8, 2013; accepted boundaries; the transistors threshold voltage (Vth) cannot be February 3, 2014. This work was supported by the National Funds reduced proportionally to the power supply voltage as it through FCT-Fundação para a Ciência e Tecnologia under Project leads to an increasing leakage current, therefore increasing PEst-OE/EEI/LA0021/2013 and Project QCell EXPL/EEI-ELC/1016/2012. D. Brito, T. G. Rabuske, and J. R. Fernandes are with GCAM, INESC- the static consumption of CMOS circuits. The exposed limi- ID/Instituto Superior Técnico - TU Lisbon, Lisbon 1000-029, Portugal (e-mail: tations encourage the exploration of circuit and system-level [email protected]; [email protected]; jorge.fernandes@ techniques to achieve higher energy efficiency. This may inesc-id.pt). P. Flores and J. Monteiro are with ALGOS, INESC-ID/Instituto Superior include dropping conventional noise margins of binary levels Técnico - TU Lisbon, Lisbon 1049-001, Portugal (e-mail: [email protected]; and, therefore, dealing with less-comfortable noise margins [email protected]). of the MVL logic should be considered. However, previously Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. reported implementations of MVL either present high power Digital Object Identifier 10.1109/TVLSI.2014.2308302 consumption, due to current-mode circuit elements [5]–[7], 1063-8210 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Fig. 1. Quaternary logic and reference voltages levels. or require nonstandard multithreshold CMOS technologies [8]. These drawbacks have prevented MVL from being competitive Fig. 2. Proposed quaternary LUT. when compared with binary logic. achieved for LUTs, as demonstrated in [9]. A LUT is an This paper proposes a novel view of MVL circuits through array indexing operator, where the output is mapped by the the design of a look up table (LUT) based on the quater- input, based on the configuration memory. The configuration nary representation that exploits simple voltage-mode standard values are initially stored in the LUT configuration memory, CMOS circuits and optimized switches using a simplified and according to the input, the logic value in the addressed clock boosting (CB) technique. The proposed MVL LUT can position is assigned to the output. By properly programming replace or complement conventional binary logic, since the the LUT configuration memory, the LUT can implement any designed circuit is simple, efficient and we can combine both; logic function with the given number of inputs and outputs, i.e., they use the same implementation/fabrication technology. making it very practical to implement reconfigurable hardware, We have implemented and fabricated a circuit in a standard such as FPGAs. 130-nm CMOS technology, requiring a single supply voltage A quaternary function implemented by a QLUT is defined of 1.2 V. We present experimentally measured results to as g : Qk → Q, over a set of quaternary input variables support the proposed ideas. Y = (y0,...,yk−1), where the values of a variable yi and the This paper is organized as follows. In Section II, we review function g(Y ) are defined in Q ={0, 1, 2, 3}. In general, if l the basic concepts of quaternary logic and LUTs. Then, is the number of logic levels, the total number of different in Section III the quaternary LUT (QLUT) topology and functions |F| that can be implemented in a LUT is given by circuits are proposed, together with some design guidelines. | × k | In Section IV, the QLUT circuits dimensioning is described |F|=l n l (4) and the simulation results are presented. In Section V, a full where n is the number of outputs and k is the number of adder prototype based on the proposed QLUT is developed. inputs. For a LUT with a single output (n = 1), the number Section VI presents the experimental results obtained for of different functions for binary (l = 2) and quaternary (l = 4) the fabricated circuit followed by a brief discussion. Finally, representations is given, respectively, by Section VII summarizes and concludes this paper. 2k k 4k k |F2|=2 = 4 |F4|=4 = 256 . (5) II. QUATERNARY LOGIC AND LUTS The number of possible functions that may be represented A quaternary variable can assume four different logic levels. in a quaternary LUT is much larger than in a binary LUT with Assuming a rail-to-rail voltage range and equal noise margins the same number of inputs and outputs. Therefore, apart from for the four logic levels, three different reference voltage val- reducing the total number of connections, MVL also leads to ues are required, 1/6VDD,3/6VDD,and5/6VDD, to determine a reduction of the total number of gates when compared with a quaternary value. This is shown in Fig. 1. Since a quaternary a binary implementation. variable (Q) is able to carry twice as much information as a binary variable (B), we have the following relation: III. PROPOSED QLUT TOPOLOGY AND IMPLEMENTATION |Q|=2 ×|B|. (3) The proposed 2-input 1-output QLUT is shown in Fig. 2. For this given QLUT complexity, 16 quaternary configuration Therefore, two binary variables may be grouped into one inputs are necessary, one for each possible combination of quaternary variable without information loss, merging two the two quaternary inputs.
Recommended publications
  • Characterization Quaternaty Lookup Table in Standard Cmos Process

    Characterization Quaternaty Lookup Table in Standard Cmos Process

    International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395-0056 Volume: 02 Issue: 07 | Oct-2015 www.irjet.net p-ISSN: 2395-0072 CHARACTERIZATION QUATERNATY LOOKUP TABLE IN STANDARD CMOS PROCESS S.Prabhu Venkateswaran1, R.Selvarani2 1Assitant Professor, Electronics and Communication Engineering, SNS College of Technology,Tamil Nadu, India 2 PG Scholar, VLSI Design, SNS College Of Technology, Tamil Nadu, India -------------------------------------------------------------------------**------------------------------------------------------------------------ Abstract- The Binary logics and devices have been process gets low power and easy to scale down, gate of developed with an latest technology and gate design MOS need much lower driving current than base current of area. The design and implementation of logical circuits two polar, scaling down increase CMOS speed Comparing become easier and compact. Therefore present logic MVL present high power consumption, due to current devices that can implement in binary and multi valued mode circuit element or require nonstandard multi logic system. In multi-valued logic system logic gates threshold CMOS technologies. multiple-value logic are increase the high power required for level of transition varies in different logic systems, a quaternary has and increase the number of required interconnections become mature in terms of logic algebra and gates. ,hence also increasing the overall energy. Interconnections Some multi valued logic systems such as ternary and are increase the dominant contributor to delay are and quaternary logic schemes have been developed. energy consumption in CMOS digital circuit. Quaternary logic has many advantages over binary logic. Since it require half the number of digits to store 2. QUATERNARY LOGIC AND LUTs any information than its binary equivalent it is best for storage; the quaternary storage mechanism is less than Ternary logic system: It is based upon CMOS compatible twice as complex as the binary system.
  • A Reduced-Complexity Lookup Table Approach to Solving Mathematical Functions in Fpgas

    A Reduced-Complexity Lookup Table Approach to Solving Mathematical Functions in Fpgas

    A reduced-complexity lookup table approach to solving mathematical functions in FPGAs Michael Low, Jim P. Y. Lee Defence R&D Canada --- Ottawa Technical Memorandum DRDC Ottawa TM 2008-261 December 2008 A reduced-complexity lookup table approach to solving mathematical functions in FPGAs Michael Low Jim P. Y. Lee DRDC Ottawa Defence R&D Canada – Ottawa Technical Memorandum DRDC Ottawa TM 2008-261 December 2008 Principal Author Original signed by Michael Low Michael Low Defence Scientist, Radar Electronic Warfare Approved by Original signed by Jean-F. Rivest Jean-F. Rivest Head, Radar Electronic Warfare Approved for release by Original signed by Pierre Lavoie Pierre Lavoie Chief Scientist, DRDC Ottawa © Her Majesty the Queen in Right of Canada, as represented by the Minister of National Defence, 2008 © Sa Majesté la Reine (en droit du Canada), telle que représentée par le ministre de la Défense nationale, 2008 Abstract …….. Certain mathematical functions, such as the inverse, log, and arctangent, have traditionally been implemented in the digital domain using the Coordinate Rotation Digital Computer (CORDIC) algorithm. In this study, it is shown that it is possible to achieve a similar degree of numerical accuracy using a reduced-complexity lookup table (RCLT) algorithm, which is much less computationally-intensive than the CORDIC. On programmable digital signal processor (DSP) chips, this reduces computation time. On field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs), this reduces the consumption of hardware resources. This paper presents the results of a study in which three commonly-used functions, i.e. inverse, log, and arctangent functions, have been synthesized for the Xilinx Virtex-II family of FPGAs, using both the RCLT and CORDIC implementations.
  • AC Induction Motor Control Using the Constant V/F Principle and a Natural

    AC Induction Motor Control Using the Constant V/F Principle and a Natural

    AVR494: AC Induction Motor Control Using the constant V/f Principle and a Natural PWM Algorithm 8-bit Microcontrollers Features • Cost-effective and flexible 3-phase induction motor drive • Interrupt driven Application Note • Low memory and computing requirements 1. Introduction Electrical power has been used for a long time to produce mechanical motion (either rotation or translation), thanks to electromechanical actuators. It is estimated that 50% of the electrical power produced in the United States is consumed by electrical motors. More than 50 motors can typically be found in a house, and nearly as many in a car. To preserve the environment and to reduce green-house effect gas emissions, gov- ernments around the world are introducing regulations requiring white goods manufacturers and industrial factories to produce more energy efficient appliances. Most often, this goal can be reached by an efficient drive and control of the motor speed. This is the reason why appliance designers and semiconductor suppliers are now interested by the design of low-cost and energy-efficient variable speed drives. Because of their high robustness, reliability, low cost and high efficiency (≈ 80%), AC induction motors are used in many industrial applications such as • appliances (washers, blowers, refrigerators, fans, vacuum cleaners, compressors …); • HVAC (heating, ventilation and air conditioning); • industrial drives (motion control, centrifugal pumps, robotics, …); • automotive control (electric vehicles) However, induction motors can only run at their rated speed when they are connected to the main power supply. This is the reason why variable frequency drives are needed to vary the rotor speed of an induction motor. The most popular algorithm for the control of a three-phase induction motor is the V/f control approach using a natural pulse-width modulation (PWM) technique to drive a voltage-source inverter (VSI), as shown on Figure 1-1.
  • Binary Search Algorithm Anthony Lin¹* Et Al

    Binary Search Algorithm Anthony Lin¹* Et Al

    WikiJournal of Science, 2019, 2(1):5 doi: 10.15347/wjs/2019.005 Encyclopedic Review Article Binary search algorithm Anthony Lin¹* et al. Abstract In In computer science, binary search, also known as half-interval search,[1] logarithmic search,[2] or binary chop,[3] is a search algorithm that finds a position of a target value within a sorted array.[4] Binary search compares the target value to an element in the middle of the array. If they are not equal, the half in which the target cannot lie is eliminated and the search continues on the remaining half, again taking the middle element to compare to the target value, and repeating this until the target value is found. If the search ends with the remaining half being empty, the target is not in the array. Binary search runs in logarithmic time in the worst case, making 푂(log 푛) comparisons, where 푛 is the number of elements in the array, the 푂 is ‘Big O’ notation, and 푙표푔 is the logarithm.[5] Binary search is faster than linear search except for small arrays. However, the array must be sorted first to be able to apply binary search. There are spe- cialized data structures designed for fast searching, such as hash tables, that can be searched more efficiently than binary search. However, binary search can be used to solve a wider range of problems, such as finding the next- smallest or next-largest element in the array relative to the target even if it is absent from the array. There are numerous variations of binary search.
  • A ' Microprocessor-Based Lookup Bearing Table

    A ' Microprocessor-Based Lookup Bearing Table

    NASA Technical Paper 1838 A'Microprocessor-Based Table Lookup Approach . for Magnetic Bearing Linearization . -. Nelson J. Groom and, James B. Miller .- MAY 1981 NASA .. TECH LIBRARY KAFB, NM NASA Technical Paper 1838 A Microprocessor-BasedTable Lookup Approach for. Magnetic BearingLinearization Nelson J. Groom and James B. Miller LarrgleyResearch Ceuter Hatnpton,Virgilria National Aeronautics and Space Administration Scientific and Technical Information Branch 1981 SUMMARY An approach forproduci ng a linear transfer chlar acteristic between force command and force output of a magnetic bearing actuator without flux biasing is pres.ented. The approach is mlcroprocessor based and uses a table 'lookup to generatedrive signals for the magnetiCbearing power driver. An experimental test setup used to demonstrate the feasibility of the approach is described, and testresults are presented. The testsetup contains bearing elements simi- lar to those used in a laboratory model annular momentum control device (AMCD) . INTRODUCTION ,. This paper describes an approach for producing a lineartransfer charac- teristic between the force command and force output of a magneticbearing actuator. The approach, which is microprocessor based and uses a table lookup to generate drive signals for the magneticbearing actuator power driver, was investigated for application to a laboratory model annular momentum control device (AKD) . The laboratory model (described in ref. 1 ) was built to inves- tigate potential problem areas in implementing the AMCD concept and is being used aspart ofan AKD hardware technology development program. The basic AMCD concept is that of a rotating annular rim,suspended by a minimum of three magneticbearing suspension stations and driven by a noncontacting elec- tromagneticspin motor.
  • Design and Implementation of Improved NCO Based on FPGA

    Design and Implementation of Improved NCO Based on FPGA

    Advances in Computer Science Research (ACSR), volume 90 3rd International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2019) Design and Implementation of Improved NCO based on FPGA Yanshuang Chen a, Jun Yang b, * School of Information Science and Engineering Yunnan University, Yun'nanKunming650091, China a [email protected], b, * [email protected] Abstract. A numerically controlled oscillator (NCO) is used to generate quadrature controllable sine and cosine waves and is an important part of software radio. The traditional NCO module is implemented based on the lookup table structure, which requires a large amount of hardware storage resources inside the FPGA. Therefore, the CORDIC algorithm is used to implement the NCO module, and the output accuracy is improved by improving the CORDIC algorithm. At the same time, the FPGA technology is characterized by strong reconfigurability, good scalability, low hardware resources. The module is designed with Verilog HDL language. Finally, the NCO model based on FPGA design has the characteristics of low hardware resource consumption and high output precision. The model was simulated by Modelsim and downloaded to the target chip verification of Altera DE2's EP2C35F672C6. The digitally controlled oscillator met the design requirements. Keywords: Digital controlled oscillator (NCO); CORDIC algorithm; Pipeline structure; FPGA; precision. 1. Introduction The numerically controlled oscillator (NCO) is an important component of the signal processing system [1], and is mainly used to generate orthogonally controllable sine and cosine waves. With the continuous development of modern communication systems, digital control oscillators have been widely used in digital communication, signal processing and other fields as an important part of software radio [2].
  • Pushing the Communication Barrier in Secure Computation Using Lookup Tables (Full Version)∗

    Pushing the Communication Barrier in Secure Computation Using Lookup Tables (Full Version)∗

    Pushing the Communication Barrier in Secure Computation using Lookup Tables (Full Version)∗ Ghada Dessouky1, Farinaz Koushanfar2, Ahmad-Reza Sadeghi1, Thomas Schneider3, Shaza Zeitouni1, and Michael Zohner3 1TU Darmstadt, System Security Lab, [email protected] 2University of California, Adaptive Computing and Embedded Systems Lab, [email protected] 3TU Darmstadt, Engineering Cryptographic Protocols Group, [email protected] Abstract Secure two-party computation has witnessed significant efficiency improvements in the recent years. Current implementations of protocols with security against passive adversaries generate and process data much faster than it can be sent over the network, even with a single thread. This paper introduces novel methods to further reduce the communication bottleneck and round complexity of semi-honest secure two-party computation. Our new methodology creates a trade-off between communication and computation, and we show that the added computing cost for each party is still feasible and practicable in light of the new communication savings. We first improve communication for Boolean circuits with 2-input gates by factor 1.9x when evaluated with the protocol of Goldreich-Micali-Wigderson (GMW). As a further step, we change the conventional Boolean circuit representation from 2-input gates to multi-input/multi-output lookup tables (LUTs) which can be programmed to realize arbitrary functions. We construct two protocols for evaluating LUTs offering a trade-off between online communication and total communication. Our most efficient LUT-based protocol reduces the communication and round complexity by a factor 2-4x for several basic and complex operations. Our proposed scheme results in a significant overall runtime decrease of up to a factor of 3x on several benchmark functions.
  • Dissertation a Methodology for Automated Lookup

    Dissertation a Methodology for Automated Lookup

    DISSERTATION A METHODOLOGY FOR AUTOMATED LOOKUP TABLE OPTIMIZATION OF SCIENTIFIC APPLICATIONS Submitted by Chris Wilcox Department of Computer Science In partial fulfillment of the requirements for the Degree of Doctor of Philosophy Colorado State University Fort Collins, Colorado Spring 2012 Doctoral Committee: Advisor: Michelle Mills Strout Co-Advisor: James M. Bieman Anton P. W. B¨ohm Daniel Turk ABSTRACT A METHODOLOGY FOR AUTOMATED LOOKUP TABLE OPTIMIZATION OF SCIENTIFIC APPLICATIONS Tuning the performance of scientific codes is challenging because of their math-intensive nature. Applications such as climate modeling and molecular biology simulate the behavior of natural systems based on scientific equations. Translating these equations into code can often yield expressions that are expensive to evaluate. Trigonometric, logarithmic, and exponential elementary functions are especially problematic because of their high cost relative to ordinary arithmetic. Lookup table (LUT) transformation can expedite function evaluation by precomputing and storing function results, thereby allowing inexpensive memory lookups to replace costly function calls. Practical concerns limit the size and accuracy of LUT data, thus the technique represents a tradeoff between error and performance. Current practice has the programmer apply each LUT transform manually, thereby impacting productivity, obfuscating code, and limiting programmer control over accuracy and performance. The goal of our research is to help scientific programmers use LUT techniques in a more effective and productive manner. Our approach substantially automates the process of applying LUT transformation via a methodology and its implementation in the Mesa tool. Mesa incorporates algorithms that make adding a LUT transform easier for the programmer, including expression enumeration, domain profiling, error analysis, performance modeling, and code generation.
  • Download Article (PDF)

    Download Article (PDF)

    International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2016) The Design of Direct Digital Synthesizer Based On Cordic Algorithm and FPGA Implementation Xian Zhang1, 2, a, Xinghua Zhao1, 2 and Binquan Zhou1, 2, b 1National Key Laboratory of Inertial Technology, Beihang University, Beijing 100191, China; 2School of Instrument Science and Opto-electronics Engineering, Beihang University, Beijing 100191, China. [email protected], [email protected] Abstract. Currently, there are many methods that can implement direct digital synthesizer (DDS) including ROM look-up table method, Cordic algorithm and so on. Traditional DDS usually adopts the method of look-up table, which needs ROM to save a lot of waveform data. But the frequency resolution of DDS depends on how many ROM can save. Obviously the more data ROM can save, the better frequency resolution will be. Thus it takes the more ROM resources and the higher power dissipation while it gets the lower reliability and the slower conversion speed. However, Cordic algorithm use the method of iteration, which can generate high-resolution local oscillator signal through the shift, accumulation and subtraction operation. Compared with ROM look-up table, it reduces the occupation of the resources of ROM substantially. Therefore, this paper use Cordic algorithm to design DDS. At the same time, the Cordic algorithm is programmed into the FPGA device, which can generate sine and cosine waveform. The frequency and amplitude of waveform can be adjusted by the host computer. Then the desired waveform is simulated in Modelsim and Chipscope platform. As a result, the function of waveform is debugged and verified in hardware platform successfully.
  • On the Claim That a Table-Lookup Program Could Pass the Turing Test to Appear, Minds and Machines

    On the Claim That a Table-Lookup Program Could Pass the Turing Test to Appear, Minds and Machines

    On The Claim That A Table-Lookup Program Could Pass The Turing Test To appear, Minds and Machines. Visit link.springer.com. Drew McDermott the date of receipt and acceptance should be inserted later Abstract The claim has often been made that passing the Turing Test would not be suffi- cient to prove that a computer program was intelligent because a trivial program could do it, namely, the “humongous table (ht) program,” which simply looks up in a table what to say next. This claim is examined in detail. Three ground rules are argued for: 1. That the HT program must be exhaustive, and not be based on some vaguely imagined set of tricks. 2. That the HT program must not be created by some set of sentient beings enacting re- sponses to all possible inputs. 3. That in the current state of cognitive science it must be an open possibility that a computational model of the human mind will be developed that ac- counts for at least its nonphenomenological properties. Given ground rule 3, the HT program could simply be an “optimized” version of some computational model of a mind, created via the automatic application of program-transformation rules (thus satisfying ground rule 2). Therefore, whatever mental states one would be willing to impute to an ordinary computa- tional model of the human psyche one should be willing to grant to the optimized version as well. Hence no one could dismiss out of hand the possibility that the HT program was intelligent. This conclusion is important because the Humongous-Table-Program Argument is the only argument ever marshalled against the sufficiency of the Turing Test, if we exclude arguments that cognitive science is simply not possible.
  • Lecture 5 Memoization/Dynamic Programming the String

    Lecture 5 Memoization/Dynamic Programming the String

    CS125 Lecture 5 Fall 2016 Memoization/Dynamic Programming Today’s lecture discusses memoization, which is a method for speeding up algorithms based on recursion, by using additional memory to remember already-computed answers to subproblems. It is quite similar to dynamic programming, which is the iterative version. (Mantra: memoization is to recursion as dynamic programming is to for loops.) The String reconstruction problem The greedy approach doesn’t always work, as we have seen. It lacks flexibility; if at some point, it makes a wrong choice, it becomes stuck. For example, consider the problem of string reconstruction. Suppose that all the blank spaces and punctuation marks inadvertently have been removed from a text file. You would like to reconstruct the file, using a dictionary. (We will assume that all words in the file are standard English.) For example, the string might begin “thesearethereasons”. A greedy algorithm would spot that the first two words were “the” and “sea”, but then it would run into trouble. We could backtrack; we have found that sea is a mistake, so looking more closely, we might find the first three words “the”,“sear”, and “ether”. Again there is trouble. In general, we might end up spending exponential time traveling down false trails. (In practice, since English text strings are so well behaved, we might be able to make this work– but probably not in other contexts, such as reconstructing DNA sequences!) This problem has a nice structure, however, that we can take advantage of. The problem can be broken down into entirely similar subproblems. For example, we can ask whether the strings “theseare” and “thereasons” both can be reconstructed with a dictionary.
  • EE 423: Class Demo 1 Introduction in Lab 1, Two Different Methods for Generating a Sinusoid Are Used

    EE 423: Class Demo 1 Introduction in Lab 1, Two Different Methods for Generating a Sinusoid Are Used

    EE 423: Class Demo 1 Introduction In lab 1, two different methods for generating a sinusoid are used. In sine gen.c, the built-in C function sin() is used to approximate the function sin(·) and interrupts are used to send the samples to the codec. For this implementation, the samples of the sine function are calculated at every interrupt. If the discrete-time sequence being generated is periodic, this implementation is a waste of resources1. When the discrete-time sinusoid sequence is periodic, a pre-computed lookup table may be stored in memory and samples may be read from the table and outputted to the codec. This is the way that sine lookup poll.c is coded. However, in this implementation, a polling (instead of interrupt driven) method is used to send the samples to the codec. In this demo, a mixture of these two methods mentioned above will be used. The idea of having a lookup table from sine lookup poll.c will be used to store samples of a discrete-time periodic. However, instead of calculating and storing these values by hand, the built-in C function sin() will be used to generate the lookup table. The values in the lookup table will be accessed in the same manner as sine lookup poll.c; however, the codec will be accessed using interrupts as in sine gen.c. In this demo, you will study: • code debugging, • overdriving the codec, and • code modification. Demo 1 Preliminaries Before continuing with this demo, make sure that the following tasks from the Lab 1 write-up have been completed (in the given order): 1.