DATASHEET TW2866C FN8253 4-Channel Video Decoders and Audio Codecs and Rev. 0.00 February 3, 2012 Video Encoder for Security Application The TW2866 includes four high quality Provides multi-channel audio mixed analog NTSC/PAL/SECAM video decoders that convert output analog composite video signal to digital Supports I2S/DSP Master/Slave interface for component YCbCr data for security applications. record output and playback input Each channel contains 10 bit ADC and proprietary clamp and gain controllers and PCM 8/16 bit and u-Law/A-Law 8bit for audio utilizes 4H comb filter for separating luminance word length & chrominance to reduce cross noise artifacts. The TW2866 adopts the image enhancement Programmable audio sample rate that covers techniques, such as IF compensation filter, CTI popular frequencies of 8/16/32/44.1/48kHz and programmable peaking. TW2866 also Supports a two-wire serial host interface includes one NTSC/PAL video encoder with two 10 bit DAC’s to support CVBS and YC output. The Integrated one video encoder and two10 bit TW2866 also includes audio CODEC, which has video CMOS DACs. five audio Analog-to-Digital converters and one Integrated clock PLL for 108MHz clock output. Digital-to-Analog converter. A built-in audio controller can generate digital outputs for Ultra low power consumption (Typical recording/mixing and accepts digital input for 666.84mW) playback. 128 pin LQFP package Features Accepts all NTSC(M/4.43) / PAL(B/D/G/H/I/K/L/M/N/60)/SECAM standards with auto detection Integrated four video analog anti-aliasing filters and 10 bit CMOS ADCs High performance adaptive 4H comb filters for all NTSC/PAL standards IF compensation filter for improvement of color demodulation Color Transient Improvement (CTI) Automatic white peak control Programmable hue, saturation, contrast, brightness and sharpness Proprietary fast video locking system for non- realtime application Supports the standard ITU-R BT.656 format or time multiplexed output with 54/108MHz Provides simultaneous four channel Full D1 and CIF time-multiplexed outputs with 54MHz. Integrated five audio ADCs and one audio DAC FN8253 Rev. 0.00 Page 1 of 143 February 3, 2012 TW2866C Block Diagram X VIN1A 4H Comb e VD1[7:0] 6 c U AADDCC 5 Video Decoder a f 6 M VD2[7:0] r VIN1B . e T t VD3[7:0] B n I AIN1 AADDCC Decimation Filter VD4[7:0] e MPP1 c P a X VIN2A f MPP2 P 4H Comb r U ADC ADC e M Video Decoder t M MPP3 VIN2B n I MPP4 AIN2 AADDCC Decimation Filter r L CLKPOn o L t k P a c r XTO k o e l c n X o VIN3A C XTI l 4H Comb e U AADDCC C Video Decoder G VIN3B M CLKNOn e c t SCLK a s AIN3 AADDCC Decimation Filter f r o e SDAT H t n I IRQ VIN4A X 4H Comb U AADDCC Video Decoder ACLKR VIN4B M ASYNR ADATR AIN4 AADDCC Decimation Filter e c ADATM a S f r 2 I e ACLKP t n I ASYNP AIN5 Decimation Filter ADC ADATP AOUT DAC Interpolation Filter VYOUT DAC Digital Video ENCLK Encoder ED[7:0] VCOUT DAC Ordering Information PART PART PACKAGE PKG. NUMBER MARKING (Pb-free) DWG. # TW2866-LC1-CR TW2866 LC1-CR 128 Ld LQFP Q128.14x14 NOTE: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb- free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN8253 Rev. 0.00 Page 2 of 143 February 3, 2012 TW2866C 0x06(CH1)/0x16(CH2)/0x26(CH3)/0x36(Ch4) – Hue Control Table of Contents Register .................................................................................. 61 0x07(CH1)/0x17(CH2)/0x27(CH3)/0x37(CH4) – Cropping Pin Diagram ...................................................................................... 5 Register, High ........................................................................ 62 Pin Descriptions .............................................................................. 6 0x08(CH1)/0x18(CH2)/0x28(CH3)/0x38(CH4) – Vertical Analog Video/Audio Interface Pins ..................................................... 6 Delay Register, Low .............................................................. 62 Digital Video/Audio Interface Pins ....................................................... 7 0x09(CH1)/0x19(CH2)/0x29(CH3)/0x39(CH4) – Vertical System Control Pins .............................................................................. 8 Active Register, Low ............................................................. 62 Power and Ground Pins ........................................................................ 9 0x0A(CH1)/0x1A(CH2)/0x2A(CH3)/0x3A(CH4) – Horizontal Functional Description ................................................................. 10 Delay Register, Low .............................................................. 62 Video Input Formats ............................................................................. 10 0x0B(CH1)/0x1B(CH2)/0x2B(CH3)/0x3B(CH4) – Horizontal Analog Frontend ................................................................................... 11 Active Register, Low ............................................................. 63 Decimation Filter ................................................................................. 12 0x0C(CH1)/0x1C(CH2)/0x2C(CH3)/0x3C(CH4) – Automatic Gain Control and Clamping ............................................ 13 Macrovision Detection .......................................................... 63 Sync Processing ................................................................................... 13 0x0D(CH1)/0x1D(CH2)/0x2D(CH3)/0x3D(CH4) – Chip Y/C Separation ....................................................................................... 13 STATUS II .............................................................................. 63 Color Decoding ..................................................................................... 15 0x0E(CH1)/0x1E(CH2)/0x2E(CH3)/0x3E(CH4) – Standard Chrominance Demodulation ............................................................. 15 Selection................................................................................. 64 ACC (Automatic Color gain control) ................................................. 16 0x0F(CH1)/0x1F(CH2)/0x2F(CH3)/0x3F(CH4) – Standard Chrominance Processing ................................................................... 16 Recognition ............................................................................ 65 Chrominance Gain, Offset and Hue Adjustment ............................ 16 0xE4(CH1)/0xE7(CH2)/0xEA(CH3)/0xED(CH4) – Vertical CTI (Color Transient Improvement).................................................. 16 Scaling Register, Low ........................................................... 65 Luminance Processing ....................................................................... 16 0xE5(CH1)/0xE8(CH2)/0xEB(CH3)/0xEE(CH4) – Scaling Video Cropping ..................................................................................... 17 Register, High ........................................................................ 65 VDELAY + VACTIVE < Total number of lines per field......................... 17 0xE6(CH1)/0xE9(CH2)/0xEC(CH3)/0xEF(CH4) – Horizontal Video Scaler ........................................................................................... 18 Scaling Register, Low ........................................................... 65 Output Format ....................................................................................... 21 0xA4(CH1)/0xA5(CH2)/0xA6(CH3)/0xA7(CH4) – ID ITU-R BT.656 Format ........................................................................ 21 Detection Control ................................................................... 66 Two Channel ITU-R BT.656 Time-multiplexed Format with 0xC4(CH1)/0xC5(CH2)/0xC6(CH3)/0xC7(CH4) – H monitor ....... 66 54MHz.................................................................................... 22 0x80 – Software Reset Control Register .......................................... 66 Four Channel CIF Time-multiplexed Format with 54MHz ............. 23 0x81 – Analog Control Register ........................................................ 67 Four Channel D1 Time-division-multiplexed Format with 0x82 – Analog Control Reister2 ........................................................ 67 108MHz ................................................................................. 25 0x83 – Control Register I ................................................................... 68 Output Enabling Act ........................................................................... 27 0x84 – Color Killer Hysteresis Control Register ............................... 68 Video Output Channel Selection ...................................................... 27 0x85 – Vertical Sharpness ................................................................ 68 Extra Sync Output .............................................................................. 27 0x86 – Coring Control Register ......................................................... 69 Video Encoder ....................................................................................... 30 0x87 – Clamping Gain ....................................................................... 69 Output Standard Selection ................................................................ 30 0x88 – Individual AGC Gain .............................................................