TURING AWARD MICROPIPELINES IVAN E. SUTHERLAND The pipeline processor is a common paradigm for very that they are elastic. high speed computing machinery. Pipeline processors I assign the name micropipeline to a particularly sim- provide high speed because their separate stages can ple form of event-driven elastic pipeline with or with- operate concurrently, much as different people on a out internal processing. The micro part of this name manufacturing assembly line work concurrently on ma- seems appropriate to me because micropipelines con- terial passing down the line. Although the concurrency tain very simple circuitry, because micropipelines are of pipeline processors makes their design a demanding useful in very short lengths, and because micropipe- task, they can be found in graphics processors, in signal lines are suitable for layout in microelectronic form. processing devices, in integrated circuit components for I have chosen micropipelines as the subject of this doing arithmetic, and in the instruction interpretation lecture for three reasons. First, micropipelines are sim- units and arithmetic operations of general purpose ple and easy to understand. I believe that simple ideas computing machinery. are best, and I find beauty in the simplicity and sym- Because I plan to describe a variety of pipeline pro- metry of micropipelines. Second, I see confusion sur- cessors, I will start by suggesting names for their var- rounding the design of FIFOs. I offer this description of ious forms. Pipeline processors, or more simply just micropipelines in the hope of reducing some of that pipelines, operate on data as it passes along them. The confusion. latency of a pipeline is a measure of how long it takes a The third reason I have chosen my subject addresses single data value to pass through it. The throughput the limitations imposed on us by the clocked-logic con- rate of a pipeline is a measure of how many data values ceptual framework now commonly used in the design can pass through it per unit time. of digital systems. I believe that this conceptual frame- Pipelines both store and process data; the storage ele- work or mind set masks simple and useful structures ments and processing logic in them alternate along like micropipelines from our thoughts, structures that their length. I will describe pipelines in their complete are easy to design and apply given a different concep- form later, but first I will focus on their storage ele- tual framework. Because micropipelines are event- ments alone, stripping away all processing logic. driven, their simplicity is not available within the Stripped of all processing logic, any pipeline acts like a clocked-logic conceptual framework. I offer this de- series of storage elements through which data can pass. scription of micropipelines in the hope of focusing at- Pipelines can be clocked or event-driven, depending tention on an alternative transition-signalling concep- on whether their parts act in response to some widely- tual framework. distributed external clock, or act independently when- We need a new conceptual framework because the ever local events permit. Some pipelines are inelastic; complexity of VLSI technology has now reached the the amount of data in them is fixed. The input rate and point where design time and design cost often exceed the output rate of an inelastic pipeline must match ex- fabrication time and fabrication cost. Moreover, most actly. Stripped of any processing logic, an inelastic pipe- systems designed today are monolithic and resist mid- line acts like a shift register. Other pipelines are elastic; life improvement. The transition-signalling conceptual the amount of data in them may vary. The input rate framework Offers the opportunity to build up complex and the output rate of an elastic pipeline may differ systems by hierarchical composition from simpler momentarily because of internal buffering. Stripped of pieces. The resulting systems are easily modified. I be- all processing logic, an elastic pipeline becomes a flow- lieve that the transition-signalling conceptual frame- through first-in-first-out memory, or FIFO. FIFOs may work has much to offer in reducing the design time and be clocked or event-driven; their important property is cost of complex systems and increasing their useful life- time. I offer this description of micropipelines as an example of the transition-signalling conceptual frame- © 1989 ACM OOOl-O782/89/o6oo-o72o $1.5o work. 720 Communications of the ACM June 1989 Volume 32 Number 6 Turing Award Until recently only a hardy few used the transition- of control called transition signalling. In return for signalling conceptual framework for design because it moving into the transition-signalling conceptual flame- was too hard. It was nearly impossible to design the work, we are rewarded with three new types of flexi- small circuits of 10 to 100 transistors that form the bility. In hardware design we attain a new flexibility to elemental building blocks from which complex systems compose systems from small parts previously designed are composed. Moreover, it was difficult to prove any- and tested; in software, we achieve a new flexibility to thing about the resulting compositions. In the past five handle vectors of variable length; and in systems we years, however, much progress has been made on both enjoy a new flexibility to extend system life by replac- fronts. Charles Molnar and his colleagues at Washing- ing isolated parts whenever components with improved ton University have developed a simple way to design speed or cost become available. the small basic building blocks [9]. Martin Rem's "VLSI It is often hard to discard a conceptual framework. Club" at the Technical University of Eindhoven has The well-known puzzle shown in Figure 1 illustrates been working effectively on the mathematics of event- this difficulty by asking us to draw four straight lines driven systems [6, 10, 11, 19]. These emerging concep- through nine dots without lifting our pencil from the tual tools now make transition signalling a lively candi- paper. Our natural conception of figure and ground in date for widespread use. looking at this puzzle suggests that the lines to be drawn should stay within the square of dots, a concep- tual framework that renders the task impossible. The TWO CONCEPTUAL FRAMEWORKS puzzle can be solved only by drawing outside the In the clocked-logic conceptual framework, registers of boundary of the dots. flip flops operating from a common clock separate Similar difficulty in discarding a conceptual flame- stages of processing logic. Each time the clock enters its work can be seen in the design of FIFOs. Conventional active state a new data element enters each register. wisdom in the clocked-logic conceptual framework says Data elements march forward through successive regis- that each stage of a flow-through FIFO should have a ters in lock step, each taking a fixed number of clock clocked register that feeds its output to the input of the cycles to pass through the fixed number of registers and next stage. Now recall that a FIFO must be elastic; it intervening logic stages built into the system. The must be able to store a variable amount of data; and if clocked-logic conceptual framework is widely used 1} it has a fixed number of stages, some of them may be because it offers a simple way to design computing unoccupied. Continuing with the clocked-logic concep- equipment, 2) because it is widely taught and under- tual framework, a "full" or "empty" clocked flip flop for stood, 3) because parts that operate with clocks are each stage is required to make the FIFO elastic. widely available, and 4) because system noise has died Each stage must also have logic involving the state of away by the time a clock event occurs. its full or empty flip flop and the states of other stages To build the micropipelines described here we must to decide when to capture new data. One simple con- discard the clocked-logic conceptual framework and trol rule operates as follows: a) Each stage captures new think instead about a different but equally simple form data and sets its full flip flop to the full state whenever f~ \/ FIGURE 1. A Puzzle 0 0 Without lifting your pencil from the paper, connect the dots with four straight lines. June 1989 Volume 32 Number 6 Communications of the ACM 721 Turing Award it is empty and its predecessor is full. b) Each stage sets TRANSITION SIGNALLING its full flip flop to the empty state whenever it is full In transition signalling any transition, either rising or and its successor is empty. This rule delivers output falling, has the same meaning, as illustrated in Figure 2; data only on alternate clock cycles. More complex rules either kind of transition is called an event. As indicated for the control of synchronous FIFOs get better perfor- in the figure, and suggested by its name, transition sig- mance by looking ahead many stages to decide if an nalling avoids distinguishing between the two types of entire block of data can move forward during the forth- transitions even though they may look quite different. coming cycle. The clocked-logic conceptual framework In effect, all responses to transition signals are edge- itself creates this complexity, because all registers must triggered, and are triggered on both rising and falling act together at once; any that fail to act now must suffer edges. Because transition signalling uses both rising and a complete cycle of delay for their next opportunity. falling edges as trigger events, it may offer twice the The clocked-logic conceptual framework is poorly matched to FIFO design for another reason as well: FIFOs often connect senders and receivers that have I separate clocks.