AGIGARAM® DDR4 Registered Non-Volatile DIMM (NVDIMM-N) AGIGA8811 (“Komodo1”) Datasheet
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After the 3D Xpoint Take-Off, Emerging NVM Keeps Growing1
Press Release February 26, 2020 LYON, France After the 3D XPoint take-off, emerging NVM keeps growing1 OUTLINES: PCM2-based persistent memory hit the market in 2019. And embedded STT-MRAM3 has finally moved into mass production. The overall emerging NVM4 market is poised to reach over US$6 billion in 2025. The embedded business will account for 1/3 of it. Foundries and IDMs5 are accelerating the adoption of embedded emerging NVMs at advanced technology nodes. Rise of in-memory computing is triggering new players’ dynamics. “The stand-alone emerging NVM market will grow to over US$4 billion in 2025”, explains Simone Bertolazzi, PhD. Technology & Market Analyst at Yole Développement (Yole). “It will be driven by two key segments: low-latency storage (enterprise and client drives) and persistent memory (NVDIMMs).” 1 Extracted from Emerging Non-Volatile Memory, Yole Développement, 2020 2 PCM: Phase-Change Memory 3 STT- MRAM : Spin-Transfer Torque Magnetoresistive RAM 4 NVM: Non-Volatile Memory 5 IDM : Integrated Design Manufacturer Press Release The embedded emerging NVM entered the takeoff phase. The embedded market segment is showing a 118% CAGR6 between 2019 and 2025, reaching more than US$2 billion by 2025. In this dynamic context, the market research and strategy consulting company Yole, releases its annual memory report, Emerging Non-Volatile Memory. The 2020 edition presents an overview of the semiconductor memory market with stand-alone7 and embedded memories8. Yole’s memory team proposes today a deep understanding of emerging NVM applications with related market drivers, challenges, technology roadmap, players, and main trends. This report also offers detailed 2019-2025 market forecasts. -
Will Carbon Nanotube Memory Replace DRAM?
Will Carbon Nanotube Memory Replace DRAM? Bill Gervasi Nantero, Inc. Abstract—In this paper, we discuss an exciting memory technology made from carbon nanotubes. Carbon nanotubes provide a predictable resistive element that can be used to fabricate very dense and very fast-switching memory cells. Nantero NRAM employs electrostatic forces to connect and disconnect these nanotubes in a memory design notably impervious to external effects including heat, shock and vibration, magnetism, and radiation. NRAM maintains its state permanently and may be rewritten arbitrarily many times without degrading. Not only NRAM is well positioned to replace DRAM in existing applications, but also its combination of high speed, persistence, density, and low power enables a slew of exciting new applications. Production of NRAM devices is on track for near-term commercialization through Nantero licensees. & CARBON NANOTUBES, ALSO known as CNTs, are CNT cells are arranged into arrays which may among the toughest constructions of atoms be presented to the host memory controller imaginable. They are incredibly strong and resil- with a custom interface or as any of the standard ient and remain neutral to external effects such memory interfaces including SDRAM. as heat, magnetism, and radiation. CNTs exhibit CNTs are inherently nonvolatile due to molec- a known resistance which is exploited to create ular binding forces that keep the nanotubes con- a memory cell. nected or separated. Data retention is measured A CNT memory cell is constructed with a sto- in centuries. The availability of high-speed persis- chastic array of hundreds of carbon nanotubes, tent memory enables a number of system-level depending on cell size. -
Embedded and Stand-Alone NVM: Two Different Futures?1
Press Release February 11th, 2021 LYON, France Embedded and stand-alone NVM: 1 two different futures? OUTLINE: • Embedded NVM market: Market forecasts: Yole Développement (Yole) forecasts a ~US$1.7 billion embedded MRAM2 market in 2026, which corresponds to ~76% of the overall embedded emerging NVM3 market. Technology trends: embedded emerging NVM is ready for takeoff, driven by MCUs4, IoTs5, as well as memory buffers for ASIC6 products. Supply chain: the embedded MRAM market is expected to grow rapidly thanks to the involvement of top foundries – TSMC, Samsung GlobalFoundries, UMC – and the first leading MRAM adopters (e.g., Sony). • Stand-alone NVM market: Market forecasts: the market will grow from ~US$595 million in 2020 to ~US$3.3 billion in 2026. The stand-alone PCM7 market is expected to grow to ~US$2.6 billion in 2026. It will represent about 78% of the overall stand-alone memory market at this time. Technology trends: PCM will be the leading technology thanks to the sales of 3D XPoint products – particularly persistent memory DIMMs8 – that are sold by Intel in a bundle with its server CPUs9. Supply chain: the stand-alone emerging NVM market will be driven by two major segments, namely persistent memory and low-latency storage. 10 “The overall emerging NVM market will grow at a CAGR20-26 ~44% ”. asserts Simone Bertolazzi, Market & Technology Analyst, Memory at Yole Développement (Yole). “After several years in development, embedded emerging NVM technologies have gained significant maturity and are now ready for market take off.” -
A Plug-And-Play NVMM-Based I/O Booster for Legacy Systems
NVCache: A Plug-and-Play NVMM-based I/O Booster for Legacy Systems Remi´ Dulong∗, Rafael Piresz, Andreia Correia∗, Valerio Schiavoni∗, Pedro Ramalhetex, Pascal Felber∗, Gael¨ Thomasy ∗Universite´ de Neuchatel,ˆ Switzerland, [email protected] zSwiss Federal Institute of Technology in Lausanne, Switzerland, [email protected] xCisco Systems, [email protected] yTelecom SudParis/Insitut Polytechnique de Paris, [email protected] propose to split the implementation of the I/O stack between Abstract—This paper introduces NVCACHE, an approach that the kernel and the user space. However, whereas Strata and uses a non-volatile main memory (NVMM) as a write cache SplitFS make the user and the kernel space collaborate tightly, to improve the write performance of legacy applications. We compare NVCACHE against file systems tailored for NVMM we follow the opposite direction to avoid adding new code (Ext4-DAX and NOVA) and with I/O-heavy applications (SQLite, and interfaces in the kernel. Then, as DM-WriteCache [53] RocksDB). Our evaluation shows that NVCACHE reaches the or the hardware-based NVMM write cache used by high- performance level of the existing state-of-the-art systems for end SSDs, we propose to use NVMM as a write cache to NVMM, but without their limitations: NVCACHE does not limit boost I/Os. Yet, unlike DM-WriteCache that provides a write the size of the stored data to the size of the NVMM, and works transparently with unmodified legacy applications, providing cache implemented behind the volatile page cache of the kernel additional persistence guarantees even when their source code and therefore cannot efficiently provide synchronous durability is not available. -
Improving Phase Change Memory Performance with Data Content
Improving Phase Change Memory Performance with Data Content Aware Access Shihao Song Anup Das Drexel University Drexel University USA USA Onur Mutlu Nagarajan Kandasamy ETH Zürich Drexel University Switzerland USA Abstract unknown content only when it is absolutely necessary to Phase change memory (PCM) is a scalable non-volatile mem- do so. We evaluate DATACON with workloads from state- ory technology that has low access latency (like DRAM) of-the-art machine learning applications, SPEC CPU2017, and high capacity (like Flash). Writing to PCM incurs sig- and NAS Parallel Benchmarks. Results demonstrate that nificantly higher latency and energy penalties compared to DATACON improves the effective access latency by 31%, reading its content. A prominent characteristic of PCM’s overall system performance by 27%, and total memory sys- write operation is that its latency and energy are sensitive to tem energy consumption by 43% compared to the best of the data to be written as well as the content that is overwrit- performance-oriented state-of-the-art techniques. ten. We observe that overwriting unknown memory content CCS Concepts: • Hardware ! Memory and dense stor- can incur significantly higher latency and energy compared age; • Software and its engineering ! Main memory. to overwriting known all-zeros or all-ones content. This is because all-zeros or all-ones content is overwritten by pro- Keywords: phase change memory (PCM), performance, en- gramming the PCM cells only in one direction, i.e., using ergy, hybrid memory, DRAM, non-volatile memory (NVM) either SET or RESET operations, not both. In this paper, we propose data content aware PCM writes ACM Reference Format: (DATACON), a new mechanism that reduces the latency Shihao Song, Anup Das, Onur Mutlu, and Nagarajan Kandasamy. -
Annual Update on Flash Memory for Non-Technologists Jay Kramer
Annual Update on Flash Memory for Non-Technologists Jay Kramer, Network Storage Advisors & George Crump, Storage Switzerland Santa Clara, CA August 2017 1 Memory / Storage Hierarchy Flash Memory Summit 2017 Santa Clara, CA 2 NAND Flash Solutions What’s an SSD? § Solid State Disk – all electronic, no moving parts § As opposed to the Hard Disk Drive (HDD) – electromechanical § SSDs typically use NAND flash for the persistence layer § SSD have evolved from 2D NAND to 3D NAND (future MRAM, RRAM, STT-RAM, PCM) Why SSDs? § Can address different Use Cases for capacity, speed, endurance, & price § Have now surpassed HDDs in density (capacity per physical size) SSD Packaging Options § SSDs come in various form factors § 2.5” and 3.5” form factor with U.2 connector – SATA, SAS, or NVMe § M.2 and M.3 form factor – SATA or NVMe § Add-in card form factor – PCI-Express – NVMe Santa Clara, CA August 2017 3 NAND Flash Solutions Evolution of flash form factor with bits per cell packaging: § SLC – single level cell – the first form of NAND § Nice and simple – and fast with high PE cycles – but not dense § MLC – multiple level cell – aka two-bits per cell § Slower than SLC and fewer PE cycles but more dense § TLC – triple level cell – three bits per cell § Slower than MLC and fewer PE cycles but more dense § QLC – four bits per cell § Slow to read & write and lower endurance - WORM (Write Once Read Many) flash use As we move from SLC through MLC to TLC and on to QLC we get higher density and lower cost…. -
Understanding the Idiosyncrasies of Real Persistent Memory
Understanding the Idiosyncrasies of Real Persistent Memory Shashank Gugnani Arjun Kashyap Xiaoyi Lu The Ohio State University The Ohio State University The Ohio State University [email protected] [email protected] [email protected] ABSTRACT form of Intel Optane DC Persistent Memory Module (DCPMM) High capacity persistent memory (PMEM) is finally commercially only recently. Researchers have not been waiting idly for its arrival. available in the form of Intel’s Optane DC Persistent Memory Mod- Over the last decade, a significant body of work has attempted to ule (DCPMM). Researchers have raced to evaluate and understand design transactional abstractions [3, 7, 17, 40, 55], persistent data the performance of DCPMM itself as well as systems and applica- structures [4, 10, 16, 22, 41, 43, 44, 49, 54, 56, 65], and file, key-value, tions designed to leverage PMEM resulting from over a decade of and database systems [2, 6, 8, 11–14, 19, 27, 28, 36, 42, 47, 59–61] research. Early evaluations of DCPMM show that its behavior is for PMEM. Most of these works use emulation to replicate PMEM more nuanced and idiosyncratic than previously thought. Several performance. Only a small subset [6, 11, 22, 36, 41, 43, 44] evaluate assumptions made about its performance that guided the design of with real PMEM (DCPMM). Now that DCPMM is commercially PMEM-enabled systems have been shown to be incorrect. Unfor- available, researchers have raced to evaluate its performance char- tunately, several peculiar performance characteristics of DCPMM acteristics. Several recent evaluation studies [35, 39, 62, 63] have are related to the memory technology (3D-XPoint) used and its shown that PMEM behavior is more idiosyncratic and nuanced internal architecture. -
Three Use Cases for Storage Class Memory (Scm)
THREE USE CASES FOR STORAGE CLASS MEMORY (SCM) Hussein Baligh Lina Eissa Senior Advisor, Sales Engineer Analyst Associate Sales Engineer Analyst Dell Technologies Dell Technologies [email protected] [email protected] Ebrahim Serag Abdelrahman El Nakeeb Associate Sales Engineer Analyst Data Center Account Manager Dell Technologies Dell Technologies [email protected] [email protected] Knowledge Sharing Article © 2020 Dell Inc. or its subsidiaries. The Dell Technologies Proven Professional Certification program validates a wide range of skills and competencies across multiple technologies and products. From Associate, entry-level courses to Expert-level, experience-based exams, all professionals in or looking to begin a career in IT benefit from industry-leading training and certification paths from one of the world’s most trusted technology partners. Proven Professional certifications include: • Cloud • Converged/Hyperconverged Infrastructure • Data Protection • Data Science • Networking • Security • Servers • Storage • Enterprise Architect Courses are offered to meet different learning styles and schedules, including self-paced On Demand, remote-based Virtual Instructor-Led and in-person Classrooms. Whether you are an experienced IT professional or just getting started, Dell Technologies Proven Professional certifications are designed to clearly signal proficiency to colleagues and employers. Learn more at www.dell.com/certification 2020 Dell Technologies Proven Professional Knowledge Sharing 2 Table of Contents