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M Morpho of Sm Ologica Mall-Sp S Al, Phy Pore a Solana Siolog
Vol. 8(37), pp. 3422-3434, 10 September, 2014 DOI: 10.5897/AJMR2014.6802 Article Number: B5A96EE47927 ISSN 1996-0808 African Journal of Microbiology Research Copyright © 2014 Author(s) retain the copyrighht of this article http://www.academicjournals.org/AJMR Full Length Research Paper Morphological, physiological and pathogenic variability of small-spore Alternaria sp. causinng leaf blight of Solanaceous plants in Allgeria BESSADAT Nabahat1*, SIMONEAU Philippe2, BENICHOU Soumaya1, SETTI Benali3, Kihal Mabrouk1 and HENNI Djamel Eddine1 1Laboratoire de Microbiologie Appliquée, Université d’Oran Es-Senia, BP15224 El M’naouer 31000 Oran, Algeria. 2SFR QUASAV 4207, UMR 1345 IRHS, Université d’Angers, 2 boulevard Lavoisier, France. 3Institut des Sciences Agronomiques, Université de Chlef, Algeria. Received 25 February, 2014; Acceppted 9 June, 2014 Due to premature defoliation, early blight epidemics can cause major yield losses. Large-spore Alternaria species such as A. solani and A. tomatophila have long been recognized as important pathogens responsible for such blight disease in the famiily Solanaceeae and thus represent a serious risk for crop production. Small-spore Alternaria species have also been frequently isolated from plant samples with typical blight symptoms but their incidence as primary pathogens is often controversial. In order to study the diversity of small-spore Alternaria species, 32 isolates were selected from a larger collection of 130 isolates from infected leaves, fruits and sttems of tomato from various growing regions of North-West Algeria. Morphological characterization under standard conditions annd polymerase chain reaction (PCR) analyses using specific primers to amplify a part of the ITS regions and the 5.8S gene were conducted to confirm their identification as members of the altternata section. -
Create Low-Power Applications with MQX™ and MQX™ Lite RTOS FTF-SDS-F0040
Hands-On Workshop: Create Low-Power Applications with MQX™ and MQX™ Lite RTOS FTF-SDS-F0040 Maclain Lobdell | Freescale Software Product Manager Vincent Leynaert | Freescale FAE APR.2014 TM External Use Hands-On Workshop: Create Low-Power Applications with MQX™ and MQX™ Lite RTOS FTF-SDS-F0040 4 Hour Class Learn how to take advantage of the power management capabilities of MQX and MQX Lite RTOS. See how to create feature-rich applications without killing battery life. Attendees will get hands-on experience with system power mode transitions, driver state transitions and slowing or stopping the system tick timer for power savings. TM External Use 1 Session Introduction • Power efficiency is an increasingly important part of embedded product design. Power consumption budgets are tightening even though performance expectations are ever increasing. • You can create power efficient applications while using an RTOS for sophisticated designs. TM External Use 2 Session Objectives • After completing this session you will be able to: − Understand how power management capabilities can be used in RTOS- based applications − Understand how to perform system power mode transitions, frequency scaling, driver state transitions, and slow or stop the RTOS system tick timer for power savings TM External Use 3 Agenda • Quick Review of MQX Software Solutions • Tools for Analyzing MCU Power • Kinetis MCU Low Power Features • MQX RTOS Power Management Features − Hands On • Optimizing Applications for Low Power − Optimizing/Disabling the System Tick Timer − Architecting -
We Shape the Connected World Automotive Autonomy Generating Energy Effectively Wearable Technology ARM’S Technology Is Cars Are Becoming Mobile Computing Platforms
ARM Holdings plc Annual Report 2015: Strategic Report We shape the connected world Automotive autonomy Generating energy effectively Wearable technology ARM’s technology is Cars are becoming mobile computing platforms. Wind turbines and solar panels can be made Smart watches, biometric-monitors and More sensors and cameras are being included more effective by including technology that augmented reality headsets are intelligent, to assist the driver with lane detection, reading controls and monitors the wind turbine, and connected devices that can give us extra shaping the way we roadside signage and identifying potential hazards aggregates data across the entire wind farm. information to improve our health and or people crossing the road. In time, driver wellness, or just to help us have more fun. all live our lives; in the assistance may lead to a fully automated vehicle. home, as we travel, at school or work, and as we have fun with our friends Mobile computing Smart city streets Intelligent networks Smarter homes ARM-based mobile computers, including City infrastructure from street lights to car Broadband and mobile phone network speeds Cost-efficiency in the home can be improved smartphones, tablets and some laptops are, parking meters can be made more effective by are increasing, and latency decreasing, enabling through learning thermostats that understand for many people, the primary device for their embedding intelligent chips. Street lights that new services for operators to provide to your daily routine, domestic appliances that use work, whether in an office or on the road; can dim when no one is nearby will save energy consumers and enterprises, from delivering advanced algorithms for calculating water and for researching and writing school assignments; and reduce carbon emissions, and prognostics in more movie and TV options to collating and detergent requirements, and smart meters that and for engaging with friends. -
Internet & Connectivity
Cover - 228.qxp 6/10/2009 8:42 AM Page 1 Battery-in-a-Chip Technology p. 62 • Up & Running With C Language p. 70 www.circuitcellar.com CIRCUITTHE MAGAZINE FOR COMPUTER CELLAR APPLICATIONS #228 July 2009 INTERNET & CONNECTIVITY Internet-Based Weather Data Acquisition A Compact Webcam Design From Start to Finish Ethernet-Controlled HERMS Text Library for Real-Time Translation I2C Master Bus Controller $5.95 U.S. ($6.95 Canada) C2.qxp 1/29/2009 10:42 AM Page 1 1.qxp 4/3/2009 10:20 AM Page 1 25.qxp 4/27/2009 8:36 PM Page 1 3.qxp 6/2/2009 1:42 PM Page 1 Let your geek shine. Meet Vanessa Carpenter and Diesel Møbius, SparkFun customers and developers of the Critical Corset. Using a Polar heart rate monitor, an Arduino, and a cleverly hidden air pump system, Vanessa and Diesel designed a corset that explores the rules of attraction. As the user’s heart rate increases, the corset gently tightens, creating a more confident posture. Whether you need a heart rate monitor or just a handful of LEDs, the tools are out there. Create a project you’ll love, and let your geek shine too. Sharing Ingenuity WWW.SPARKFUN.COM ©2009 SparkFun Electronics, Inc. All rights reserved. For more info on Vanessa and Diesel’s project visit www.illutron.dk. SFE-0015-PrintAd05-CircuitCellar.indd 1 5/19/09 4:49 PM Task_Masthead_228.qxp 6/12/2009 8:46 AM Page 4 ASK ® TMANAGER CIRCUIT CELLAR THE MAGAZINE FOR COMPUTER APPLICATIONS ’Net Tech and You FOUNDER/EDITORIAL DIRECTOR Steve Ciarcia CHIEF FINANCIAL OFFICER Jeannette Ciarcia MANAGING EDITOR With each passing year, we receive more and more arti- C. -
ECE 4999: INDEPENDENT STUDY on PORTING AMBER CPU to DE1-SOC and ALTERA BUS Mohammad Saifee Dohadwala
ECE 4999: INDEPENDENT STUDY ON PORTING AMBER CPU TO DE1-SOC AND ALTERA BUS Mohammad Saifee Dohadwala Under the supervision of: Professor Bruce R. Land Fall 2016 Table of Contents Table of Figures ............................................................................................................................................ 2 1. Introduction ........................................................................................................................................... 3 2. FPGA .................................................................................................................................................... 3 3. Amber Core ........................................................................................................................................... 5 3.1 Amber 23 Pipeline Architecture ................................................................................................... 6 3.2 Registers ........................................................................................................................................ 6 3.3 Cache............................................................................................................................................. 7 4. Amber FPGA system ............................................................................................................................ 7 4.1 Clocks and Reset ........................................................................................................................... 8 4.2 BOOT Memory -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
MQX Board Support Package Porting Guide on KEIL By: Guo Jia
Freescale Semiconductor Document Number:AN4626 Application Note Rev. 0, 11/2012 MQX Board Support Package Porting Guide on KEIL by: Guo Jia Contents 1 Introduction 1 Introduction................................................................1 This application note is a supplement to AN4287: MQX Board 2 Introduction to MQX’s BSP......................................1 Support Package Porting Guide, available on freescale.com. 3 Steps to make a new BSP based on an AN4287 introduced how to create new BSP in CW7.2, CW10 existing BSP manually..............................................7 and IAR, but didn't cover KEIL embedded development products. So, this application note introduces how to create a 4 Using script tool to accelerate the new BSP in KEIL for porting. In addition, this document also process.......................................................................8 introduces a script tool to help make this procedure much 4.1 About the script tool.......................................8 easier. All the discussion in this application note is based on Freescale MQX™ RTOS 3.8.0. 4.2 Command for making a new BSP..................8 4.3 Command for deleting a BSP........................9 4.4 Command for making a new application project ........................................9 2 Introduction to MQX’s BSP 4.5 Command for backing up a BSP..................10 BSP masks the hardware details and provides the uniform 4.6 Command for installing a BSP....................11 interface to the operating system (OS). Before beginning to port a BSP for MQX, it must be known how MQX is 4.7 Preparation for using the organized and how it works. command......................................................11 Figure 1 shows the folder organization of MQX. The folders 5 Possible disadvantage of the script tool..................12 enclosed by red rectangular boxes (as shown in Figure 1) are 5.1 Deletion error (Deleting files or significant while porting a BSP. -
Linux Hardware Compatibility HOWTO Linux Hardware Compatibility HOWTO
Linux Hardware Compatibility HOWTO Linux Hardware Compatibility HOWTO Table of Contents Linux Hardware Compatibility HOWTO........................................................................................................1 Patrick Reijnen, <[email protected] (remove both "antispam.")>..1 1.Introduction...........................................................................................................................................1 2.Computers/Motherboards/BIOS...........................................................................................................1 3.Laptops..................................................................................................................................................1 4.CPU/FPU..............................................................................................................................................1 5.Memory.................................................................................................................................................1 6.Video cards...........................................................................................................................................2 7.Controllers (hard drive).........................................................................................................................2 8.Controllers (hard drive RAID)..............................................................................................................2 9.Controllers (SCSI)................................................................................................................................2 -
DRUG DELIVERY Review and Outlook I N D U S T R Y G R O W T H T O C O N T I N U E T H R O U G H N E W Technologies
SPECIAL REPORT DECEMBER 2011 DRUG DELIVERY REVIEW AND OUTLOOK INDUSTRY GROWTH TO CONTINUE THROUGH NEW TECHNOLOGIES The worldwide drug-delivery arena is growing each year as the increasing aging population is in need of improved methods of administration for products and therapies. Drug-delivery industry growth is being led by the United States as well as emerging markets. Oral forms remain the preferred method of drug-delivery administration. Gaining in popularity are parenteral, inhalation and implantable systems. Elements impacting the development of drug-delivery systems include reimbursement, environmental factors, and regulatory processes. Product developers are coming up with better ways to improve therapy performance and safety as patients become more involved in their treatments in an effort to cut down on costs. New electronic technologies for reusable systems and disposable devices are leading to improved sales of auto-injectors. Microneedle technology is on the rise so that medicine can be precisely delivered to areas in need of treatment. UBM CANON DATA PRODUCTS TABLE OF CONTENTS 828B Newtown-Yardley Road, Suite B Drug-Delivery Industry Overview . Page 3 Newtown, PA 18940 Drug-Delivery Company Overview . 8 United States Phone: +1 .215 .944 .9800 Drug-Delivery Prescription Products Fax: +1 .215 .867 .0053 Website: PharmaLive .com Awaiting Approval . 26 Steve Corrick Phase III . 29 VP and Executive Director UBM Canon Publishing Phase II/III . 36 steve .corrick@ubm .com Phase II . 37 Roger Burg Phase I/II . 46 VP, Operations Publications Division Phase I . 47 roger .burg@ubm .com +1 .310 .445 .4221 Preclinical Development . 50 Glenn Glasberg Companies . 52 Circulation and Marketing Director glenn .glasberg@ubm .com Drug-Delivery Medical Devices +1 .215 .944 .9810 Class I Devices – General Controls – 510(k) Exempt . -
Amber : Enabling Precise Full-System Simulation with Detailed Modeling
Amber*: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources Donghyun Gouk1, Miryeong Kwon1, Jie Zhang1, Sungjoon Koh1, Wonil Choi1,2, Nam Sung Kim3, Mahmut Kandemir2 and Myoungsoo Jung1 Yonsei University, 1Computer Architecture and Memory Systems Lab, 2Pennsylvania State University, 3University of Illinois Urbana-Champaign, http://camelab.org Abstract—SSDs become a major storage component in modern While most of the time simulation-based studies are nec- memory hierarchies, and SSD research demands exploring future essary to explore a full design space by taking into account simulation-based studies by integrating SSD subsystems into a different SSD technologies, it is non-trivial to put SSD-based full-system environment. However, several challenges exist to model SSDs under a full-system simulations; SSDs are composed subsystems into a full-system simulation environment. First, upon their own complete system and architecture, which employ even though SSDs are considered as storage or memory all necessary hardware, such as CPUs, DRAM and interconnect subsystems, in contrast to conventional memory technologies, network. Employing the hardware components, SSDs also require they are in practice incarnated on top of a complete, in- to have multiple device controllers, internal caches and software dependent, and complex system that has its own computer modules that respect a wide spectrum of storage interfaces and protocols. These SSD hardware and software are all necessary architecture and system organization. Second, SSDs consist to incarnate storage subsystems under full-system environment, of not only a storage backend (by having multiple flash pack- which can operate in parallel with the host system. -
A Real Time Operating System Survey
A Real Time Op erating System Survey John Ford 1 What the heck is a Real Time system anyway? From Donald Gillies: \A real-time system is one in which the correctness of the computations not only dep ends up on the logical correctness of the computation but also up on the time at which the result is pro duced. If the timing constraints of the system are not met, system failure is said to have o ccurred." From POSIX 1003.1: \Realtime in op erating systems: the ability of the op erating system to pro- vide a required level of service in a b ounded resp onse time" 2 What makes a good RTOS? A RTOS Real-Time Op erating System has to have a real-time kernel Good do cumentation Good device supp ort Good to ols 3 Why are there so darn many? Classes of RTOS low-end small { AMX { C-Executive { CMX { Precise/MQX { Nucleus { C-Task { RTEMS { eCOS 4 Why are there so darn many? Classes of RTOS Mid-range { RT-Linux { OS-9 { QNX { VRTX { VxWorks { RTEMS { eCOS 5 Why are there so darn many? Classes of RTOS High-end large { ChorusOS { LynxOS { RT-Linux { Solaris 6 How can I sort through this mess? A couple of examples of cho osing: High-end Solaris 2.X Virtual trigger connection beween the VLA and the 140 ft. Mid-range VxWorks Telescop e control Low-end C-Task Monitor and Control system for an Inertial Nav- igation System test stand 7 And now for something completely di erent Some \Free" RTOS options High-end RT-Linux Mid-range RT-Linux,RTEMS,eCOS Low-end C-Task,eCOS,uCOS,.. -
The Design of a Debugger Unit for a RISC Processor Core
Rochester Institute of Technology RIT Scholar Works Theses 3-2018 The Design of a Debugger Unit for a RISC Processor Core Nikhil Velguenkar [email protected] Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Velguenkar, Nikhil, "The Design of a Debugger Unit for a RISC Processor Core" (2018). Thesis. Rochester Institute of Technology. Accessed from This Master's Project is brought to you for free and open access by RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. The Design of a Debugger Unit for a RISC Processor Core by Nikhil Velguenkar Graduate Paper Submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Approved by: Mr. Mark A. Indovina, Lecturer Graduate Research Advisor, Department of Electrical and Microelectronic Engineering Dr. Sohail A. Dianat, Professor Department Head, Department of Electrical and Microelectronic Engineering Department of Electrical and Microelectronic Engineering Kate Gleason College of Engineering Rochester Institute of Technology Rochester, New York March 2018 To my family and friends, for all of their endless love, support, and encouragement throughout my career at Rochester Institute of Technology Abstract Recently, there has been a significant increase in design complexity for Embedded Sys- tems often referred to as Hardware Software Co-Design. Complexity in design is due to both hardware and firmware closely coupled together in-order to achieve features forlow power, high performance and low area. Due to these demands, embedded systems consist of multiple interconnected hardware IPs with complex firmware algorithms running on the device.