TO APPEAR IN IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS 1 Wideband TV White Space Transceiver Design and Implementation Ross A. Elliot, Martin A. Enderwitz, Keith Thompson, Louise H. Crockett, Stephan Weiss and Robert W. Stewart

Abstract—For transceivers operating in television white space The permitted interference levels outlined in Fig. 1 cannot (TVWS), frequency agility and strict spectral mask fulfilments be met by standard orthogonal frequency division multiplex- are vital. In the UK, TVWS covers a 320 MHz wide frequency ing (OFDM). Therefore, filter bank techniques that pre-date band in the UHF range, and the aim of this paper is to present a wideband digital up- and down converter for this scenario. OFDM [8]–[11] have recently seen a revival in the form Sampling at RF, a two stage digital conversion is presented, of filter bank-based multicarrier (FBMC) modulation [12]– which consists of a polyphase filter for implicit upsampling and [14] due to their superior spectral confinement and resulting decimation, and a filter bank-based multicarrier approach to advantages in terms of synchronisation over OFDM [15]–[17]. resolve the 8MHz channels within the TVWS band. We demon- Most FBMC transceivers operate in the baseband, where a strate that the up- and down-conversion of 40 such channels is hardly more costly than that of a single channel. Appropriate number of subchannels or multiple users are allocated to well filter design can satisfy the mandated spectral mask and control defined frequency bands. Popular structures include discrete the reconstruction error. An FPGA implementation is discussed, Fourier transform (DFT) modulated filter banks [8], [15] capable of running the wideband transceiver on a single Virtex-7 and derivatives [18], but also iterated halfband schemes such device with sufficient word length to preserve the spectral mask as [11]. Many filter bank schemes currently evolving in the requirements of the system. context of frequency agility and cognitive radio [19], [20] are Index Terms—software radio; white space; filter banks; wide- also located in the baseband. In the context of software radio, band transceiver. recently a number of implementations of wideband receivers based on filter banks have been discussed [21]–[24], whereby I.INTRODUCTION very high-speed implementations such as [23] are restricted The switch from analogue to digital television (TV) has to essentially a DFT, while more flexible filter bank designs resulted in the local availability of benign wireless commu- such as [21], [22] do not comment on complexity or attempt nications channels in the so-called TV white space (TVWS) a real-time implementation. spectrum, which has triggered a number of important appli- Based on initial design work in [25], [26] for a two stage cations including rural broadband access [1], [2]. The latter architecture and a low-rate implementation in [27], this paper also offers infrastructure for smart grid [3] and potentially 5G explores the design and real-time FPGA implementation of services. In the UK, the TVWS spectrum ranges from 470 to a wideband TVWS frequency agile transceiver. In order to 790 MHz and is divided into 40 channels of 8 MHz bandwidth accomplish an implementation, different from [25], the number each. Wireless transmission over TVWS sets a number of re- of subbands is restricted to a power of 2. Below, Sec. II quirements to potential devices, including frequency agility in outlines the overall system, while Sec. III provides some order to select and change channels depending on geolocation, design details. The multirate implementation and its impact and the strict adherence to spectral masks which are likely to on complexity and latency are explored in Sec. IV, and be imposed by regulators to protect incumbent users [4]. demonstrated in Sec. V. This design is ported onto a Xilinx With substantial progress in the area of analogue-to-digital Virtex-7 in Sec. VI, with conclusions drawn in Sec. VII. (ADC) and digital-to-analogue conversion (DAC), see e.g. [5]– [7] where devices can operate close to 3GHz, software de- II. SYSTEM CONFIGURATION fined radio transceivers that exhibit the frequency agility and The proposed transceiver aims to downconvert all 40 chan- flexibility required of future TVWS devices appear viable. nels covering the UK’s TVWS spectrum from 470MHz to Therefore, the aim of this paper is to explore a transceiver 790MHz. The upconverter in the transmitter must adhere to design and implementation that is capable of converting the the strict spectral mask shown in Fig. 1, which regulators entire 320 MHz TVWS range from and to RF, and discuss some of its characteristics in terms of cost, latency, and selectivity. PSD 8 MHz 8 MHz 8 MHz 8 MHz 8 MHz 0 dB

The work of S. Weiss and K. Thompson was supported by the Engi- ≈ ≈ ≈ neering and Physical Sciences Research Council (EPSRC) Grant number -55 dB EP/K014307/1 and the MOD University Defence Research Collaboration in f Signal Processing. -69 dB ≈ The authors are with the Dept. of Electronic & Electrical Engineer- l − 2 l − 1 l l + 1 l + 2 channel index ing, University of Strathclyde, Glasgow, Scotland; e-mail: {ross.elliot, stephan.weiss}@strath.ac.uk. Fig. 1. Spectral mask defining permitted power sepctral density (PSD) levels in adjacent (l ± 1) and next-adjacent (l ± 2) TVWS channels [4]. TO APPEAR IN IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS 2

−jΩn |

e )

s (i) fs/K1 . FBMC . p/s × PPF . p/s DAC (i) (i)

. . . πf/f BT,1 320MHz BT,1

Tx 2 fs, Rtx j e

(i) (i) (i) (i) ( aliasing

)

L K L K RF i

( 2 2 1 1 1 after decimation f

jΩn H

| f , R ≈ baseband e s rx 470MHz 630MHz 790MHz . FBMC . s/p × PPF . s/p ADC . Rx . . Fig. 3. Stage 1 filter with passband width of 320MHz to capture TVWS stage 2 stage 1 (i) spectrum, and with transition bandwidth BT,1 depending on the selected (i) Fig. 2. Proposed multi-stage TVWS filter bank transmitter (above) and decimation ratio K1 . receiver (below) with a polyphase filter (PPF) in stage 1 and an FBMC modulator in stage 2. (i) FBMC, K2 , to be a power of 2. This differs from a previous design [25] and will enable the realisation on an FPGA to be are expected to impose [4]. While OFDM-based standards discussed in Sec. VI. generally exhibit too poor a frequency selection to comply with this mask, filter bank based multicarrier (FBMC) sys- A. Polyphase Filter — Stage 1 tems can provide sufficient frequency selectivity to fulfil this specification. In the filter bank receiver, stage 1 extracts the TVWS bands The implementation of an FBMC system is numerically with a centre frequency fc = 630MHz from the RF signal most efficient with a single filter bank, as it requires fewer sampled at fs = 2.048 GHz, to create an analytic baseband coefficients and therefore lower latency than an iterated fil- signal with TVWS channels aligned from DC to 320MHz. ter bank with several stages leading to interpolated FIR This can be achieved by means of an analytic bandpass filter filters [28]. However, targeting an FPGA implementation, centred at fc, whose bandlimitation will allow decimation by (i) there is a limit to the sampling rate of such devices. Using a factor K1 . The required filter characteristic is shown in a polyphase structure, data can be externally multiplexed Fig. 3, whereby aliasing is permitted in the transition band, (i) and demultiplexed into a limited number of streams, with therefore enabling a transition bandwidth BT,1, polyphase components running on the FPGA at a lower rate. 2.048GHz (i) − (1) Therefore, a two-stage approach is adopted, with the proposed BT,1 = (i) 320MHz . transceiver system outlined in Fig. 2. K1 On the transmitter side — the upper branch in Fig. 2 (i) ∈ Positive definiteness of (1) admits decimation ratios K1 — stage 2 combines 40 TVWS baseband channels each of (2) [1, 4]. The setting K1 = 4 leads to 512 MHz signals 8 MHz bandwidth by means of an FBMC synthesis bank into which can be realistically interfaced with an FPGA. Instead a baseband signal that feeds into stage 1. Stage 1 comprises of filtering at RF and decimating afterwards, a polyphase a polyphase filter, which, together with a position correcting (2) −jΩn approach will create K1 reduced-rate signals, which are term e , will translate the baseband signal to the UHF (2) then fed into a polyphase network operating at f /K . The range of 470–790 MHz, with a sampling rate f and a word s 1 s polyphase decomposition of the RF signal was previously length R . The real part of the analytic outputs is then fed to tx accomplished by hardware demultiplexers [25], but instead a DAC at RF. the polyphase structure can here be fed by demultiplexed data The receiver in the lower branch of Fig. 2 operates a dual streams available in recent ADCs such as [6]. design to the transmitter. In stage 1, the RF signal is sampled The case K(1) < 4 leads to rates that cannot be directly at f with worrd length R . A complex-valued polyphase 1 s rx interfaced with the FPGA, unless oversampled polyphase bandpass filter creates an analytic signal which is appropriately structures are employed. To demonstrate the trade-off of a modulated with a complex exponential of normalised angular lower decimation in stage 1, we will also be discussing the frequency Ω such that the 40 channels of the TVWS spectrum (1) case K1 = 2. The resulting requirements for the design of lie flush at DC. In stage 2, an analysis filter bank implementing (i) the FBMC receiver extracts the 40 TVWS baseband channels. the polyphase filter H1 (z) are outlined in Fig. 3. Oversampled by a factor two, the outputs of the FBMC run To align the decimated TVWS spectrum with DC, a cor- at 16 MHz to ease the task of synchronisation, subsequent rection by the lower frequency of 470MHz after aliasing can · (i) filtering, and further down-conversion of the individual 8 MHz be accomplished by selecting Ω = 2π470MHz K1 /fs. channels. An alternative implementation would first demodulate the incoming signal by a complex exponential to DC, where a real- valued lowpass filter instead of the bandpass H(i)(ejΩ) could III. FILTER BANK TRANSCEIVER 1 be employed. After lowpass filtering, a second modulation step This section details the design of the proposed transceiver. would then re-align the decimated TVWS spectrum with DC, Two different designs i ∈ {1, 2} will be proposed, with a although this operation could also be corrected in stage 2 by (i) (i) decimation/expansion by K1 in stage 1, and K2 channels ensuring that the 8 MHz TVWS channels are extracted by (i) and a decimation/expansion by K2 /2 in stage 2. The compu- applying appropriate frequency offsets. tational complexity of the proposed system will be analysed The transmitter implementation of stage 1 is a dual of the later in Sec. IV, but favours the number of channels in the receiver, with a frequency shift by Ω followed by upsampling. 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(i) j2πf/fs |P2 (e )| TABLE I (i) (i) BANDWITHREDUCTIONS Ki FORDIFFERENTRECEIVERSTAGES i = 1, 2 BT,2 BT,2 WITH ASSOCIATED INCREASE IN BIT RESOLUTION ∆Ri, AND OTHER aliasing PERFORMANCEMEASURES. after decimation f Design i 1 2 -12MHz -8MHz -4MHz 0 4MHz 8MHz 12MHz (i) K1 2 4 Fig. 4. Stage 2 prototype filter with 8MHz passband width and decimation to (i) stage 1 ∆R1 / bits 0.5 1 16 MHz sampling rate. The absolute bandwidths are identical for all designs, (i) (i) L1 12 44 which however differ in their number of bands K2 . (i) K2 128 64 (i) stage 2 ∆R2 / bits 3 2.5 (i) (i) Interpolation can be performed with the bandpass H (ejΩ), L2 640 320 1 (i) whereby the widened transition bands do not matter due to the C / GMAC/s 176.1 213.0 (i) input signal to stage 1 fulfilling tight frequency mask charac- delay ∆ / ns 83.7 40.5 reconstruction error / dB 62.9 63.1 teristics. The real part of the analytic signal at the bandpass adjacent channel leakage / dB -65.3 -64.1 output is then passed to a DAC operating at RF rate. The next-adj. channel leakage / dB -71.4 -72.2 filter is again implemented in polyphase structure, whereby (i) a polyphase network at fs/K1 operates on the FPGA with polyphase outputs interfaced to a hardware multiplexer [25]. multiplexers are often readily incorporated in state-of-the-art The latter is often already incorporated in state-of-the-art ADCs [6] and DACs [7]. DACs [7]. The implementation in Sec. III-A assumes a complex band- pass polyphase filter, combined with a frequency shift Ω. With (i) (i,a) (i) (i) B. Filter Bank-Based Multicarrier System — Stage 2 a filter length L1 , the complexity is C1 =4L1 /K1 +4 The two designs for stage 1 necessitate different filter real-valued multiply accumulates (MACs). Alternatively, the bank approaches for stage 2. With an RF sampling rate of stage 1 signal could be filtered by a real-valued lowpass filter, (i) (i) requiring a modulation at both the input and output of stage 2.048 GHz and decimations by K1 in stage 1, K2 = (i,b) (i) (i) (i) {128, 64} channels of 8 MHz bandwidth have to be extracted 1, leading to C1 =2L1 /(K1 )+4K1 +4. The second for the three designs in stage 2, respectively, as contained in implementation is only favoured if Tab. I. For each of the designs, only 40 of the K(i) channels 2 C(i,a) > C(i,b) ←→ L(i) > 2(K(i))2 , (2) will be utilised. Due to their uniform ordering, a modulated 1 1 1 1 filter bank is an efficient approach, which is oversampled by a i which for the selected values K( ) = {2, 4} is not satisfied. factor of two. Firstly, this eases the synchronisation efforts 1 For stage 2, different implementations are possible [15]. of individual TVWS channels in the baseband. Secondly, Since circular buffers are not advantageous for FPGA im- oversampling is advantageous as it relaxes the prototype filter plementations, we have selected polyphase implementations P (i)(z), which is outlined in Fig. 4, allowing a maximum 2 according to [30], which require only one tapped delay line, a possible transition bandwidth (i) . This design characteristic BT,2 set of multipliers, and the transform on which the modulated assumes that the TVWS channel inputs to Tx stage 2 are filter bank is based, such as in this case a DFT implemented perfectly bandlimited to 8 MHz. via a fast Fourier transform (FFT). We here employ a DFT modulated filter bank [29], where the analysis filter bank in the transmitter employs an inverse DFT and the synthesis bank in the receiver a DFT, in order to B. Computational Complexity and Latency align channels in ascending order from DC to 320 MHz. With the complexity of the stage 1 filter considered in (i) IV. IMPLEMENTATION ASPECTS,NUMERICAL EFFICIENCY, Sec. IV-A and the polyphase filter bank requiring 2L2 + (i) (i) AND ROBUSTNESS 4K2 log2 K2 multiply accumulates (MACs) [30] at the lower rate of stage 2, the total complexity of a transmitter This section elaborates on a potential FPGA implementa- or receiver as shown in Fig. 2 is given by tion, focusing on polyphase realisations in Sec. IV-A, on its computational complexity in Sec. IV-B and on word length i L( ) 4f considerations in Sec. IV-C. (i) (i) 2 (i) s (3) C = L1 + (i) + 2 log2 K2 +1 (i) , K2 ! K1 A. Polyphase Implementations measured in real-valued MACs/s. For stage 2, the complexity For stage 1, the receiver requires a hardware demultiplexer of up- and downconverting 40 channels with a DFT-modulated to feed K(i) polyphase components of the sampled RF signal filter bank is the same as for a single channel, plus the modu- 1 (i) into the FPGA for polyphase filtering, while in the transmitter, lating transform i.e. a K2 -point DFT. The overall complexity the output of the polyphase filter components are passed out of in (3) is likely to be dominated by the stage 1 filter of length (i) the FPGA implementation and will be multiplexed in hardware L1 , and is listed for the two different implementations in to form the RF signal. As mentioned before, such hardware Tab. I. TO APPEAR IN IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS 4

The latency of a filter bank transmitter or receiver, assuming 0 j2πf/fs (a) P2(e ) linear phase prototype filters, is given by mask L(i) L(i)K(i) −50 ∆(i) = 1 + 2 1 . (4) 2fs 2fs −100 The latency will be dominated by the lower rate stage 2 /magnitude [dB] −30 −20 −10 0 10 20 30 frequency f/ [MHz] filter, with the overall transmitter or receiver delay for the 0 j2πf/fs two implementations shown in Tab. I. (b) H1(e ) mask C. Word Length Requirements −50 To achieve the spectral mask as defined in Fig. 1, the −100 transmitter demands a dynamic range of -69dB [4], which /magnitude [dB] 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 frequency f/ [GHz] requires at least 12 bits word length all the way up to the Fig. 5. Magnitude responses of (a) stage 2 and (b) stage 1 prototype filters.

DAC. The DAC characterised in [7] offers a word length of 0 (a) PSD Rtx = 16 bits. Therefore, we here assume a 16 bit fixed −20 mask point resolution for the data as well as for the coefficients −40 of both stage 1 and 2 filters in the transmitter, with a higher −60 PSD / [dB] −80 resolution for the accumulators and appropriate scaling prior 0 50 100 150 200 250 300 350 400 450 500 to any rounding. frequency f/ [MHz]

In the receiver, the succession of filtering and decimation 0 (b) PSD leads to a gain in effective wordlength, whereby one extra bit mask of resolution is obtained for every oversampling by a factor of −50 4, since a reduction in bandwidth also leads to a reduction in

PSD / [dB] −100 noise power without curtailing signal power. Thus, the virtual 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 gain in bits for the proposed filter bank transceiver is ∆R = frequency f/ [GHz] 1 Fig. 6. PSDs of transmit signal after (a) stage 2 and (b) stage 1. dashed lines. log4 K = 2 log2 K, where K is the reduction in bandwidth. With the overall reduction in bandwith from 2.048 GHz to 2.048GHz 8 MHz, K = 8MHz = 256 yields a gain in resolution by ∆R =4 bits. B. Reconstruction Error and Adjacent Band Leakage The overall gain of ∆R = 4 bits is divided over the Testing the overall filter bank transceiver back-to-back as (i) (i) different filter bank stages into ∆R = ∆R1 + ∆R2 as shown in Fig. 2, the reconstruction error between a transmitted shown in Tab. I for the three different implementations. Thus, and received 5.33 MHz channel, as well as the leakage level the coefficient quantisation for each stage has to be selected into adjacent channels, is provided in Tab. I. The measured such that the greatest gain can be realised, requiring an extra mean square error between input and output is equivalent to resolution of at least 2 and 3 bits for stage 1 and 2 filters the reconstruction error of the filter bank, and therefore linked compared to their input signals, respectively. With this extra to the prototype filter design [31]. Due to the selection of the (i) resolution of ∆R = 4 bits, the targetted ADC [6] with filter lengths Lj for the jth stage in the ith design to comply Rrx = 12 bits therefore provides a resolution of 16 bits for with the overall desired spectral mask, all implementations the down-converted 8 MHz TVWS channels given processing meet the imposed requirement of at least -55dB for adjacent with appropriate word lengths throughout the receiver chain. and -69dB for next-adjacent channels [4].

V. DESIGN, SIMULATIONS AND RESULTS VI. FPGA REALISATION A. Filters and Power Spectral Densities Based on the complexity analysis in Sec. IV-B, the design The prototype filter for stage 1 is constructed using a mini- i = 2 with its more straightforward stage 1 but higher max design while stage 2 employs a root Nyquist system [31], computational complexity has been implemented on a Virtex-7 [32], with magnitudes shown in Fig. 5. Responses can be seen XC7VX550T using the Xilinx ISE 14.6 software suite. In the to satisfy the stopband edges and adjacent channel attenuation transmitter, the wordlength is maintained at 16 bits throughout of -69dB imposed by the spectral mask in Fig. 1 [4]. Only all stages to the output. In the receiver, a 12 bit signal is (2) (2) design i =2 using K1 =4 and K2 = 64 with its simpler obtained from the ADC, which is allowed to grow by the stage 1 as discussed in Sec. III-A and lower latency according appropriate gain in resolution up to 13 bits at the output of to Tab. I is demonstrated here. stage 1, and 16 bits at the output of stage 2, as outlined in The PSDs of simulated Tx signals after stages 1 and 2 Sec. IV-C. A complex exponential with 16 bit word length are shown in Fig. 6, whereby each TVWS channel is loaded performs the frequency shifts in both Tx and Rx. with a 5.33 MHz signal [25]. The stage 2 transmitter output, In order to ensure that the timing requirements were met containing the 320 MHz TVWS baseband across 40 of the with stage 1 running at 512MHz, post-place and route timing (2) K2 = 64 channels, is depicted in Fig. 6(a). Fig. 6(b) displays analysis was performed. The analysis reported a minimum the PSD of the stage 1 output occupying the TVWS band 470– clocking period of 1.606ns, giving a maximum operating fre- 790 MHz with the spectral mask satisfied. quency of 622MHz. Table. II lists the hardware resources used TO APPEAR IN IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS 5

TABLE II [7] “DAC39J82 dual-channel, 16-bit, 2.8 Gsps, digital-to-analog converter TRANSCEIVER HARDWARE RESOURCE UTILISATION ON A with 12.5 Gbps JESD204B interface,” Texas Instruments, data sheet, VIRTEX7-XC7VX550T FPGA DEVICE. Jan. 2015. logic utilisation number used available percentage used [8] M. Bellanger and J. Daguet, “TDM-FDM transmultiplexer: Digital polyphase and FFT,” IEEE Trans. Comms, 22(9):1199–1205, Sept. 1974. LUTs 83566 346400 24% [9] G. Bonnerot, M. Coudreuse, and M. Bellanger, “Digital processing FFs 63108 692800 9% techniques in the 60 channel transmultiplexer,” IEEE Trans. Comms, slices 26297 86600 30% 26(5):698–706, May 1978. DSP48E1 units 1748 2880 60% [10] F. Takahata, Y. Hirata, A. Ogawa, and K. Inagaki, “Development of a TDM/FDM transmultiplexer,” IEEE Trans. Comms, 26(5):726–733, May

0 1978. (a) PSD −20 mask [11] F. Molo, “Transmultiplexer realization with multistage filtering,” IEEE −40 Trans. Comms, 30(7):1614–1622, July 1982. [12] f. harris, C. Dick, and M. Rice, “Digital receivers and transmitters using −60 polyphase filter banks for wireless communications,” IEEE Trans. Mi- PSD / [dB] −80 crowave Theory and Techniques, 51(4):1395–1412, Apr. 2003. 0 50 100 150 200 250 300 350 400 450 500 [13] G. Cherubini, E. Eleftheriou, and S. Olcer,¨ “Filter Bank Modulation frequency f/ [MHz] Techniques for Very High-Speed Digital Subscriber Lines,” IEEE J. Se- 0 lected Areas of Comms, 20(5):1016–1028, May 2002. (b) PSD mask [14] S. Rahimi and B. Champagne, “Perfect reconstruction DFT modulated oversampled filter bank transceiver,” in European Signal Processing −50 Conference, Barcelona, Spain, Aug. 2011.

PSD / [dB] [15] A. Tonello and F. Pecile, “Efficient architectures for multiuser −100 FMT systems and application to power line communications,” IEEE 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Trans. Comms., 57(5):1275–1279, May 2009. frequency f/ [GHz] [16] S. Weiss, A. Millar, R. Stewart, and M. Macleod, “Performance of Fig. 7. PSDs after (a) stage 2 and (b) stage 1 obtained by a bit-true and cycle transmultiplexers based on oversampled filter banks under variable accurate simulation with 16 bit word length. oversampling ratios,” in 18th Europ. SP Conf., Aalborg, Denmark, Aug. 2010, pp. 2181–2185. by the design in terms of look up tables (LUTs), Flip-Flops [17] B. Farhang-Boroujeny, “OFDM versus filter bank multicarrier,” IEEE SP Mag., 28(3):92–112, May 2011. (FFs), DSP48E1s, and slices. Fig. 7 shows the PSDs obtained [18] J. Alhava and M. Renfors, “Exponentially-Modulated Filter Bank with a bit-true and cycle accurate simulation in Simulink, with Transmultiplexer with Fine-Coarse Adaptive Filtering,” in 3rd the system maintaining its spectral mask compliance. Int. Symp. Comms, Control & SP, Mar. 2008, pp. 68–72. [19] M. Iwabuchi, K. Sakaguchi, and K. Araki, “Study on multi-channel receiver based on polyphase filter bank,” in 2nd Int. Conf. SP & Comms VII. CONCLUSION Sys., 2008. [20] M. Lin, A. Vinod, and C. See, “Very low complexity variable resolution We have discussed a two-stage filter bank transceiver design filter banks for spectrum sensing in cognitive radios using multi-stage with the capability to simultaneously up- and downconvert coefficient decimation,” in 5th Int. Conf. Wirel. Comms, Networking and the entire UK’s TVWS range of 40 8 MHz wide channels Mobile Computing, Sept. 2009. [21] N. Mansour and D. Dahlhaus, “Interference in dft modulated filter bank by sampling at the radio frequency. The system satisfies transceivers for cognitive radio,” in 20th Europ. Wirel. Conf., May 2014. regulatory requirements w.r.t. the spectral mask as well as [22] f. harris, X. Chen, and E. Venosa, “Cascade of perfect reconstruction hardware limitations on the sampling rate and the FPGA analysis and synthesis filter banks: The new architecture of next gener- ation wideband receivers,” in Const. Int. Workshop SP, Jan. 2013. devices. Amongst two discussed parameterisations, a trade- [23] A. Tolmachev, M. Orbach, M. Meltsin, R. Hilgendorf, T. Birk, and off between complexity and latency arises. The design exploits M. Nazarathy, “Real-time FPGA implementation of efficient filter-banks additional word length resolution due to oversampling and can for digitally sub-banded coherent DFT-S OFDM receiver,” in Opt. Fiber Comms Conf., Mar. 2013. cope with fixed point implementations while still satisfying [24] M. Nazarathy and A. Tolmachev, “Subbanded DSP architectures based design requirements. Results of an FPGA implementation have on underdecimated filter banks for coherent OFDM receivers: Overview been reported, with the more costly design fitting comfortably and recent advances,” IEEE SP Mag., 31(2):70–81, Mar. 2014. [25] R. A. Elliot, M. A. Enderwitz, F. Darbari, L. H. Crockett, S. Weiss, and onto a Virtex-7 device. R. W. Stewart, “Efficient TV white space filter bank transceiver,” in 20th Europ. SP Conf., Bukarest, Romania, Aug. 2012, pp. 1079–1083. REFERENCES [26] R. A. Elliot, M. Enderwitz, F. Darbari, L. H. Crockett, S. Weiss, and R. Stewart, “Reconfigurable TVWS transceiver for use in UK and US [1] F. Darbari, M. Brew, S. Weiss, and R. Stewart, “Practical aspects of markets,” in 7th Int. Workshop on Reconf. Comm. Sys.-on-Chip, York, broadband access for rural communities using a cost and power efficient UK, July 2012. multi-hop/relay network,” in IEEE Global Communications Conference, [27] R. Elliot, M. Enderwitz, F. Darbari, L. Crockett, S. Weiss, and R. W. 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