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Traveo™ II Ethernet Mac Customer Training Workshop Traveo™ II Ethernet Mac Q1 2021 Target Products › Target product list for this training material Family Category Series Code Flash Memory Size Traveo™ II Automotive Body Controller High CYT3BB/4BB Up to 4160 KB Traveo II Automotive Body Controller High CYT4BF Up to 8384 KB Traveo II Automotive Cluster CYT3DL Up to 4160 KB Traveo II Automotive Cluster CYT4DN Up to 6336 KB 002-25166 *D 2021-02-12 Copyright © Infineon Technologies AG 2021. All rights reserved. 2 Introduction to Traveo II Body Controller High › Ethernet MAC is located in the peripheral blocks Hint Bar ITCM DTCM CPU Subsystem ITCM16 KB DTCM16 KB SWJ/ETM/ITM/CTI Review TRM section 31 for CYT4BF 16 KB 16 KB MXS40-HT SWJ/ETM/ITM/CTI SWJ/MTB/CTI additional details Cortex M7 143Channel M P P 65 Channel 65 ASIL-B eCT FLASH Channel 8 CRYPTO - - 350 MHz - DMA1 Arm Cortex-M7 SRAM0 SRAM1 SRAM2 DMA0 ROM 8384 KB Code Flash DMA0 AES, SHA, CRC, Arm 350 MHz 512 KB 256 KB 256 KB TRNG, RSA, 64 KB FPU D$ I$ + 256 KB Work Flash Cortex-M0+ (SP/DP) 16KB 16KB ECC System Resources FPU D$ I$ AHBP NVIC, MPU, AXI AHBS 100 MHz (SP/DP) 16 KB 16 KB 8 KB $ SRAM SRAM SRAM Power Initiator/MMIO ROM Controller AHBP NVIC, MPU, AXI AHBS FLASH Controller Controller Controller Controller MUL, NVIC, MPU Sleep Control POR BOD OVP LVD System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU) REF PWRSYS-HT LDO PCLK Peripheral Interconnect (MMIO, PPU) (Hyperbus,Memory Single SPI, Serial Interface Clock Clock Control SPI,DualQuadOctal SPI) SPI, 10/100/1000 Ethernet 10/100/1000 + AVB 2xILO WDT Prog. TIMER, IMO ECO Analog SD/SDIO/eMMC Event Event Generator I2C, I2C, 115xTCPWM I2S/TDM In/Out I2S/TDM 1x FLEXRAY 1x CAN FlexRay Interface FlexRay 3x AUDIOSS 3x 1x SMIF 1x 10x 10x CANFD FLL CSV 2x ETH SAR SDHC EVTGEN 10x 10x SCB SPI, SPI, 20x 20x LIN 1x SCB1x EFUSE LIN/UART - 4xPLL CTR, ADC FD Interface IOSSGPIO UART, (12-bit) UART, Reset QD, QD, PWM Reset Control LIN XRES LIN x3 Test TestMode Entry Digital DFT SARMUX Analog DFT 96 ch WCO RTC High-Speed I/O Matrix, Smart I/O, Boundary Scan 5x Smart I/O Power Modes Active/Sleep Up to 196x GPIO_STD, 4x GPIO_ENH, 40xHSIO LowPowerActive/Sleep DeepSleep I/O Subsystem Hibernate 002-25166 *D 2021-02-12 Copyright © Infineon Technologies AG 2021. All rights reserved. 3 Introduction to Traveo II Cluster › Ethernet MAC is located in the peripheral blocks Hint Bar ITCM DTCM CPU Subsystem GFX Subsystem ITCM64 KB DTCM64 KB CYT4DN SWJ/ETM/ITM/CTI Review TRM section 31 for 64 KB 64 KB MXS40-HT SWJ/ETM/ITM/CTI SWJ/MTB/CTI Cortex M7 Gfx Vector additional details M P P 76 ASIL-B 84 eCT FLASH Channel 8 CRYPTO - - - 320 MHz DMA0 DMA1 Channel Arm Cortex-M7 SRAM0 SRAM1 SRAM2 Channel ROM DMA0 VRAM 6336 KB Code Flash AES, SHA, CRC, Arm 320 MHz 256 KB 256 KB 128 KB TRNG, RSA, 64 KB 4096 KB FPU D$ I$ + 128 KB Work Flash Cortex-M0+ (SP/DP) 16KB 16KB ECC FPU D$ I$ AHBP NVIC, MPU, AXI AHBS 100 MHz (SP/DP) 16 KB 16 KB 8 KB $ SRAM SRAM SRAM System Resources Initiator/MMIO ROM Controller VRAM Controller AHBP NVIC, MPU, AXI AHBS FLASH Controller Controller Controller Controller MUL, NVIC, MPU Power Sleep Control POR BOD OVP LVD System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU) GFX Interconnect (AXI) REF PWRSYS-HT 2x RGB/LVDS Output 2x RGB/LVDS LDO PCLK Peripheral Interconnect (MMIO, PPU) SPI, (Hyperbus,Single Memory Serial Interface 1x RGB/MIPI Input 1x RGB/MIPI Clock 2.5D Engine Dual SPI, Quad SPI, OctalSPI, SPI)Quad Dual SPI, Clock Control 10/100 2xILO WDT Prog. TIMER, IMO ECO Analog /1000 Event Event Generator I2C, I2C, FLL CSV 2 CAN 82 2x SMIF 2x x PCMx 1x 1x ETH Audio DAC Audio 4x CANFD 4x CXPI CXPI Interface CTR, SAR EVTGEN 8xPLL LPECO 11x SCB 2 2x CXPI 2x SPI, SPI, x TCPWM x 4 1x SCB 1x EFUSE LIN/UART 2x LIN 2x 4 - Ethernet +AVB Ethernet 5x SG 5x x Mixerx x TDM x ADC FD Interface IOSSGPIO x I2S x Reset QD, QD, PWM, SMC UART, (12-bit) UART, Reset Control - XRES PWM LIN Test LIN TestMode Entry x1 Digital DFT Analog DFT SARMUX WCO 48 ch RTC Power Modes High-Speed I/O Matrix, Smart I/O, Boundary Scan Active/Sleep 1x Smart I/O LowePowerActive/Sleep 52x GPIO_STD, 8x GPIO_ENH, 26x GPIO_SMC, 70x HSIO_STD, 22x HSIO_ENH, 4x HSIO_ENG_DIFF DeepSleep Hibernate I/O Subsystem 002-25166 *D 2021-02-12 Copyright © Infineon Technologies AG 2021. All rights reserved. 4 Ethernet MAC Overview › Ethernet MAC1 module transmits and receives IEEE 802.3 frames by connectingHint Bar 2 with the PHY device Review TRM section 31.1 for additional details Review the device-specific datasheet to confirm ECU which PHY interfaces are Traveo II supported in the device Ethernet (10 Mbit/s) Dedicated PHY Fast Ethernet (100 Mbit/s) Ethernet MAC Gigabit Ethernet (1000 Mbit/s) (10/100/1000 Mbit/s) MII3 or RMII4 or GMII5 or RGMII6 and MDIO7 Physical Layer MAC Layer Network Interface Layer 1 MAC: Media Access Control 2 PHY: Physical layer 3 MII: Media Independent Interface 4 RMII: Reduced Media Independent Interface RMII is the standard for reducing the number of signals needed to connect the PHY to the MAC compared to MII 5 GMII: Gigabit Media Independent Interface 6 RGMII: Reduced Gigabit Media Independent Interface RGMII is the standard for reducing the number of signals needed to connect the PHY to the MAC compared to GMII 7 MDIO: Management Data Input/Output 002-25166 *D 2021-02-12 Copyright © Infineon Technologies AG 2021. All rights reserved. 5 Ethernet MAC Features › MII, RMII, GMII, and RGMII PHY interface Hint Bar › MDIO interface for PHY management Review TRM section 31.1 › 10/100/1000 Mbps Ethernet MAC compatible with IEEE 802.3 for additional details Review the device-specific › Full-duplex datasheet to confirm which PHY interfaces are › Jumbo frame1 (Max 1536 bytes) supported in the device › IEEE 802.1Q: Virtual LAN (VLAN) › IEEE 802.3: Pause frame › IEEE 802.1BA: Audio video bridging systems › IEEE 802.1Qav: Forwarding and queuing enhancements for time- sensitive streams › IEEE 802.1AS: Timing and synchronization for time-sensitive applications in bridged LANs › IEEE 1588 – Precision time protocol 1 Jumbo frame is not standardized by IEEE 002-25166 *D 2021-02-12 Copyright © Infineon Technologies AG 2021. All rights reserved. 6 Ethernet MAC Components › MAC control Hint Bar – PHY interface Review TRM section 31.2 for additional details – MAC transmitter/receiver Refer to the Features List in the datasheet for – Time stamp unit additional details AXI master interface AHB slave interface Review the device-specific › TX/RX packet memory datasheet to confirm Ethernet MAC which PHY interfaces are supported in the device › CLK control AXI Interface AHB2APB AHB Interface TX Packet Buff MAC Control (16KB) MMIO Time Stamp Unit Registers (TSU) RX Packet Buff (4KB) MAC Transmitter MAC Receiver clk_sys Clock clk_mem MII/RMII/GMII/RGMII PHY Interface Control clk_tsu and MDIO int_ref_clock 002-25166 *D 2021-02-12 Copyright © Infineon Technologies AG 2021. All rights reserved. 7 PHY Interface › Supports MII/RMII/GMII/RGMII PHY interface Hint Bar › Supports MDIO interface Review TRM section 31.3.14 for additional details AXI master interface AHB slave interface Review the device-specific datasheet to confirm which PHY interfaces are Ethernet MAC supported in the device AXI Interface AHB2APB AHB Interface TX Packet Buff MAC Control (16KB) MMIO Time Stamp Unit Registers (TSU) RX Packet Buff (4KB) MAC Transmitter MAC Receiver clk_sys Clock clk_mem MII/RMII/GMII/RGMII PHY Interface Control clk_tsu and MDIO int_ref_clock 002-25166 *D 2021-02-12 Copyright © Infineon Technologies AG 2021. All rights reserved. 8 PHY Interface Types › Supports the following interface types and transfer rates Hint Bar Review TRM Transfer Rate section 31.3.14 for additional details Interface Type Review the device-specific 10 Mbps 100 Mbps 1000 Mbps datasheet to confirm which PHY interfaces are supported in the device MII ✓ ✓ - RMII ✓ ✓ - GMII - - ✓ RGMII ✓ ✓ ✓ 002-25166 *D 2021-02-12 Copyright © Infineon Technologies AG 2021. All rights reserved. 9 MII/RMII/GMII/RGMII Interface › Supported signals: transmitter/receiver signals Hint Bar Pin Name Function of signals MII RMII GMII RGMII Review TRM section 31.3.14 and for TXD[1:0] Transmit data [1:0] ✓ ✓ ✓ ✓ additional details TXD[3:2] Transmit data [3:2] ✓ - ✓ ✓ See the Package Pin List and Alternate Functions in TXD[7:4] Transmit data [7:4] - - ✓ - the datasheet for TX_CTL Transmit enable ✓ ✓ ✓ ✓ additional details TX_ER Transmit error ✓ - ✓ - Review the device-specific datasheet to confirm TX_CLK Transmit clock ✓ ✓ ✓ ✓ which PHY interfaces are supported in the device RXD[1:0] Receive data [1:0] ✓ ✓ ✓ ✓ RXD[3:2] Receive data [3:2] ✓ - ✓ ✓ RXD[7:4] Receive data [7:4] - - ✓ - RX_CTL Receive data valid ✓ ✓ ✓ ✓ RX_ER Receive error ✓ ✓ ✓ - RX_CLK Receive clock ✓ - ✓ ✓ REF_CLK Operation clock out - ✓ ✓ ✓ Operation clock in - ✓ ✓ ✓ 002-25166 *D 2021-02-12 Copyright © Infineon Technologies AG 2021. All rights reserved. 10 Use Case: MII/RMII Interface MII Interface RMII Interface Hint Bar [PHY device] [Traveo II] [PHY device] [Traveo II] TXD[3:0] TXD[3:0] TXD[1:0] TXD[1:0] Review TRM section 31.3.14 for TXD[7:4] TXD[7:2] additional details TX_EN TX_CTL TX_EN TX_CTL TX_ER TX_ER TX_ER Review the device-specific TX_CLK TX_CLK TX_CLK datasheet to confirm 25 MHz for 100 Mbit/s which PHY interfaces are 2.5 MHz for 10 Mbit/s supported in the device RXD[3:0] RXD[3:0] RXD[1:0] RXD[1:0] Register info RXD[7:4] RXD[7:2] - ETH_CTRL RX_DV RX_CTL CRS_DV RX_CTL (REFCLK_SRC_SEL) RX_ER RX_ER RX_ER RX_ER RX_CLK RX_CLK RX_CLK REF_CLK REF_CLK(I) 50MHz ~ TX and RX clocks are supplied from external PHY TX and RX clock source can be supplied from either the internal reference clock or the external clock source ETH_CTRL register must be used to select the reference clock source from the internal reference clock or from HSIO 002-25166 *D 2021-02-12 Copyright © Infineon Technologies AG 2021.
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