Traveo™ II Ethernet Mac

Customer Training Workshop Traveo™ II Ethernet Mac

Q1 2021 Target Products

› Target product list for this training material Family Category Series Code Flash Memory Size Traveo™ II Automotive Body Controller High CYT3BB/4BB Up to 4160 KB Traveo II Automotive Body Controller High CYT4BF Up to 8384 KB Traveo II Automotive Cluster CYT3DL Up to 4160 KB Traveo II Automotive Cluster CYT4DN Up to 6336 KB

› Ethernet MAC is located in the peripheral blocks Hint Bar

ITCM DTCM CPU Subsystem ITCM16 KB DTCM16 KB SWJ/ETM/ITM/CTI Review TRM section 31 for CYT4BF 16 KB 16 KB MXS40-HT SWJ/ETM/ITM/CTI SWJ/MTB/CTI additional details

Cortex M7 143 Channel

P P 65 65 Channel

ASIL-B eCT FLASH 8 Channel CRYPTO

- -

350 MHz - DMA1 Arm Cortex-M7 SRAM0 SRAM1 SRAM2 DMA0 ROM 8384 KB Code Flash DMA0 AES, SHA, CRC, Arm 350 MHz 512 KB 256 KB 256 KB TRNG, RSA, 64 KB FPU D$ I$ + 256 KB Work Flash Cortex-M0+ (SP/DP) 16KB 16KB ECC System Resources FPU D$ I$ AHBP NVIC, MPU, AXI AHBS 100 MHz (SP/DP) 16 KB 16 KB 8 KB $ SRAM SRAM SRAM Power Initiator/MMIO ROM Controller AHBP NVIC, MPU, AXI AHBS FLASH Controller Controller Controller Controller MUL, NVIC, MPU Sleep Control POR BOD OVP LVD System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU) REF PWRSYS-HT

LDO PCLK Peripheral Interconnect (MMIO, PPU) Interface Serial SPI,Single Memory (Hyperbus, Clock

Clock Control SPI, SPI) Quad Octal Dual SPI, 10/100/1000 Ethernet + AVB+10/100/1000 Ethernet

2xILO WDT Prog. TIMER,

IMO ECO Analog SD/SDIO/eMMC

Event GeneratorEvent

I2C, I2C,

115x TCPWM 115x

I2S/TDM I2S/TDM In/Out

1x FLEXRAY

CAN

FlexRay FlexRay Interface

3x AUDIOSS

1x SMIF 10x CANFD10x FLL CSV ETH 2x

SAR SDHC

EVTGEN

10x SCB10x

SPI, SPI,

20x LIN 20x

1xSCB

EFUSE

LIN/UART

4xPLL CTR,

ADC InterfaceFD

IOSS GPIO IOSS

UART, (12-bit) UART,

Reset QD, PWM QD,

Reset Control

LIN XRES LIN x3 Test TestMode Entry Digital DFT SARMUX Analog DFT 96 ch

WCO RTC High-Speed I/O Matrix, Smart I/O, Boundary Scan 5x Smart I/O Power Modes Active/Sleep Up to 196x GPIO_STD, 4x GPIO_ENH, 40xHSIO LowPowerActive/Sleep DeepSleep I/O Subsystem Hibernate

› Ethernet MAC is located in the peripheral blocks Hint Bar

ITCM DTCM CPU Subsystem GFX Subsystem ITCM64 KB DTCM64 KB CYT4DN SWJ/ETM/ITM/CTI Review TRM section 31 for 64 KB 64 KB MXS40-HT SWJ/ETM/ITM/CTI SWJ/MTB/CTI

Cortex M7 Vector Gfx additional details

P P 76 ASIL-B 84

eCT FLASH 8 Channel CRYPTO

- -

320 MHz

DMA0 DMA1 Channel Arm Cortex-M7 SRAM0 SRAM1 SRAM2 Channel ROM DMA0 VRAM 6336 KB Code Flash AES, SHA, CRC, Arm 320 MHz 256 KB 256 KB 128 KB TRNG, RSA, 64 KB 4096 KB FPU D$ I$ + 128 KB Work Flash Cortex-M0+ (SP/DP) 16KB 16KB ECC FPU D$ I$ AHBP NVIC, MPU, AXI AHBS 100 MHz (SP/DP) 16 KB 16 KB 8 KB $ SRAM SRAM SRAM System Resources Initiator/MMIO ROM Controller VRAM Controller AHBP NVIC, MPU, AXI AHBS FLASH Controller Controller Controller Controller MUL, NVIC, MPU Power Sleep Control POR BOD OVP LVD System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU) GFX Interconnect (AXI) REF

PWRSYS-HT 2x RGB/LVDS 2x Output

LDO PCLK Peripheral Interconnect (MMIO, PPU) InterfaceSerial Memory Single(Hyperbus, SPI, 1x RGB/MIPI 1x Input

Clock Engine 2.5D Dual SPI, SPI, Dual QuadSPI) SPI, Octal

Clock Control 10/100

2xILO WDT Prog. TIMER,

IMO ECO Analog

/1000

Event GeneratorEvent

I2C, I2C,

FLL CSV 2

CAN

2xSMIF

x x PCM

1x ETH 1x

Audio DAC

4x CANFD

CXPI InterfaceCXPI CTR,

SAR EVTGEN

8xPLL LPECO SCB11x

2x CXPI

SPI, SPI,

x x TCPWM

1x SCB

EFUSE

LIN/UART

2x LIN

Ethernet + Ethernet AVB+

5x SG

x x Mixer x x TDM

ADC InterfaceFD

IOSS GPIO IOSS x x I2S

Reset

QD, PWM,SMC QD, UART, (12-bit) UART,

Reset Control -

XRES PWM

LIN Test LIN TestMode Entry x1 Digital DFT Analog DFT

SARMUX WCO 48 ch RTC

Power Modes High-Speed I/O Matrix, Smart I/O, Boundary Scan Active/Sleep 1x Smart I/O LowePowerActive/Sleep 52x GPIO_STD, 8x GPIO_ENH, 26x GPIO_SMC, 70x HSIO_STD, 22x HSIO_ENH, 4x HSIO_ENG_DIFF DeepSleep Hibernate I/O Subsystem

› Ethernet MAC1 module transmits and receives IEEE 802.3 frames by connectingHint Bar 2 with the PHY device Review TRM section 31.1 for additional details

Review the device-specific datasheet to confirm ECU which PHY interfaces are Traveo II supported in the device Ethernet (10 Mbit/s) Dedicated PHY Fast Ethernet (100 Mbit/s) Ethernet MAC Gigabit Ethernet (1000 Mbit/s) (10/100/1000 Mbit/s) MII3 or RMII4 or GMII5 or RGMII6 and MDIO7

Physical Layer MAC Layer

Network Interface Layer

1 MAC: Media Access Control 2 PHY: Physical layer 3 MII: Media Independent Interface 4 RMII: Reduced Media Independent Interface RMII is the standard for reducing the number of signals needed to connect the PHY to the MAC compared to MII 5 GMII: Gigabit Media Independent Interface 6 RGMII: Reduced Gigabit Media Independent Interface RGMII is the standard for reducing the number of signals needed to connect the PHY to the MAC compared to GMII 7 MDIO: Management Data Input/Output

› MII, RMII, GMII, and RGMII PHY interface Hint Bar

› MDIO interface for PHY management Review TRM section 31.1 › 10/100/1000 Mbps Ethernet MAC compatible with IEEE 802.3 for additional details Review the device-specific › Full-duplex datasheet to confirm which PHY interfaces are › Jumbo frame1 (Max 1536 bytes) supported in the device › IEEE 802.1Q: Virtual LAN (VLAN) › IEEE 802.3: Pause frame › IEEE 802.1BA: Audio video bridging systems › IEEE 802.1Qav: Forwarding and queuing enhancements for time- sensitive streams › IEEE 802.1AS: Timing and synchronization for time-sensitive applications in bridged LANs › IEEE 1588 – Precision time protocol

1 Jumbo frame is not standardized by IEEE

› MAC control Hint Bar

– PHY interface Review TRM section 31.2 for additional details

– MAC transmitter/receiver Refer to the Features List in the datasheet for – Time stamp unit additional details AXI master interface AHB slave interface Review the device-specific › TX/RX packet memory datasheet to confirm Ethernet MAC which PHY interfaces are supported in the device › CLK control AXI Interface AHB2APB AHB Interface

TX Packet Buff MAC Control (16KB) MMIO Time Stamp Unit Registers (TSU) RX Packet Buff (4KB) MAC Transmitter MAC Receiver clk_sys Clock clk_mem MII/RMII/GMII/RGMII PHY Interface Control clk_tsu and MDIO int_ref_clock

› Supports MII/RMII/GMII/RGMII PHY interface Hint Bar › Supports MDIO interface Review TRM section 31.3.14 for additional details

AXI master interface AHB slave interface Review the device-specific datasheet to confirm which PHY interfaces are Ethernet MAC supported in the device AXI Interface AHB2APB AHB Interface

› Supports the following interface types and transfer rates Hint Bar

Review TRM Transfer Rate section 31.3.14 for additional details Interface Type Review the device-specific 10 Mbps 100 Mbps 1000 Mbps datasheet to confirm which PHY interfaces are supported in the device MII ✓ ✓ - RMII ✓ ✓ - GMII - - ✓ RGMII ✓ ✓ ✓

› Supported signals: transmitter/receiver signals Hint Bar

Pin Name Function of signals MII RMII GMII RGMII Review TRM section 31.3.14 and for TXD[1:0] Transmit data [1:0] ✓ ✓ ✓ ✓ additional details TXD[3:2] Transmit data [3:2] ✓ - ✓ ✓ See the Package Pin List and Alternate Functions in TXD[7:4] Transmit data [7:4] - - ✓ - the datasheet for TX_CTL Transmit enable ✓ ✓ ✓ ✓ additional details TX_ER Transmit error ✓ - ✓ - Review the device-specific datasheet to confirm TX_CLK Transmit clock ✓ ✓ ✓ ✓ which PHY interfaces are supported in the device RXD[1:0] Receive data [1:0] ✓ ✓ ✓ ✓ RXD[3:2] Receive data [3:2] ✓ - ✓ ✓ RXD[7:4] Receive data [7:4] - - ✓ - RX_CTL Receive data valid ✓ ✓ ✓ ✓ RX_ER Receive error ✓ ✓ ✓ - RX_CLK Receive clock ✓ - ✓ ✓ REF_CLK Operation clock out - ✓ ✓ ✓ Operation clock in - ✓ ✓ ✓

MII Interface RMII Interface Hint Bar [PHY device] [Traveo II] [PHY device] [Traveo II]

TXD[3:0] TXD[3:0] TXD[1:0] TXD[1:0] Review TRM section 31.3.14 for TXD[7:4] TXD[7:2] additional details TX_EN TX_CTL TX_EN TX_CTL TX_ER TX_ER TX_ER Review the device-specific TX_CLK TX_CLK TX_CLK datasheet to confirm 25 MHz for 100 Mbit/s which PHY interfaces are 2.5 MHz for 10 Mbit/s supported in the device

RXD[3:0] RXD[3:0] RXD[1:0] RXD[1:0] Register info RXD[7:4] RXD[7:2] - ETH_CTRL RX_DV RX_CTL CRS_DV RX_CTL (REFCLK_SRC_SEL) RX_ER RX_ER RX_ER RX_ER RX_CLK RX_CLK RX_CLK

REF_CLK REF_CLK(I)

50MHz ~

TX and RX clocks are supplied from external PHY TX and RX clock source can be supplied from either the internal reference clock or the external clock source ETH_CTRL register must be used to select the reference clock source from the internal reference clock or from HSIO

GMII Interface RGMII Interface Hint Bar [PHY device] [Traveo II] [PHY device] [Traveo II]

TXD[7:0] TXD[7:0] TXD[3:0] TXD[3:0] Review TRM section 31.3.14 for TXD[7:4] additional details TX_EN TX_CTL TX_CTL TX_CTL TX_ER TX_ER TX_ER Review the device-specific datasheet to confirm GTX_CLK TX_CLK TXC TX_CLK 125 MHz 125 MHz which PHY interfaces are supported in the device

RXD[7:0] RXD[7:0] RXD[3:0] RXD[3:0] Register info RXD[7:4] - ETH_CTRL RX_DV RX_CTL RX_CTL RX_CTL (REFCLK_SRC_SEL) RX_ER RX_ER RX_ER RX_CLK RX_CLK RXC RX_CLK

REF_CLK(I) REF_CLK(I)

125 MHz ~ 125 MHz ~

TX clock source can be selected either from the TX clock source can be selected either from the internal internal clock source or from HSIO clock source or from HSIO ETH_CTRL register must be used to select the ETH_CTRL register must be used to select the reference reference clock source from the internal reference clock source from the internal reference clock or from clock or from HSIO HSIO

› Supported signals Hint Bar

Pin Name Direction Function of signals Review TRM section 31.3.12 for additional details MDIO I/O Management Data Input/Output MDC O Management Data Clock – MDIO is a single bi-directional tristate signal between Ethernet MAC and PHY – MDC is a clock for MDIO – MDC is generated by dividing CLK_GR4 – MDC should not toggle faster than 2.5 MHz (minimum period of 400 ns), as defined by the IEEE 802.3az › Use case – ETH_phy_management register is implemented as a shift register – Writing to this register starts a shift operation and outputs to the MDIO pin 2-bit 2-bit 5-bit 5-bit 2-bit 16-bit MDIO ST OP PHY Address REG Address TA DATA

MDC

› MAC Transmitter/Receiver and TX/RX Packet Buff Hint Bar

– Supports transfer of packets between Physical Layer and MAC Layer, and Review TRM stores data in TX/RX packet buffer sections 31.3.2 to 31.3.4 for additional details › Time Stamp Unit (TSU) – Generates a time stamp for the transmit data and checks the time stamp for the receive data AXI master interface AHB slave interface

Ethernet MAC AXI Interface AHB2APB AHB Interface

› Procedure (1) IP Datagrams are transferred to the TX packet memory via AXI1

(1) AXI master interface AHB slave interface

Ethernet MAC Internet AXI Interface AHB2APB AHB Interface Layer IP TCP Application (IP Datagram) Header Header Data TX Packet Buff MAC Control Network (16KB) MMIO Time Stamp Unit Interface Ethernet IP TCP Application Ethernet Registers Layer (MAC Frame) (TSU) Header Header Header Data Trailer RX Packet Buff (4KB) MAC Transmitter MAC Receiver clk_sys Clock clk_mem MII/RMII/GMII/RGMII PHY Interface Control clk_tsu and MDIO int_ref_clock

1 Support to DMA transfer. DMAC is implemented in the MAC Control

› Procedure (1) IP Datagrams are transferred to the TX packet memory via AXI1 (2) IP Datagram is transferred to the MAC Transceiver1

(1) AXI master interface AHB slave interface

Ethernet MAC Internet AXI Interface AHB2APB AHB Interface Layer IP TCP Application (IP Datagram) Header Header Data TX Packet Buff MAC Control Network (16KB) MMIO (2) Time Stamp Unit Interface Ethernet IP TCP Application Ethernet Registers Layer (MAC Frame) (TSU) Header Header Header Data Trailer RX Packet Buff (4KB) MAC Transmitter MAC Receiver clk_sys Clock clk_mem MII/RMII/GMII/RGMII PHY Interface Control clk_tsu and MDIO int_ref_clock

1 Support to DMA transfer. DMAC is implemented in the MAC Control.

› Procedure (1) IP Datagrams are transferred to the TX packet memory via AXI1 (2) IP Datagram is transferred to the MAC Transceiver1 (3) MAC frame is multiplexed and transmitted by the hardware

(1) AXI master interface AHB slave interface

Ethernet MAC Internet AXI Interface AHB2APB AHB Interface Layer IP TCP Application (IP Datagram) Header Header Data TX Packet Buff MAC Control Network (16KB) MMIO (2) Time Stamp Unit Interface Ethernet IP TCP Application Ethernet Registers Layer (MAC Frame) (TSU) Header Header Header Data Trailer RX Packet Buff (4KB) MAC Transmitter MAC Receiver clk_sys (3) Clock clk_mem MII/RMII/GMII/RGMII PHY Interface Control clk_tsu and MDIO int_ref_clock

1 Support to DMA transfer. DMAC is implemented in the MAC Control.

› Procedure (1) MAC frame is checked and demultiplexed by the hardware

AXI master interface AHB slave interface

Ethernet MAC Internet AXI Interface AHB2APB AHB Interface Layer IP TCP Application (IP Datagram) Header Header Data TX Packet Buff MAC Control Network (16KB) MMIO Time Stamp Unit Interface Ethernet IP TCP Application Ethernet Registers Layer (MAC Frame) (TSU) Header Header Header Data Trailer RX Packet Buff (4KB) MAC Transmitter MAC Receiver clk_sys (1) Clock clk_mem MII/RMII/GMII/RGMII PHY Interface Control clk_tsu and MDIO int_ref_clock

› Procedure (1) MAC frame is checked and demultiplexed by the hardware (2) IP Datagram is transferred to the RX packet memory1

AXI master interface AHB slave interface

Ethernet MAC Internet AXI Interface AHB2APB AHB Interface Layer IP TCP Application (IP Datagram) Header Header Data TX Packet Buff MAC Control Network (16KB) MMIO Time Stamp Unit Interface Ethernet IP TCP Application Ethernet Registers Layer (MAC Frame) (TSU) Header Header Header Data Trailer RX Packet Buff (4KB) MAC Transmitter MAC Receiver clk_sys (1) (2) Clock clk_mem MII/RMII/GMII/RGMII PHY Interface Control clk_tsu and MDIO int_ref_clock

1 Support to DMA transfer. DMAC is implemented in the MAC Control.

› Procedure (1) MAC frame is checked and demultiplexed by the hardware (2) IP Datagram is transferred to the RX packet memory1 (3) IP Datagram is transferred to the internal memory via the AXI bus1 (3) AXI master interface AHB slave interface

Ethernet MAC Internet AXI Interface AHB2APB AHB Interface Layer IP TCP Application (IP Datagram) Header Header Data TX Packet Buff MAC Control Network (16KB) MMIO Time Stamp Unit Interface Ethernet IP TCP Application Ethernet Registers Layer (MAC Frame) (TSU) Header Header Header Data Trailer RX Packet Buff (4KB) MAC Transmitter MAC Receiver clk_sys (1) (2) Clock clk_mem MII/RMII/GMII/RGMII PHY Interface Control clk_tsu and MDIO int_ref_clock

1 Support to DMA transfer. DMAC is implemented in the MAC Control.

› Frame format Hint Bar

– Basic Frame Review the Register TRM 7-octet 1-octet 6-octet 6-octet 2-octet 46 to 1500-octet 4-octet for additional details

S DESTINATION SOURCE LENG Preamble F TH/ MAC Client Data, Pad FCS D ADDRESS ADDRESS TYPE

Notes: SFD: Start of Frame Delimiter FCS: Flag check sequence

– Q-tagged Frame

7-octet 1-octet 6-octet 6-octet 4-octet 2-octet 42 to 1500-octet 4-octet S DESTINATION SOURCE Q Tag Preamble F MAC Client Data, Pad FCS D ADDRESS ADDRESS Prefix

MAC CLIENT LENGTH/TYPE

› The maximum length of the Traveo II jumbo frame payload Hint Bar

is 1536 bytes Review the Register TRM for additional details 7-octet 1-octet 6-octet 6-octet 4-octet 2-octet 42 to 1536-octet 4-octet Register Info S Destination Source Q Tag - ETH_jumbo_max_ Preamble F MAC Client Data, Pad FCS length D Address Address Prefix

MAC CLIENT LENGTH/TYPE Set to the following register. - ETH_jumbo_max_length register

› Provides a virtual LAN group in the network by VLAN tag Hint Bar › VLAN tag is inserted into the Q-tagged frame Review the Register TRM for additional details MAC CLIENT LENGTH/TYPE Register info - ETH_network_config 7-octet 1-octet 6-octet 6-octet 4-octet 2-octet 42 to 1500-octet 4-octet - ETH_stacked_vlan S Destination Source Q Tag - ETH_dma_config Preamble F MAC Client Data, Pad FCS Address Address Prefix - ETH_screening_type_2 D _register_0 to 15

2-octet 2-octet TCI 2 1 VLAN Tag TPID (0x8100) 3 4 user priority CFI VID 3-bit 1-bit 12-bit

Set to the following register. Set to the following register. Set to the Buffer descriptor. - ETH_stacked_vlan - ETH_screening_type_2 _register_0 to 15

1 TPID: Tag Protocol Identifier 2 TCI: Tag Control Information 3 CFI: Canonical Format Indicator 4 VID: VLAN identifier

› Pause frame is used to prevent self-buffer overflow Hint Bar

7-octet 1-octet 6-octet 6-octet 2-octet 46-octet 4-octet Review the Register TRM for additional details S MAC Client Data, Pad Preamble F Destination Address Source Address Type Op Pause FCS Padding Register info D code time - ETH_network_config - ETH_pause_time 01:80:C2:00:00:01 0x8808 0 to 65535 0x0001

Fix value Set to the following register. - ETH_pause_time

› Supports the timing and synchronization (IEEE 802.1AS) Hint Bar › Supports the TSU1 Review the Register TRM for additional details – Ethernet MAC has a TSU compatible to IEEE 1588 › Supports the FQTSS2 (IEEE 802.1Qav) – Ethernet MAC has registers to support FQTSS – FQTSS is controlled by software using registers and supports priority control of transmission data

1 TSU: Time Stamp Unit 2 FQTSS: Forwarding and Queuing Enhancements for Time-Sensitive Streams

› The following clocks are needed to execute the internal Hint Bar

operation of Ethernet MAC Review TRM section 31.3.15 for – clk_sys additional details – clk_mem – clk_tsu AXI master interface AHB slave interface

– int_ref_clock Ethernet MAC AXI Interface AHB2APB AHB Interface

› Usage of each clock is listed here Hint Bar

Review TRM section Clock Function 31.3.15 for additional details clk_sys To generate MDC clock and for AHB operation clk_sys is derived from CLK_PERI clk_tsu TSU clock for TSU timer clk_mem Fast clock for AXI operation int_ref_clock Internal reference clock supplied from PLL

Revision ECN Submission Description of Change Date ** 6399212 12/03/2018 Initial release *A 6678084 09/19/2019 Updated page 2, 3, 5, 6, 8, 11 to 20, 21, 24, 26, 27 Added page 4 *B 6950716 08/17/2020 Updated MII and RMII Interface description on page 11. *C 7051240 12/22/2021 Updated revision to 0C from 0B Added the new products: page 2 Changed to new block diagram: page 3, 4 Updated TX_CLK assignment: page 10 Updated clock name and description: page 7, 8, 14 to 20, 26, 27 Updated Hint Bar: page 5 to 14, 26, 27 *D 7082784 02/12/2021 Updated page 10 for typo