3D SONOS NAND October, 2020

Gawon Lee Dept. of Electronics Engineering Chungnam National University E-mail: [email protected] Main Research Field: Semiconductor Non Volatile Memory (SONOS Flash Memory) Simulation/Fabrication/Analysis Engineering Thin Film Transistor (poly-Si, ZnO-based TFT) Simulation/ Fabrication/Analysis Laboratory Si-based Solar Cell with Heterojunction with Thin Intrinsic layer (HIT Solar Cell) 1D/2D devices

Planar/3D Flash Memory based on Si material

Simulation

Flexible and Transparent Electronics including Display (based on ZnO material)

Process Development/Physical Analysis

(Gas, Infrared, UV..) Sensor with 1D or 2D material Introduction of Laboratory: Semiconductor Engineering Lab.

Clean Room Measurement Room

Fabrication: ALD, Sputter, Evaporator, Furnace, Photolithography Analysis: I-V, C-V, Charge Pumping Measurement, Noise Analysis, Low Temp Check. CONTENTS

01 Overview on Flash Memory INTRODUCTION

- Operating Mechanism 02 - Why NAND? NAND and OR Structure Planar Flash Memory - Limitations of Planar NAND Flash

3D Structure 03 - BiCS/p-BiCS - VNAND 3D Flash Memory

04 Challenges Current Status for Future Current Status Overview on Flash Memory

Comparison with Volatile (DRAM and SRAM) vs. Non-Volatile (Flash) Memory

Higher Cell density Lowest Cell density Highest Cell density Highest Operation Speed Data Access: String Structure not Random Access Overview on Flash Memory

HDD 시장 점유

Source from http://www.samsung.com (키옥시아) OperatingFlash Memory Mechanism of Flash Memory: FG Flash Memory Flash Memory: Operating Mechanism

Floating Gate (FG) Conventional MOSFET Flash Memory Transistor

VGS

IDS V DS Blocking Oxide

Tunneling Oxide e N+ N+ P-type

On-State

Off-State

Vth (threshold voltage, turn-on voltage) OperatingFlash Memory Mechanism of Flash Memory: FG Flash Memory

Flash Memory: Operating Mechanism

Erase Program

Vth1 Vth2 State “0” State “1”

Program Mode Erase Mode A large positive gate voltage (Program A large negative gate voltage (Erase voltage) voltage) applied to the control gate causes a applied to the control gate (or silicon substrate) tunneling current to flow through the oxide releases the electrons accumulated at the layer, injecting electrons into the floating gate. floating gate. (electron stored in floating gate) Operating Mechanism of Flash Memory: FG Flash Memory

NOR vs. NAND type Flash Memory

1 1 1 0 Operating Mechanism of Flash Memory: FG Flash Memory

NOR vs. NAND type Flash Memory

Image from http://eetimes.com Operating Mechanism of Flash Memory: FG Flash Memory NOR High Speed Random Access Channel Hot Carrier Injection Program/ FN Erase Slow Programming (Hot Carrier Injection) → Code Memory Application

NAND Serially Connected Cells (need I/O interface) FN Program/FN Erase Page Unit Read/Program Block Unit Erase Small On-Current (Slow Sensing) Low Cost/High Density → Data Memory Application Limitations of Planar Flash Memory Limitations of Planar Flash Memory Limitations of Planar Flash Memory

Gate Oxide Thickness - electrons stored in the floating gate can tunnel through Frenkel-Pool mechanism - For data retention characteristics, gate oxide thickness > 8nm

Percolation model for defect-assisted tunneling. (a) A single defect in a thin tunnel oxide may induce Frenkel–Poole tunneling. The red circle represents the characteristic length an electron may tunnel. (b) For a thick oxide a single defect is insufficient to cause tunneling. Even multiple defects cannot assist tunneling if they are not within reach of one another.

Referred from Chih-Yuan Lu et. al, “Future challenges of flash memory technology”, Microelectronic Engineering 86 (2009) 283-286 Limitations of Planar Flash Memory

Gate Coupling Ratio Limitations of Planar Flash Memory

Gate Coupling Ratio - GCR=C (control gate to floating gate) / C (total floating gate) capacitance) - For the effective gate control GCR > 0.6 - Wrap-around gate structure - at below 40nm node, GCR > 0.6 cannot be achieved Limitations of Planar Flash Memory

Interference

Reference: Hynix Seminar on “NAND Flash Technology”, 2012 Limitations of Planar Flash Memory

NAND Flash Scaling Issues

How much can we scale down the cell? Patterning limitation Dielectric Thickness due to current leak, breakdown Data Retention, Endurance

How many electrons in cell? Few electrons below 10nm Restricted MLC operation

Cell operation Operating voltages (Gate Coupling Ratio) Noise performance – cross talk Flash3D SONOS Memory Flash Memory Flash Memory ITRS Roadmap

Artificial Intelligence

Source : FOODICON, Psychology Today, Bankinfo security, Hellot.net 3DFlash SONOS MemoryMemory Flash Memory

Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Flash Memory (Charge Trapping Flash Memory, CT Flash Memory)

Advantages of SONOS Device

→ Better scaling capability → Lower programming voltage → High logic compatibility Tunneling oxide

Tunneling oxide 3D SONOS FlashFlash Memory Memory VNAND

Silicon-Oxide-Nitride-Oxide-Silicon (SONOS)

Charge Loss Path

Pitch (Half Pitch: Unit Cell Length)

Planar (2D) SONOS Vertical Channel (3D) SONOS 3D FlashSONOS3D Memory FlashNAND Memory Flash Memory

3D SONOS Flash Mem 3D NAND Flash Memory: BiCS (Bit Cost Scalable)

- Punch and Plug process

Reference: H. Tanaka et al., VLSI, 2007 Y. Fukuzumi et al., IEDM, December, 2007 BiCS NAND Flash Memory

Fabrication Process - Lower select gate transistor, memory string and upper select gate transistor are fabricated individually. - Gate material is P+ poly-Si. Holes for transistor channel or memory plug are punched through and LPCVD TEOS film or ONO films are deposited. - The bottom of dielectric films are removed by RIE and plugged by amorphous Si. - Arsenic is implanted and activated for drain and source of upper device. Edges of control gate are processed into stair-like structure by repeating of RIE and resist sliming. - For minimizing disturb, whole stack of control gate and lower select line are etched to have a slit. Upper select gate is cut into line pattern to work as row address selector. - Via hole and BL are processed on the array and peripheral circuit simultaneously

Reference: Y. Fukuzumi et al., IEDM, December, 2007 BiCS NAND Flash Memory

Reference: Y. Komori et al., IEDM, December, 2008 BiCS NAND Flash Memory

BiCS Improvement

Shared LSG plate changed to separate line and space LSG

Bit Line Separated USG

Reference: Y. Komori et al., IEDM, December, 2008 Pipe-shaped BiCS (P-BiCS) NAND

P-BiCS: pipe-like Nand string structure

One terminal connected to BL and the other to SL

Reference: T. Maeda et al., VLSI Circuits Symposium, June, 2009 P-BiCS NAND

Reference: M. Ishiduki et al., IEDM, December, 2009 P-BiCS NAND

Pipe Connection process

Reference: M. Ishiduki et al., IEDM, December, 2009 P-BiCS NAND Process Flow Fabrication Process

-The first step is the PC formation. -The next step is the deposition of the sacrificial films followed by memory-hole formation. - Multiple layers of memory films should be deposited. -The SG transistors are formed after the fabrication of the Nand strings. -After SG-hole formation the sacrificial films are removed. -The removal of the sacrificial film leaves a U-pipe that connects two vertical Nand cells strings. - Next the memory films are deposited

Reference: M. Ishiduki et al., IEDM, December, 2009 P-BiCS NAND Stare-like structure for word line

Reference: T. Maeda et al., VLSI Circuits Symposium, June, 2009 P-BiCS NAND

Gate first process

Dielectric

Polysilicon (CG)

Dielectric

Reference: M. Ishiduki et al., IEDM, December, 2009 Vertical Recess Array Transistor (VRAT) NAND

Vertical Recess Array Transistor (VRAT) 3D NAND flash memory

Schematic cross sectional view of VRAT

Reference: J. Kim et al., VLSI Technology Symposium, June, 2008 VRAT NAND

Vertical recess array transistor (VRAT) 3D NAND flash memory

Process sequence of VRAT

3a. An active region is formed on the Si mesa 3b. The oxide layers are selectively etched by wet process, which makes undercut space 3c. The polysilicon is deposited on the multi-staking mold, which becomes the channel material 3d. The undercut space is filled with gate oxide and electrode followed by etch-back process to isolate the gates from each other 3e. The gate electrodes are exposed on the same plane after planarization by CMP and N-type implantation is added with tilt angle to form the S/D 3f. Each string is isolated. 3g.The contacts of WLs and BLs are completed [Fig. 3g].

Reference: J. Kim et al., VLSI Technology Symposium, June, 2008 TCAT/VNAND Terabit Cell Array Transistor, TCAT 3D NAND Flash

Structural Change Oxide/Nitride multilayer stack Sacrificial nitride layer is removed by wet removal process Line type W/L cut TCAT

Terabit Cell Array Transistor, TCAT 3D NAND Flash

Advantages over BiCS The channel poly plug connected to Si substrate → Implementation of bulk erase operation without any major peripheral circuit changes. Smaller area overhead than BiCS flash

Metal gate structure Good erase speed, wider Vth margin, and better retention However, difficult to etch metal/oxide multilayer simultaneously

GIDL erase of BiCS flash Area overhead Limited erase voltage

Reference: J. Jang et al., VLSI Technology Symposium, June, 2009 4D NAND

SK hynix develops world’s first 4D NAND flash, 2018 SK hynix has developed the world’s first 4D NAND flash memory using both Charge Trap Flash and Peri Under Cell technologies, with a plan to start mass production this year, according to the chipmaker on Sunday.

SK hynix said it developed 96-layer 512-gigabit NAND flash, named CTF-based 4D NAND Flash to distinguish it from current 3D NAND flash technologies. (From Koearherald, 2018)

Source: http://news.hynix.com (2020) Xtacking (YMTC, China)

YMTC Introduces 128-Layer 1.33Tb QLC 3D NAND (source: http://www.ymtc.com)

Wuhan, China, April 13, 2020 - Yangtze Memory Technologies Co., Ltd (YMTC), today announced that its 128-layer 1.33Tb QLC 3D NAND flash memory chip, X2-6070, has passed sample verification on the SSD platform through co-working with multiple controller partners. As the first QLC based 128-layer 3D NAND, X2-6070 has achieved the highest bit density, highest I/O speed and highest capacity so far among all released flash memory parts in the industry. Accompanying this release, YMTC introduced a 128- layer 512Gb TLC (3 bit/cell) chip, X2-9060, to meet diversified application requirements.

Independent process

“As a new entrant in the flash memory industry, YMTC has reached to new heights by launching the 1.33 Tb QLC product,’’ said Grace Gong, YMTC Senior Vice President of Marketing and Sales. “We are able to achieve these results today because of the incredible synergy created through seamless collaboration with our global industry partners, as well as remarkable contributions from our employees. With the launch of XtackingTM 2.0, YMTC is now capable of building a new business ecosystem where our partners can play to their strengths and we can achieve mutually beneficial results.” Current Status: Roadmap of NAND Flash Memory Current Status: Challenges Current Status for Future Flash memory applications Current Status for Future Flash memory applications: USB Flash Drive

The internals of a 32 GB USB 3.0 flash drive.This drive has a write speed of 60 MB/s and a read speed of 120 MB/s, making it faster than the USB 2.0 standard. Current Status for Future Flash memory applications: SSD

"네버다이 SSD, SSD 가상화, V낸드 머신러닝" 삼성전자, 혁신 기술 적 용한 SSD 19종 출시 (2019.09 from http://www.itworld.co.kr)

플래시 메모리 (VNAND, 3D SONOS) Current Status Flash memory applications: SSD

“모두를 만족하는 SK 하이닉스의 첫 SSD” SK 하이닉스 골드 S31 SATA SSD 2019. 10 from http://www.itworld.co.kr

골드 S 31은 두께 7mm의 2.5인치 SATA III 6Gbps 드라이브로 표준 PC와 대다수 노트북에 맞는 폼팩터이다. 당연히 SK 하이닉스의 72계층 TLC NAND와 4세대 쿼츠(Quartz) 컨트롤러를 사용한다. SK 하이닉스는 탑재된 DRAM과 NAND 캐시 용량을 밝히지 않았지만…

현재 제품 모델은 250GB, 500GB, 1TB 세 가지이며, 가격은 아마존을 기준으로 각각 50달러, 70달러, 119달러이다. 모든 모델의 보증기간 은 5년이며, 제시한 내구성은 각각 200TBW, 30TBW, 500TBW이다. TBW가 좀 낮은 편이지만, 일반 사용자가 10년 동안 사용할 수 있는 것보 다 많은 용량이다. Current Status for Future

3D schematic diagram of TSV-integrated SSD

Reference: C. Sun et al., ASP-DAC, January, 2013