POWER Architecture

Taikhoom Attar Agenda

• RISC

• History

• POWER8

• Centaur

• CAPI

• More POWER8

• The present/future RISC

• The Power Architecture is RISC

• Reduced Instruction Set Computing

• Less complex instructions generally guaranteed to execute quickly

• Other examples: SPARC, ARM, MIPS Origins

• POWER traces its origins back to the experimental IBM 801

• Intended to be a phone switching system

• Development for a successor began in 1985 (America project) RISC System/6000 • Fruit of the America Project

• First POWER architecture-based system

• Introduced in 1990 in both and server varieties

• 32-bit 2-way superscalar CPU

• Three EU: Fixed-point, branch, floating-point

• No — improvements only possible w/increased clock speed https://www.flickr.com/photos/epc/456569763/in/photostream/ The next few years…

• RS/6000 CPU known as POWER1

• POWER2 came a few years later, adding an extra fixed point and floating point unit, some more cache, among others…

• Single-chip variety materialized between POWER1 and POWER2 — this became PowerPC, further developed in parallel

POWER8

• Current iteration of the architecture, introduced 2013

• Massively multithreaded, 8 threads/core

• Available in up to 12 cores

• Apparently performs 3x better than POWER7

• Another PPC chip handles frequency and voltage of cores POWER8 continued

• 64-bit 8-way superscalar

• “Chiplet" design

• Each chiplet contains a core, L2, and L3 cache.

• Revised version added support for NVLink

• Intended use by NVIDIA for CPU-GPU or GPU-GPU connections

• Otherwise essentially identical to original POWER8 Centaur

• Memory controlled by “Centaur” chips

• Serve as an abstraction layer for RAM

• Contains L4 Cache, up to 16MB per Centaur (of which there can be 4)

• Serve as a method of future-proofing

• Current Centaurs support DDR3, but DDR4 support can be added in a new Centaur CAPI

• Coherent Accelerator Processor Interface

• Expansion technology

• Sits on top of PCIe bus

• Therefore bandwidth limited by that bus (16GB/ s)

• Coherent Accelerator Processor Proxy — FU within CPU; paired with Power Service Layer • The CAPP and the PSL, paired, allow for low- latency communications over the PCIe bus

• Allows an accelerator, FPGA, etc connected to the bus to share memory space with the CPU directly and have high-speed access to it

• Low-latency a huge plus as well • OpenCAPI Consortium: AMD, Google, IBM, others

• New specification based on CAPI

• Available in POWER9

• Uses NVLink instead of PCIe; therefore PSL not needed, and doesn’t use PCI slots POWER9

• Next-generation, available later this year

• 12-stage

• 2 core variants - SMT4 and SMT8

• 2 device variants - Scale-out and scale-up

• Adds support for PCIe gen4

• One variety has integrated DDR4, other uses Centaur

• DoE, Oak Ridge Lab, Lawrence Livermore have contracted to build Summit and Sierra: supercomputers based on POWER9 + Volta Conclusion

• POWER series CPUs designed for server and high-end workstation loads

• Centaur memory abstraction layer allows for future-proofing a CPU design for compatibility with future RAM standards

• CAPI is an efficient protocol for low-latency interfacing with off- chip accelerators

• POWER still cannot compete at the consumer level

• PowerPC otherwise still used in some embedded applications; NXP produces some specifically for automobile applications References

• http://www.anandtech.com/show/10435/assessing-ibms-power8-part-1/7

• https://www.itjungle.com/2014/02/17/tfh021714-story01/

• http://www.idgconnect.com/abstract/3292/ibm-watson-smarter-power8-chip

• https://www.ibm.com/developerworks/community/wikis/form/anonymous/api/wiki/61ad9cf2- c6a3-4d2c-b779-61ff0266d32a/page/f1abe75a-a2b2-43dd-9d75-7dae28f5bc5f/attachment/ 0b9be9c6-1d2b-44dc-9630-384f47734c94/media/ 2014-01%20Intro%20to%20POWER8%20Process

• https://www-304.ibm.com/webapp/set2/sas/f/capi/home.html

• http://www-03.ibm.com/ibm/history/documents/pdf/rs6000.pdf

• https://upload.wikimedia.org/wikipedia/commons/d/d3/Power-cpu.jpg

• http://www.anandtech.com/show/8727/nvidia-ibm-supercomputers

• http://www.pcworld.com/article/3110620/servers/ibms-blazing--chip-is-coming-and- heres-what-you-need-to-know.html