From Technologies to Markets
2.5D / 3D TSV & Wafer Level Stacking Technology & market updates 2019
Sample
©2019 TABLE OF CONTENT Part 1/3
• Report scope & objectives P5 2. High end market segment P72 • Glossary P6 • Trends P74 • Artificial Intelligence • Authors P8 • Data center • Super computer • Companies cited in this report P9 • Cryptocurrency mining • Comparison with 2017 report version P10 • Gaming • AR/MR/VR • The three pages report summary P13 • Forecasts P95 Stacked memories wafer, units production 3D stacking – packaging market repartition: P16 • • • Stacked memories packaging revenues • Per 3D stacking technologiy • 2.5D interposer wafer, units production • Per segment • 2.5D interposer packaging revenues • Per market • 3D SoC wafer production & packaging revenue • Technologies & roadmaps P109 • Executive summary P21 • TSV 1. Introduction P58 • 3D stacked memories • 3D SoC Hints for reading • • 3D sequential integration • Updates from the last report • Hardware examples, players & supply chain P125 • Terminology • Hardware for HPC & Networking • From global market to advanced stacking technologies • GPU, FPGA supply chain • TSV based product players • Conclusions P150
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 2 TABLE OF CONTENT Part 2/3
3. Mid/Low End market segment P152 • CIS P153 • MEMS & sensors P187 • Trends • Trends • CIS market drivers • Market evolution & packaging trends • CIS packaging evolution • Forecasts • Forecasts • MEMS & sensors with TSV wafer • CIS market repartition per technology & units production • Global CIS wafer production • TSV revenues for MEMS & Sensors • Stacked CIS wafer, unit production • Hardware examples, players & supply chain • Stacked CIS packaging revenue • MEMS & Sensors with TSV examples • Technologies & roadmaps • Supply chain for certain MEMS • CIS stacking technologies:TSV & hybrid bonding & sensors applications and players • CIS roadmap • Conclusions • Hardware examples, players & supply chain • LED P212 BSI Stacked TSV • • TSV in LED • BSI Stacked Hybrid • TSV in LED wafer & revenue forecasts • BSI Multi-stack TSV • Conclusion
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 3 TABLE OF CONTENT Part 3/3
4. Potential future applications for 3D stacking technologies P216 • 3D NAND • Stacked memories, 3D SoC & displays 4. Appendix P219 • Stacking technologies vs 2.5D TSV interposer • Details of each technology 5. AboutYole Développement P245
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 4 REPORT SCOPE & OBJECTIVES
• This report is an update of the previous 2017 release “3D TSV and 2.5D business update: Market and Technology trends 2017” • The scope of this report is to present the actual trends and their impact on the packaging need and especially the 2.5D/3D stacking technologies. Mega trends are pushing the packaging market into more and more stacking technologies in order to answer their stringent requirements (more performance, lower consumption & footprint). Already established stacking technologies like TSV will continue to flourish, but will have extended challengers as OSAT’s and other players are also innovating and proposing alternative technologies & solutions for devices stacking • This report objectives are to: • Show the impact of the semiconductor market mutation on packaging technologies • Outline three stacking technologies, through silicon via (TSV), 3D system on chip & hybrid bonding • Provide an overview of the markets requiring stacking technologies • Update market data & forecasts for stacking technologies • Describe the hardware & key applications that are/will use stacking technologies • Identify the main players & supply chain for stacking technologies • Evoke novice technologies that may challenge some of the actual stacking technologies • Predict future applications where stacking technologies may be needed
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 5 ABOUT THE AUTHOR Biographie & contact
Mario Ibrahim
As a Technology & Market Analyst, advanced packaging, Mario Ibrahim is a member of the Semiconductor & Software division at Yole Développement (Yole). Mario is engaged in the development of technology & market reports as well as the production of custom consulting studies. He is also deeply involved in test activities business development within the division.
Prior to Yole, Mario was engaged in test activities development on LEDs at Aledia. He was also in charge of several R&D advanced packaging programs. During his five-year stay, he developed strong technical & managerial expertise in different semiconductor fields.
Mario holds an Electronics Engineering Degree from Polytech’ Grenoble (France). He apprenticed for three years in the Imaging division of STMicroelectronics Grenoble, where he contributed to the test benches park automation within the test & validation team.
Contact: [email protected]
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 6 COMPANIES CITED IN THIS REPORT
Alchip, Aledia, Alibaba, Amazon, AMD, Amkor, AMS, ANPEC, Apple, ASE, ASUS, Atos, Audi, Avago, Baidu, Bosch, Bitmain, BitFury, Broadcom Canaan, Carsem, Cisco, Cray DARPA EBANG, EMmicroelectronic, EPworks Facebook, Faraday, Fingerprints, Foxconn, Fraunhofer, Fujitsu Gigabyte, Global Foundries, Google, GUC HalongMining, HLMC, HP, Huatian, Huawei Ibiden, IBM, Icsens, IMEC, Inari technology, Infineon, Innosilicon, Intel, InvenSense JCET STATS ChipPAC, Juniper Lenovo, Leti, Lfoundry, LGinnotek mCube, Melexis, Memsic, Mercedes-Benz, Micralyne, Micron, Microsoft NEC, Nokia, Nvidia, NXP Omnivision, ON Semiconductor, OpenSilicon, Osram PTI Samsung, SensL, Shinko, SK hynix, SMIC, Sony, SPIL, STMicroelectronics Tencent, TF, Toshiba, TPK, TSMC UMC, Unimicron Xfab, Xilinx, Xintek, XMC, Xperi YMTC
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 7 TSV TECHNOLOGY WAFER START & REVENUES Global TSV market
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 8 ADVANCED PACKAGING TECHNOLOGIES REVENUES REPARTITION Repartition per markets : HPC & Networking / Consumer / Automotive / Others
The numbers are based on each technology’s revenues (M$), meaning that 30% of margin is taken into consideration
• HPC & networking markets are going to grow fast in order to follow the AI & big data trends. This market added to consumer market will represent almost 90% of the advanced packaging (stacking) market • Stacking technologies will be needed for autonomous vehicles where higher computing performance will be required (edge computing), but attention to automotive stringent regulations in term of reliability • Medical market is a small one for TSV’s but where the performance and form factor parameters are becoming more and more important
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 9 WHAT’S NEW SINCE THE LAST REPORT (JUNE 2017)
• Updating the hardware list using TSV & other 3D stacking technologies with focus on GPUs for High Performance Computing (HPC) in addition to MEMS & Sensors for mid / low end market segment • Updating the 3D integration markets by adding cryptocurrency as a new market • Updating the 3D stacked memory market by omitting HMC & MCDRAM memories from it. Micron stopped any R&D program related to HMC, they will continue to produce low volumes for some of their clients and they are switching to HBM instead • Updating the 3D integration technologies and adding technologies like hybrid bonding, Foveros, RDL interposer as a new stacking solutions. • Updating the CIS market and segmenting it into 3 different stacked CIS technologies (using TSV / Hybrid and combo TSV +Hybrid). More focus on this market asYole is foreseeing important usage of stacking technologies in it • Updating the 2017 forecasts with numbers based on the actual & future market analysis & trends • Updating the players & ecosystem for stacking technologies, showing that it’s in place and ready to fulfill clients demands • Updating the cost structure calculation used for the forecasts: • 2017 report: the cost of packaging was including for example the DRAM wafer cost + TSV cost + bumping cost +yield loss cost • 2019 report: the cost of packaging is only and for example the TSV cost + bumping cost + yield loss cost. Not taking into consideration the device wafer cost as we want to focus on the packaging costs only • New forecasts on Intel’s Foveros technology & updating the 3D SoC forecasts • 3D SoC will hit the market by 2019 produced by TSMC and with HiSilicon as a first potential client for their datacenter activities • EMIB from Intel as 3D stacking alternative to 2.5D TSV interposer, with products already launched • DRAM is still and will further be a big playing ground for 3D stacking technologies. Samsung is prompting pre-emptive $27.7 billion in a 2nd plant in Pyeongtaek to be able to answer growing DRAM & NAND demand. On the other hand, Micron will also invest $3 billion by 2023 to increase memory production at its Manassas plant • Chinese government is massively backing their memory startups. YMTC (Tsinghua Unigroup) received $24 billion to implement a new 12” 3D NAND production line in the new plant in Chengdu. Tsinghua Unigroup are also investing $30 billion in a plant in Nanjing to manufacture 3D NAND & DRAM • TSMC CoWoS and advanced packaging production capacity extension up to 200K wafers/month. Wafer on Wafer (3D SoC with hybrid bonding) new platform from TSMC for HPC and data center markets
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 10 WHY 3D INTEGRATION IS BECOMING MORE AND MORE IMPORTANT Moore’s law slowing down Only 4 players with 14/12nm Fab (2017) Only 2-3 players still in the 7nm node race
7nm Fab
Delay in Intel’s 10nm node, so obviously they are late regarding TSMC & Samsung
Moore’s law pace is slowing down, if not already dead as mentioned by Forbes & Nvidia. It’s reaching some limitations as developing lower technology nodes is doable technically but not anymore cost efficient
In this report, we will be using the “slow down” term when describing Moore’s law status
To deal with this slow down, other alternatives are currently used & will be further developed: • Advanced packaging technologies development. 2.5D technology was first used in high performance applications. Scaling the Z axis is taking more and more importance in what is called 3D stacking especially for HPC, but not only • Specialized devices. Meaning 1 device = 1 function. Example of GPU VS Neural engine, that allows reduced power consumption & faster computing speed • Other advanced packaging technologies development (SLIT, FOCoS, SWIFT, EMIB, ...)
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 11 MEGA TRENDS Opportunity for various stacking advanced packaging
Sensors/ Analog / Opto- CPU /GPU APU MCUs ASICs FPGAs Memory Actuators/CIS Discretes electronics AI/ML FC, FO FC, FC, 2.5D/3D, FC,WB,FO, Smart automotive FO FC, FO,ED WB,QFN, FC,FO,WB, QFN, QFN, ED, /Electrification/ ADAS FC, 2.5D/3D, WLCSP SiP FO, SiP WLCSP, SiP, 3D AR/VR FC, 2.5D/3D, SiP, 2.5D/3D, HPC FO FC, WB FC, FC, 3D, FC,FO,WB, QFN, IoT WB,QFN, WB,QFN, WLCSP, SiP, 3D WLCSP WLCSP FC,WB,FO, FC, 2.5D/3D, QFN, ED, 5G FO, SiP FC, FO,ED SiP SiP, 2.5D/3D, FC,FO,WB, QFN, FC, WB Mobile 3D WLCSP, SiP, 3D FC,WB,FO, FC, 2.5D/3D, FC, 2.5D/3D, Blockchain / Cryptocurrency QFN, ED, FO FO SiP Where 2.5D/3D stacking technologies are used
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 12 ADVANCED PACKAGING PLATFORMS Focus on 3D stacking packaging platforms in this report
No Organic Leadframe Ceramic Embedded substrate substrates substrates substrates Die
Fan-Out WLCSP Wirebond Flip-Chip Wire Bond Flip Chip Wirebond Flip-Chip
FC QFN BGA CSP LGA BGA CSP LGA QFN/QFP Hi Rel HTCC (MIS)
COB FC BGA SOIC LTCC
FO on BOC TSOP Substrate
WB CSP 2.5/2.1D LCC
3D* DIP In this report
*Hybrid bonding is included in 3D platform 2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 13 2.5D & 3D INTEGRATION MARKET SEGMENTATION The market is divided into High End & Mid/Low segments
2.5D & 3D integration
Segments High End Mid / Low segment End segment
Market Gaming, HPC Networking Sensing Lighting VR/AR/MR
Applications Data mining Artificial Super Data centers, Switch / MEMS & (crypto & CIS LED Intelligence computers hyper scale Router sensors other data)
High End segment is defined as the market where an application is less Mid/Low End segment is defined by a sensitive to the cost, but requires reduced footprint in addition to high good balance between cost sensitivity & performances & reliability performances
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 14 2.5D & 3D STACKING TECHNOLOGIES With / Without TSV. Foundries VS OSATs battle TSV + TSV Hybrid TSV Bonding
3D Stacked memory 3D SoC Without TSV With Or
With TSV Embedded in substrate Without TSV Hybrid Bonding
i-THOP FC-EIC EMIB TGV
G-ALCS
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 15 2.5D INTEGRATION WITH TSV TECHNOLOGY FOR HIGH END SEGMENT Heterogeneous integration on Si interposer
• The TSV is used as interconnection between the 2 Si facets in the so called Si interposer. It is a thinned silicon wafer with TSV’s that enable heterogeneous device integration on top of it in what is described as 2.5D integration. • This 2.5D Si interposer is the technology created just before the 3D integration (used for example in stacked memories). It was created as an intermediate technology before accessing the 3D integration and still used in many applications that requires: • Higher performances and lower power consumption due to shorter connections • In the example below, the Si interposer is used as an interconnection between a X-PU (GPU for example) and a 3D stacked memory (with TSV’s inside, HBM for example)
TSV
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 16 3D INTEGRATION WITH TSV TECHNOLOGY FOR HIGH END SEGMENT 3D Stacked memories with TSV technologies (3DS & HBM)
• 2 types of stacked memories technologies using TSV are on the market: • 3DS: this type of memory is using DDR4 DRAM stacked chips and operate as stand-alone memories for HPC & data centers markets • HBM: this type of memory is often used beside other hardware like GPU, CPU, FPGA on top of a 2.5D interposer • The 3DS memories are TSV based devices, where several DDR4 DRAMs are interconnected together using TSV technology. It can have a total capacity of 64 and 128GB. Samsung announced its availability in 256GB configuration back in October 2018 • 2 major players share the 3DS market, Samsung as a leader, SK Hynix as runner up with micron completing the podium but still far away from the 2 leaders in term of volume production • The HBM memories are also TSV based devices, where 2/4 & 8 DRAMs are interconnected together via TSV. We can see 1/2/4 HBM devices around a processor in a system dedicated for HPC. Samsung is the leader in this market with SK Hynix in second position. Micron will switch to this technology instead of their HMC technology that they are letting down • In term of market, the 3DS today is around 42% of total high performance stacked memories (3DS & HBM). Due to the fact of data collection exploded in the last years and the entry of artificial intelligence onto our daily life, the need of 3DS will increase in the upcoming years reaching 51% of the total high performance stacked memories market by 2020
Samsung Samsung stacked 8 stack DRAM high (3DS) HBM2
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 17 3D SOC 2 or 3 potential approaches to reach 3D SoC
Approach 1 (IMEC)
Approach 2 (IMEC)
Approach 3 (other possible approach?)
1 2 3?
Potential 3rd approach:
Hybrid or other bonding + Wafer 1 Dielectric bonding + complete Si removal + Si thinning + TSV last Hybrid bonding + Si thinning bumping (No TSV) + bumping + TSV middle + bumping
RDL may still be needed before bumping Source IMEC (except approach 3) 2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 18 3D SOC FORECAST 12’’ SoC WSPY production
• TSMC is believed to be the first to get a product on the market, by end of 2018, start of 2019 (Die to wafer, memory on logic). They are able to ramp up the production very quickly if a client will manifest an interest in this technology • TSMC WoW technology will be based on SoC wafer stacking using hybrid bonding and intended for datacenter usage. HiSilicon (Huawei) can be their first client,AMD is also a potential client
• Global foundries will enter the market by 2021 with as first phase memory on logic wafer to wafer stacking using hybrid bonding with pitches between 1 & 2µm. They will produce both wafers & stack them in-house, which is of an interest for the yield
• Hybrid bonding will, most probably, be the bonding technology used for 3D SoC stacking (wafer to wafer) • 3D SoC wafer should cost 3 to 4 times less than TSV interposer wafer • 3D SoC can be memory on logic or logic on logic (attention heat dissipation issues for the latter one). In the case of memory on logic which is the most probable application for 3D SoC, memory manufacturers & logic circuits ones should talk together to limit the design differences & yield losses (the manufacturers having capabilities to produce both wafers will have a big advantage)
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 19 HIGH END HARDWARE USING STACKING TECHNOLOGIES, PRODUCTS LAUNCH
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 20 HIGH END MARKET SEGMENT EXAMPLES, PLAYERS & SUPPLY CHAIN
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 21 TSV IN HIGH END SEGMENT FORECAST TSV revenues & growth in High End segment
• This graph is based on TSV revenues in High end segment: • 3D stacked memory (HBM & 3DS) • 2.5D interposer (active & passive) • 2.3B$ TSV revenues by 2023 with an important growth of 57% between 2017-2023 in high end segment • 3D stacked memories are and will still be the best friend hardware applications for TSV technology • We insist, it’s the TSV revenues and growth for High end segment only. If we plot the growth of TSV for all the combined market segments, the growth is around 25%
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 22 2.5D “PASSIVE” INTERPOSER A vision on its future
• TSV interposer is an expensive and complex technology in term of process steps
• All the players acting in the field of 2.5D stacking are working on replacing the TSV interposer by other technologies. The goal is to reduce the prices, enabling the access of 2.5D to mid/low end segments, but also simply to reduce the total module cost
• Two scenarios are possible for TSV: • Scenario 1: On the previous 2 slides, we shown that the demand for TSV interposer will continue to grow till 2020 and starting from 2021 the growth will be slower. This is the first potential scenario where we believe that one of the TSV less technologies will hit the market by 2020/2021 and will start replacing the TSV interposer for 2.5D gradually
• Scenario 2: Delays in the development and commercialization of TSV less technology(ies). Meanwhile, the demand for TSV interposer continue to grow to feed the HPC markets. In this case, the TSV interposer will continue to dominate the 2.5D market and players like TSMC & UMC will be able to increase their production volumes to meet with the demand
• TSV interposer still have some golden years in front, both scenarios can happen even if scenario 1 is more likely to occur after 2020 & scenario 2 till 2020
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 23 CIS WAFER LEVEL PACKAGING EVOLUTION From FSI to BSI multi-stack TSV sensors
4 stacks high CIS & Pixel to pixel high density 2017 interconnection 2016 CIS under development. 2016
Used in Sony XZs: 3 wafers Used in Galaxy interconnected Used in Iphone S7: via TSV I7+: 2 wafers 2 wafers interconnected interconnected via Hybrid via TSV Bonding
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 24 CIS ROADMAP Stacking technologies enabled new CIS technologies
• Technology shift into stacked CIS driven by the willingness to go for more performances & higher image quality in parallel to reducing the footprint • Stacking technologies enabled Rolling Shutter (RS) pixel size reduction. This will also be applied to Global Shutter pixel in the future Technology complexity
FSI RS pixel Lenovo 2Pro GS pixel ToF pixel FSI SOI Apple iX BSI
BSI Stacked TSV Samsung S6 Apple i7 BSI Stacked Hybrid Samsung S7 Apple i8 BSI Multi-stacked TSV Event-based Sony XZ pixel ? 2000 2005 2010 2015 2020 2025 Time
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 25 CIS STACKED TECHNOLOGIES FURTHER DETAILS [1/2] TSV and hybrid stacked BSI processes
• BSI stacked TSV: • Oxyde /oxide permanent bonding • Via Last TSV process + RDL
• BSI stacked Hybrid: • Copper pads on both wafers (upper & lower ones) • Oxide deposition & planarization (very low surface roughness is required ~1nm) • Plasma activation + alignment (able to go under 1µm of pitch alignment using a stepper) + Room temperature bonding followed by an annealing cycle
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 26 TSV VS HYBRID BONDING FOR CIS Which technology is the most suited?
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 27 STACKED CIS PACKAGING MARKET Packaging cost & revenues for stacked CIS (M$)
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 28 KEY PLAYERS FOR 3D STACKED CIS PRODUCTS Still a reduced comity with few players
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 29 PLAYERS LICENSING XPERI’S HYBRID BONDING TECHNOLOGY From CIS to memory, more and more players are using/evaluating hybrid bonding
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 30 THE DIFFERENT MEMS, SENSORS, AND ACTUATORS, AND WHERE THEY CAN COMBINE
SENSORS ACTUATORS
Movement Environment Optical sensors Optical MEMS Microfluidics RF Micro structures Focus - sonic Filter Switch µspeakers fingerprint fingerprint Pressure Ultra sonic Ultra sonic Probes Biochips Watches Micro Micro tips Oscillator Gyroscopes Vision FTIR SiPM Ink Ink heads jet components Auto Micromirrors Drug Drug delivery Accelerometers Magnetometers Sound Sound ultra and Gas Fingerprint 3D sensing 3D ALS, RGB ALS, Opticalbenches Particles Temperature Humidity Hyperspectral Micro Micro bolometers PIR & & PIR thermopiles IMUs (6 to 9 DOF)
“closed” package “open” package Possible MEMSPixels Audio 6 to 9+ DOF environmental combos Optical combos integration with combos opto combos Debiotech micro Avago-Broadcom pump FBAR Filter
Possible integration with environment sensorfingerprint Qualcomm combos Spiromax Patek Philippe - based speaker based Texas Instruments DLP SiTime oscillator FLIR Lepton One Apple dot projector
InvenSense ST pressure sensor MPU9250 Bosch BME680 poLight AF
Infineon microphone
Application where TSV is used
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 31 TRENDS IN MEMS PACKAGING [2/2] Packaging trends by market
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 32 INTEREST OF WAFER LEVEL PACKAGING + TSV ON ACCELEROMETERS? WLCSP & TSV = smaller package dimensions
65% surface reduction due to the use of (WLCSP + TSV) VS (LGA + TSV)
25% thickness reduction due to the use of (WLCSP + TSV) VS (LGA + TSV)
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 33 TSV FORECASTS FOR MEMS & SENSORS TSV revenues for MEMS & Sensors
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 34 MEMS & SENSOR (EXCEPT CIS) GLOBAL SUPPLY CHAIN THAT USE TSV IN THEIR PRODUCTS Non exhaustive list
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 35 RELATED REPORTS
2.5D/3D TSV & Wafer Level Integration Technology & Market updates 2019 | Sample | www.yole.fr | ©2019 36 2.5D / 3D TSV & WAFER-LEVEL STACKING: TECHNOLOGY & MARKET UPDATES 2019 Market & Technology report - January 2019 2.5D heterogeneous and 3D wafer-level stacking are reshaping the packaging landscape. STACKING: ONE ALTERNATIVE FOR HIGH INTEGRATION BESIDE WHAT’S NEW MOORE’S LAW • Two main market segments: - Highigh-end segment: high- The slowdown of Moore’s law opened the path to Hardware like High Bandwidth Memory (HBM) and performance computing, new inventions for answering actual mega-trends’ CIS comprise the majority of TSV’s revenue. The networking, gaming, and AR/VR/ stringent specifications. In the packaging field, 2.5D overall stacking technologies market will exceed MR and 3D stacking technologies were preferred by many $5.5B in 2023 with a CAGR of 27%. As for today, - Mid/low-end segment: CMOS semiconductor players, and through silicon via (TSV) the consumer market is the biggest contributor, Image Sensors (CIS), MEMS, was the initial stacking technology. After several years with over 65% market share. But this, paradoxically, and LED of development and a focus on MEMS, it finally entered doesn’t mean that consumer is the driver for these • Semiconductor market mutation many applications. Today, 2.5D and 3D stacking technologies. In reality, HPC is the real driver for and its impact on stacking technologies are the only solution that meet the stacking technologies and will exhibit the fastest technologies required performance of applications like AI and data growth up to 2023, with market share doubling from • Through silicon via's (TSV) center as for today. Stacking technologies are used in 20% in 2018 to 40% in 2023. In terms of packaging extensive usage in HPC and a variety of hardware, including 3D stacked memory, revenue, this equates to a more than 6x increase networking hardware Graphics Processing Unit (GPU), Field-Programmable from 2018’s revenue. Consequently, the consumer • 3D System on Chip (SoC) Gate Array (FPGA), and CMOS Image Sensor (CIS), market’s share will decrease. Other markets like technology to hit the market by 2019 are intended for the high/mid and low-end market automotive, medical, and industrial will maintain • Hybrid bonding/stacking segments. their current market share. technology: markets, applications, forecasts, and players Stacking technologies: revenue breakdown per market from 2018 to 2023 • Stacking technologies forecast for the CIS market HPC & networking 2023 • Technologies that are challenging Consumer 5 9M Automotive 2.5D TSV interposer Others industrial and medical 252M CAGR 25 KEY FEATURES 2018 • Markets and applications requiring 1 58M 2 22M 3D stacking technologies CAGR 18 2 32 M • High-end market segment: 81M 1 1 M CAGR stacking technologies (TSV, 2.5D CAGR +27% interposer, and 3D SoC), supply 350M 52M chain and forecasts for HPC, CAGR 25 networking, gaming, and AR/ 150M VR/MR. Breakdown by product (stacked memory) and technology *CAGR: Compound Annual Growth Rate (2.5D and 3D SoC) (Yole Développement, January 2019) • M id/low-end segment: FROM TSV TO WAFER-LEVEL STACKING, PACKAGING TECHNOLOGIES ARE technologies (TSV and hybrid bonding), supply chain, and FLOURISHING forecasts for CIS, MEMS, Since the stacking battle is mostly between TSV- bonding and TSV interconnections (potentially). sensors, and LED. Breakdown by based and TSV-less technologies, these are the The Foveros example shows that although TSV technology for CIS and LED, and two categories Yole Développement considers in is being challenged by non-TSV technologies, by application for MEMS & sensors this report. companies still have faith in it. • The future of stacking technologies For today’s high-end market segment, the most We cannot neglect the emergence of TSV-less popular 2.5D and 3D integration technologies on the technologies in the market. These innovations market are based on TSV for 3D stacked memory, can be placed into two groups: “with substrate” and TSV interposer for heterogeneous stacking. and “embedded in substrate”. Embedded Multidie Chip-on-Wafer-on-Substrate (CoWos) technology Interconnect Bridge (EMIB) technology, already is already widely used for HPC applications, and commercialized, is part of the embedded-in- new TSV technologies will hit the market in 2019, substrate group, where the Si bridge is deep seating i.e. Foveros from Intel, which is based on “active” in the substrate. Other substrate technologies are TSV interposer and 3D SoC technology, with hybrid being developed but are still not on the market, i.e. 2.5D / 3D TSV & WAFER-LEVEL STACKING: TECHNOLOGY & MARKET UPDATES 2019
Integrated Thin Film High Density Organic Package (FOCoS) was developed and commercialized in 2016, (I-THOP) and Flip Chip - Embedded Interposer but seems to be lacking orders. Carrier (FC-EIC). Hybrid bonding can bridge the two main categories With-substrate technologies are also used as (with TSV/without TSV). This technology’s alternatives to TSV, for example InFO on substrate, particularity is that it can be simultaneously TSV which is widely used in Apple’s processors. Also, challenger and teammate. Since 2016 it has been redistribution layer (RDL) interposer technology is commonly used in smartphones’ CIS, and in the near currently being developed and will hit the market by future it will integrate the high-end market segment 2020. Last but not least, Fan Out Chip on Substrate for memory and 2.5D as an interconnection solution.
TSV-less stacking technologies - 2018 overview