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April 1st, 2010 Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry.
Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. 3. 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Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. 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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority- owned subsidiaries. (Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics. 3D GRAPHICS ACCELERATOR µPD62011
The µPD62011 is a 3D graphics accelerator LSI designed for personal computers of the PowerVR 3D graphics processor family. The µPD62011 realizes high performance system by adding functions such as bi-linear texture and 66-MHz PCI bus support to the µPD62010 and incorporating a circuit that supports geometry operations performed in the CPU.
FEATURES
• Pin-compatible/software-compatible with the µPD62010 • Interface conforming with PCI bus 2.1 (supports 66 MHz) • On-chip hidden surface removal (Z buffer unnecessary, per pixel, 32-bit depth precision) • Automatic shadow generation by hardware • Per-pixel fogging • 66-MHz operation • On-chip geometry processing support circuit • Texture mapping • Perspective correct texture mapping • MIP mapping • Bi-linear texture • 16-/8- bit texture • Translucent texture • Texture memory: 1 to 4 Mbytes • Shading • Smooth shading • Flat shading/Highlighting • Output Image • RGB/BGR 565 Packed, RGB/BGR 555 Packed • RGB/BGR 888 Packed/Unpacked • Little/Big endian pixel format • Maximum 1024 × 1024 resolution • Supported API • Dedicated API (PowerSGLTM) • Microsoft’s Direct3DTM ARCHITECTURE
The PowerVR system is a 3D graphics technology featuring an original architecture in order to resolve the intrinsic cost/performance problem of conventional 3D graphics systems. The most typical functions, hidden surface removal and plane modeling, are described below.
1. Hidden Surface Removal
Conventional 3D graphics systems employ the Z-buffer that compares the z value (depth) of each polygon- configuring pixel when performing hidden surface removal (removing data invisible from the viewpoint). The memory requirement for 32-bit depth at 640 × 480 pixels is 1.2 Mbytes, which greatly affects the cost of the system. Moreover, because memory access must be executed the same number of times as the number of polygons that include the pixel for which hidden surface removal is to be performed, the system performance is affected by the memory band width (data transfer performance). In the PowerVR architecture, the display is divided into 32 × 32 pixels or 64 × 64 pixels segments called tiles and hidden surface removal is performed within the device. Accordingly, since no Z-buffer is necessary and the data written into the frame buffer is only the forefront visible pixel data, high performance 3D systems not limited by the memory system can be realized.
2. Plane Modeling
In addition to the conventional polygon modeling method (configuring with triangles and squares), PowerVR employs the method of modeling with an infinite plane (defining an area enclosed by planes as an object). The data (x, y, z) of each vertex of the polyhedron that configures the object is required in the polygon modeling method. On the other hand, in plane modeling, data is defined using only a normal vector and a point on a plane, which considerably reduces the amount of data. This data reduction directly contributes to reducing the processing time. Additionally, a unique function that performs real-time and automatic shadow generation for effective 3D rendition by using plane modeling is realized.
2 OUTLINE OF µPD62011 FUNCTIONS
The µPD62011 extends the functions of the µPD62010 and improves 3D graphics rendering, while realizing high performance.
1. Bi-linear Texture Mapping
The µPD62010 employs the MIP mapping function for precise texture mapping. MIP mapping is a precise texture mapping method (2-point texture) in which the texture to be mapped is prepared in advance, and then data is sampled from a large and small texture sheets corresponding to the object. The µPD62011 enhances the function of the µPD62010 and supports bi-linear texture mapping. In data sampling in the core of MIP mapping, mapping is performed by interpolating two points from each texture (4- point texture).
2. 66-MHz PCI Bus Interface
In the PowerVR system, the parameters/data for 3D image processing are captured via the PCI bus, and the generated 3D images are transferred to the 2D system via the PCI bus. The µPD62011 provides an interface compatible with the 66-MHz spec of PCI bus, which enables high-speed parameter transfer/image data transfer.
3. Floating Point Format Conversion Circuit
In the PowerVR system, parameters A and B of the plane equation Ax + By + C are processed in the 20-bit floating point format, and parameter C is processed in the 20-bit fixed point format. In the µPD62010, conversion from the IEEE floating point format to the above data format is performed by software. On the other hand, the µPD62011, which incorporates a format conversion circuit, enables loading of parameter data in the IEEE floating point format which enables high-speed processing by reducing the software load.
4. On-chip Pointer Register
When loading the parameters or object data in the main memory, the µPD62010 references the pointer table configured in memory but the µPD62011 accesses data directly because it has a pointer register. Moreover, successive data loading is enabled by the pointer chain function.
5. Output Image Mask Function
Since the PowerVR architecture adopts 3D screen processing in tile units, when adding 3D objects on a 2D background, the background color of tiles must be made transparent. The µPD62010 does this by software, while, the µPD62011 does this by masking the output image in pixel units.
6. Edge Sharing
When processing a polygon mesh structure, the amount of data processing is reduced greatly by sharing the data regarding the boundary edges of neighboring polygons.
7. Software-Compatible with µPD62010
The µPD62011 is compatible with the µPD62010 in the initial state immediately after reset. This function is enabled by register setting.
3 INTERNAL BLOCK DIAGRAM
Texture/ Parameter memory
µ PD62011
ISP block TSP block CPU 2D (VGA) display device PCI interface
Parameter/Texture data Image data after rendering Core logic PCI bus CPU ISP TSP 2D device
¥ Modeling data ¥ Hidden surface ¥ Shading ¥ Screen display base configuring removal ¥ Texture mapping, ¥ Geometry ¥ Shadow/Fog etc. operation, etc. judgment, etc.
The main function of the ISP block is performing hidden surface removal for an object list in a 3D space. The output of the ISP block is the ID of the visible surface corresponding to each pixel. Hidden surface removal carried in the ISP block has a precision equivalent to that of conventional Z buffering. As a result, when processing with a precision identical that of a 32-bit Z buffer is performed, the µPD62011 does not require a Z buffer memory. Moreover, the ISP block supports the shadow casting function indicating whether a shadow is generated in the visible surface. The TSP block mainly performs precise texture mapping and shading for the ID of the visible surface supplied by the ISP. The TSP also enables perspective correct texture mapping, smooth shading, transparent face overlaying, and fogging. Besides, the TSP block provides a method for processing visible surface with a minimum number of accesses to texture data stored in an external SDRAM. Both the ISP and TSP blocks have internal caches enabling an efficient local access for rendering parameters stored in these caches. The PCI bus interface is provided with both master and slave functions for efficient operation. When the µPD62011 reads the parameters related to the ISP block from the system memory, the PCI bus interface functions as PCI master and when it receives the parameters related to the TSP block, it functions as a PCI slave. The PCI bus interface performs optimum buffering for transferring data securely at high speed. The SDRAM/ SGRAM controller is designed to allow the blocks in the µPD62011 to share external SDRAM/SGRAM. The µPD62011 receives the parameters required for rendering via PCI bus and transfers 3D images with texture mapping or shading to the PCI address space. The 3D images data from the µPD62011 is transferred to the 2D graphics (VGATM controller) frame buffer allocated in the PCI address space.
4 PIN CONFIGURATION (Top View)
208-PIN PLASTIC QFP (28 × 28 mm) GNDE GND VDD(5V)E GP10 GP9 GP8 GP7 GP6 GNDE VDD(3.3V)E GP5 GP4 GP3 GP2 VDD(3.3V)E GNDE GP1 GP0 TM2 TM1 GND VDD(3.3V) N.C SDDATA08 SDDATA09 GNDE VDD(3.3V)E SDDATA10 SDDATA11 SDDATA12 SDDATA13 SDDATA14 SDDATA15 GNDE VDD(3.3V) SDDATA24 SDDATA25 SDDATA26 SDDATA27 SDDATA28 SDDATA29 GNDE VDD(3.3V)E SDDATA30 SDDATA31 SDDATA00 SDDATA01 SDDATA02 SDDATA03 VDD(5V)E GND GNDE 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VDD(3.3V)E 157 104 VDD(3.3V)E VDD(5V)E 158 103 VDD(5V)E GNDE 159 102 GNDE GP11 160 101 SDDATA04 GP12 161 100 SDDATA05 GP13 162 99 SDDATA06 GP14 163 98 SDDATA07 GNDE 164 97 SDDATA16 GP15 165 96 GNDE MEMCLK0 166 95 SDDATA17 MEMCLK1 167 94 SDDATA18 CLKCMPO 168 93 SDDATA19 VDD(3.3V)E 169 92 SDDATA20 TBI0 170 91 VDD(3.3V)E TBI1 171 90 GNDE TBO0 172 89 SDDATA21 GNDE 173 88 SDDATA22 CLKCMP1 174 JAPAN 87 SDDATA23 TMSEL0 175 86 SDWE TMSEL1 176 85 SDCAS VDD(3.3V)E 177 84 GND GNDE 178 83 SDRAS PVRCLK 179 82 SDCS1 N.C 180 D62011GD001 81 SDCS0 N.C 181 80 SDADDR09 GND 182 79 GNDE VDD(3.3V) 183 78 VDD(3.3V)E N.C 184 77 SDADDR00 N.C 185 76 SDADDR01 N.C 186 75 SDADDR02 PCIINTA 187 74 SDADDR03 GNDE 188 73 GNDE PCIRST 189 72 SDADDR04 PCICLK 190 71 SDADDR05 PCIGNT 191 70 SDADDR06 PCIREQ 192 69 SDADDR07 VDD(5V)E 193 68 SDADDR08 GNDE 194 67 GNDE VDD(3.3V)E 195 66 VDD(3.3V)E PCIAD31 196 65 SDADDR10 PCIAD30 197 64 SDADDR11 PCIAD29 198 63 SDDQM1 PCIAD28 199 62 SDDQM0 GNDE 200 61 GNDE PCIAD27 201 60 PCIAD00 PCIAD26 202 59 PCIAD01 PCIAD25 203 58 PCIAD02 PCIAD24 204 57 PCIAD03 PCICBE3 205 56 PCIAD04 PCIDSEL 206 55 PCIAD05 VDD(5V)E 207 54 VDD(5V)E VDD(3.3V)E 208 53 VDD(3.3V)E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 GND GND GND GNDE GNDE GNDE GNDE GNDE GNDE GNDE GNDE PCIBE2 PCIPAR PCIFRM PCIIRDY PCIAD08 PCIAD07 PCIAD06 PCIAD15 PCIAD11 PCIAD10 PCIAD09 PCIAD23 PCIAD22 PCIAD21 PCIAD20 PCIAD14 PCIAD13 PCIAD12 PCIAD19 PCIAD18 PCIAD17 PCIAD16 PCICBE0 PCICBE1 PCITRDY PCISTOP VDD(5V)E VDD(5V)E VDD(5V)E VDD(5V)E VDD(5V)E VDD(5V)E VDD(5V)E VDD(3.3V) PCIDVSEL VDD(3.3V)E VDD(3.3V)E VDD(3.3V)E VDD(3.3V)E VDD(3.3V)E VDD(3.3V)E
5 PIN FUNCTION LIST
Pin Name Function
PCIFRM PCI Cycle Frame
PCIIRDY PCI Initiator Ready
PCITRDY PCI Target Ready
PCIDVSEL PCI Device Select
PCISTOP PCI Stop/Disconnect
PCIPAR PCI Parity
PCIINTA PCI Interrupt A
PCIRST PCI Reset, used as master reset for the µPD62011
PCICLK Clock for PCI Interface
PCIGNT PCI Master Grant
PCIREQ PCI Master Request
PCICBE0 to 3 PCI Bus Command and Byte Enables
PCIIDSEL PCI Initialization Device Select
PCIAD00 to 31 PCI Address Data Bus
SDDQM0 to 1 Memory Request
SDADR00 to 11 Memory Address Bus
SDCS0 to 1 Memory Chip Select
SDRAS Memory Row Address Strobe
SDCAS Memory Column Address Strobe
SDWE Memory Write Enable
SDDATA00 to 31 Memory Data Bus
GP0 to 15 General Purpose I/O Port
MEMCLK0 to 1 Memory Clock
CLKCMPO Clock Adjusting Port (Output)
CLKCMPI Clock Adjusting Port (Input)
PVRCLK Internal Clock
TM1 to 2 Test Input
TBI0 to 1 Test Input
TBO0 Test Output
TMSEL0 to 1 Test Input
VDD (3.3 V) Internal Digital VDD (3.3 V)
GND Internal Digital GND
VDD (5 V) E External Digital VDD (5 V)
VDD (3.3 V) E External Digital VDD (3.3 V)
GNDE External Digital GND
6 INTERFACE BETWEEN µPD62011 AND MEMORY
(1) 1 Mbyte
PCI
SDRAS RAS SDCAS CAS
SDDATA0 - 31 DQ0 - 31 8-MBit µPD62011 SGRAM SDADDR00 - 09 A0 - 9 SDWE WE SDDQM0 DQM0 - 3
(2) 2 Mbytes
PCI SDCS0 CS SDRAS RAS SDCAS CAS 8-MBit SDWE WE SGRAM SDDQM0 DQM0 - 3 SDDATA0 - 31 DQ0 - 31 SDADDR0 - 9 A0 - 9
µPD62011 RAS CAS WE 8-MBit DQ0 - 31 SGRAM A0 - 9 SDDQM1 DQM0 - 3 SDCS1 CS
(3) 4 Mbytes
PCI SDRAS RAS SDCAS CAS SDWE WE 16-MBit SDDQM0 LDQM/UDQM SDRAM SDDATA0 - 15 DQ0 - 15 SDADDR0 - 11 A0 - 11
µPD62011 RAS SDDATA16 - 31 DQ0 - 15 CAS 16-MBit WE SDRAM LDQM/UDQM A0 - 11
Recommended Devices 8-Mbit SGRAM : µPD481850GF-A12 16-Mbit SDRAM : µPD4516161G5-A10, µPD4516161G5-A12
7 PACKAGE DRAWING
208-PIN PLASTIC QFP (FINE PITCH) (28 × 28 mm)
A B
156 105 157 104
detail of lead end C D S R Q
208 53 1 52 F
G H I M J K P M N L NOTE ITEM MILLIMETERS INCHES Each lead centerline is located within 0.10 mm (0.004 inch) of A 30.6±0.2 1.205±0.008 its true position (T.P.) at maximum material condition. B 28.0±0.2 1.102+0.009 Ð0.008
C 28.0±0.2 1.102+0.009 Ð0.008 D 30.6±0.2 1.205±0.008 F 1.25 0.049 G 1.25 0.049 +0.05 H 0.22Ð0.04 0.009±0.002 I 0.10 0.004 J 0.5 (T.P.) 0.020 (T.P.) K 1.3±0.2 0.051±0.008 +0.008 L 0.5±0.2 0.020Ð0.009
M 0.17+0.03 0.007+0.001 Ð0.07 Ð0.003 N 0.10 0.004 P 3.2 0.126 Q 0.4±0.1 0.016+0.004 Ð0.005 R 5¡±5¡ 5¡±5¡ S 3.8 MAX. 0.150 MAX. P208GD-50-LML, MML-2
8 [MEMO]
9 [MEMO]
10 PowerVR and PowerSGL are trademarks of VideoLogic Limited. Direct3D is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. VGA is a trademark of International Business Machines Corporation.
The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or of others.
M7A 96.10
11 For further information, please contact:
NEC Corporation NEC Building 7-1, Shiba 5-chome, Minato-ku Tokyo 108-01, Japan Tel: 03-3454-1111 Fax: 03-3798-6059
[North & South America] [Europe] NEC Electronics (France) S.A. 9, rue Paul Dautier-BP 187 NEC Electronics Inc. NEC Electronics (Germany) GmbH 78142 Velizy-Villacoublay Cédex 2880 Scott Blvd. Kanzlerstr. 2, France Santa Clara, CA 95050-2554 40472 Düsseldorf Tel: 01-30-67-58-00 Tel: 408-588-6000 Germany Fax: 01-30675899 800-366-9782 Tel: 0211-650302 Fax: 408-588-6130 Fax: 0211-6503490 Madrid Office 800-729-5288 Munich Office Juan Esplandiu, 15 [Regional Sales Offices] Arabellastr. 17 28007 Madrid, Spain 81925 München, Germany Tel: 01-504-2787 Central Region Tel: 089-921003-0 Fax: 01-504-2860 Greenpoint Tower Fax: 089-92100315 2800 West Higgins NEC Electronics Italiana s.r.l. Road Suite 765 Stuttgart Office Via Fabio Filzi, 25/A, Hoffman Estates, Industriestr. 3 20124 Milano, Italy IL 60195 70507 Stuttgart, Germany Tel: 02-667541 Tel: 847-519-3930 Tel: 0711-99010-0 Fax: 02-66754299 Fax: 847-519-9329 Fax: 0711-99010-19 Norcal Region Hannover Office [Asia & Oceania] 3033 Scott Blvd. Königstr. 12 Santa Clara, CA 95054 30175 Hannover, Germany NEC Electronics Hong Kong Limited Tel: 408-588-5100 Tel: 0511-33402-0 12/F., Cityplaza 4, Fax: 408-588-5134 Fax: 0511-33402-34 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 Eastern Region Benelux Office Fax: 2886-9022/9044 901 Lake Destiny Drive Boschdijk 187a Suite 320 5612 HB Eindhoven, Seoul Branch Maitland, FL 32751, U.S.A. The Netherlands 10F, ILSONG Bldg., 157-37, Tel: 407-875-1145 Tel: 040-2445845 Samsung-Dong, Kangnam-Ku Fax: 407-875-0962 Fax: 040-2444580 Seoul, the Republic of Korea Tel: 02-528-0303 Western Region Scandinavia Office Fax: 02-528-4411 One Embassy Centre P.O. Box 134 9020 S.W. Washington 18322 Taeby, Sweden NEC Electronics Taiwan Ltd. Square Road Tel: 08-6380820 7F, No. 363 Fu Shing North Road Suite 400 Fax: 08-6380388 Taipei, Taiwan, R. O. C. Tigard, OR 97223, U.S.A. Tel: 02-719-2377 Tel: 503-671-0177 NEC Electronics (UK) Limited Fax: 02-719-5951 Fax: 503-643-5911 Cygnus House, Sunrise Park Way, Milton Keynes, MK14 6NP, U.K. NEC Electronics Singapore Pte. Ltd. NEC do Brasil S.A. Tel: 01908-691-133 101 Thomson Road #04-02/05 Div. Componentes Eletronicos Fax: 01908-670-290 United Square, Singapore 307591 Rodovia Presidente Dutra, KM 218 Tel: 253-8311 CEP 07210-902-Jd. Fax: 250-3583 Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829
G97. 8
Document No. S12238EJ3V0PF00 (3rd edition) Date Published November 1997 N
© 1997 Printed in Japan