Organic Electronics: Devices, Circuits and Applications

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Organic Electronics:

Devices, Circuits and Applications

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Jin Jeon

July 2012

This work is licensed under a Creative Commons Attribution- Noncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/

This dissertation is online at: http://purl.stanford.edu/zv127wb2165

ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Zhenan Bao, Primary Adviser

I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Yoshio Nishi

I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Ada Poon

Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives.

iii

ABSTRACT

Organic materials have brought exciting opportunities for flexible, light weight, low cost, and disposable electronics. However, there are still several technical challenges for the wide spread of this technology. In this dissertation, I discuss about the challenges and the improvements of organic electronics.

In the first part, I explore device engineering for organic thin film transistors (OTFTs).

New device architecture and fabrication methods to improve the OTFT characteristics are proposed. Short channel and self-aligned OTFTs are implemented on a non-planer substrate. The self-aligned structure enables accurate alignment between the electrodes with a pre-defined prism-structure dimension, thus reducing parasitic overlap capacitance.

In the second part, circuit engineering based on OTFTs is studied. An OTFT circuit design methodology is proposed to enable accurate analysis and verification in the design stage. Various topologies of digital circuits such as complimentary and unipolar OTFT circuits based on this design methodology are demonstrated.

The third part focuses on application engineering, specifically on the implementation of disposable and flexible organic electronic sensors. Wireless temperature sensor based on conductive filled polymer is demonstrated. The stability and reproducibility is improved and the sensitive temperature can be tuned by employing a binary polymer system.

DEDICATION

The author wishes to dedicate this dissertation to Eunju Song and Soul Jeon.

ACKNOWLEDGEMENT

Foremost, I would like to express my sincere gratitude to my advisor Professor Zhenan

Bao for the continuous support of my Ph.D. study and research, for her patience, motivation, enthusiasm, and immense knowledge. Her guidance helped me in all the time of research and writing of this dissertation. I could not have imagined having a better advisor and mentor for my Ph.D. study.

I am grateful to Professor Yoshio Nishi and Ada Poon for their precious time and efforts as members of my reading and defense committee.

I also thanks to Professor Boris Murmann for his valuable suggestions on my research.

I would like to thank all the past and present group members for their great assistance and friendship. Especially, I thank Benjamin T, Dr. Peng Wei, Olasupo (Ade) Johnson,

Dr. Do Hwan Kim, Dr. Han-Bo-Ram Lee for the valuable interaction and collaborations.

Samsung Mobile Display has been sponsoring me for five years, which was indispensible for my Ph.D. study.

Finally, my deepest gratitude goes to my wife, Eunju Song, for her continuous support and inspiration in my life. I also thank to my daughter, my mom and dad.

TABLE OF CONTENTS

Abstract ...... iv Dedication ...... v Acknowledgement ...... vi Table of Contents ...... vii List of tables ...... x List of figures ...... xi CHAPTER 1 : Introduction ...... 1 1.1 Organic Semiconductor ...... 2 1.2 Organic Thin Film Transistor ...... 5 1.2.1 Basic Operation of OTFT ...... 6 1.2.2 Capacitance ...... 9 1.2.3 Contact Resistance and Device Architectures of OTFT ...... 10 1.2.4 Maximum Operating Frequency ...... 14 1.3 Applications ...... 15 1.4 Motivation and organization of this dissertation ...... 17 CHAPTER 2 : Device Engineering ...... 20 2.1 Background and Motivation ...... 20 2.2 A review of channel electrodes patterning methods ...... 21 2.2.1 Shadow Mask Patterning ...... 21 2.2.2 Photolithography ...... 23 2.2.3 Nano-Imprinting Lithography (NIL) ...... 25 2.2.4 Vertical Channel Device Structure ...... 26 2.3 A review of self-aligned structures ...... 29 2.4 Experimental ...... 30 2.5 Fabrication Process of PRISM OTFT ...... 31 2.5.1 Fabrication of a Master Mold for Imprinting ...... 32 2.5.2 Imprinting of PRISM Structures ...... 34 2.5.3 OTFT Fabrication on Prism Structures ...... 37 vii

2.6 Characteristics of PRISM OTFT ...... 39 2.6.1 Fabrication Results...... 39 2.6.2 Frequency Characteristic of PRISM OTFTs...... 40 2.6.3 DC Characteristics of Prism OTFT...... 42 2.7 Summary ...... 43 CHAPTER 3 : Circuit Engineering...... 45 3.1 Background and Motivation ...... 45 3.2 Design Methodology for OTFT Circuits ...... 46 3.3 Experimental ...... 50 3.4 A Circuit simulation model for OTFT ...... 52 3.4.1 The Non-ideal Characteristics of OTFT ...... 52 3.4.2 Device Model for OTFTs...... 55 3.5 Complementary OTFT Circuits ...... 58 3.5.1 Complementary Inverter ...... 58 3.5.2 Electrical Measurement of Complementary Inverter ...... 61 3.6 Unipolar Type Inverter ...... 63 3.6.1 Conventional Unipolar Circuits ...... 64 3.6.2 Bootstrap Unipolar Digital Circuits ...... 65 3.6.3 Fabrication of Unipolar Digital Circuits ...... 69 3.6.4 Electrical Characterizations of Unipolar Digital Circuits ...... 71 3.7 Summary ...... 74 CHAPTER 4 : Application Engineering (A Flexible Wireless Thermal Sensor) ...... 76 4.1 Backgrounds and Motivation ...... 76 4.2 Experimental ...... 78 4.3 Thermal sensor based on metal filled polymer ...... 80 4.3.1 Introduction to Conductive Filled Polymers ...... 80 4.3.2 Ni Filled Polymer Temperature Sensor Development ...... 82 4.3.3 Plasticizer Effects...... 87 4.3.4 Binary Polymer Composites ...... 90 4.4 Wireless temperature sensor ...... 97

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4.4.1 Wireless Temperature Sensor Architecture ...... 97 4.4.2 Flexible Wireless Temperature Sensor Tag ...... 102 4.5 Summary ...... 105 CHAPTER 5 : Conclusions and outlook ...... 107 5.1 Conclustion ...... 107 5.2 Outlook ...... 108 bibliography ...... 110

LIST OF TABLES

Number Page

Table 3.1 Inverter output characteristics...... 71 Table 4.1 PTC effects of various polymers ...... 83 Table 4.2 Crystallinity and resistance of a Ni filled PE with different cooling rates...... 87 Table 4.3 Properties of different thermal sensors ...... 97

LIST OF FIGURES

Number Page

Figure 1.1 Organic semiconductors (a) pentacene, (b) tetracene, (c) C60, (d) oligothiophenes, (e) polythiophenes poly(3-hexyl thiophene) (P3HT) and (f) poly(p-phenylene vinylene) (PPV)...... 4 Figure 1.2 Energy band diagram of MIS structure (a) at equilibrium state, (b) with negative gate bias. (c) Cross-section of OTFT with negative gate bias.

Here ΦM is metal work function and χ is organic semiconductor electron

affinity. EC is the lowest level of the conduction band, EV is the highest

level of the covalent band, EF is Fermi energy level, and EG is energy gap of organic semiconductor...... 7 Figure 1.3 Capacitances of OTFT...... 10 Figure 1.4 Energy band diagram of metal-semiconductor contact (a) at equilibrium state, (b) with negative gate bias...... 11 Figure 1.5 OTFT architectures (a) top-contact with top-gate, (b) bottom-contact with top-gate, (c) top-contact with bottom-gate, and (d) bottom-contact with bottom-gate...... 13 Figure 2.1 (a) A photograph of a metal shadow mask, (b) patterned metal (Al and Au) layers with the shadow mask and (c) a schematic diagram of shadow mask process...... 22 Figure 2.2 A schematic diagram of photolithography process...... 24 Figure 2.3 A schematic diagram of a vertical-channel OTFT ...... 28 Figure 2.4 Self-aligned structure of a silicon-based MOSFET...... 29 Figure 2.5 Structure of PRISM OTFT ...... 32 Figure 2.6 Fabrication of a silicon master mold. (a) A silicon (100) wafers with a 300 nm thermally grown oxide. (b) Patterning of a silicon oxide layer by standard photolithography process. (c) Silicon wet etching with potassium hydroxide (KOH) . (d) Stripping the remaining oxide layer using buffered

hydrofluoric acid...... 33 Figure 2.7 Microscope image of imprinted PRISM patterns of (a) PMMA, (b) Polyethylene, (c) polystyrene, and (d) polyvinylalohol substrate...... 35 Figure 2.8 Scheme of prism substrate fabrication process. (a) A Silicon master mode with prism-shape arrays. (b) PMMA deposition on PET substrate. (c) Imprinting. (d) Imprinted prism-like structures...... 36 Figure 2.9 Scheme of prism-OTFT fabrication process. (a) Aluminum (gate electrodes) layer deposition with a tilt angle. (b) Gate insulator and organic semiconductor deposition. (c) Gold (source-drain electrodes) layer deposition with a tilt angle...... 38 Figure 2.10 (a) Cross-sectional scanning electron microscope (SEM) image of pentacene prism-OTFT and (b) close-up of the channel region...... 40 Figure 2.11 Measured capacitance between gate and source-drain electrode of (a)

metal-insulator-metal (MIM, Al-AlOx-Au) structure (W=100 μm , L=8 μm) and (b) pentacene OTFT with voltage bias (W=100 μm , L=8 μm)...... 41 Figure 2.12 Frequency characteristics of of pentacene OTFTs (W=100 um, L=8 um). ...42 Figure 2.13 DC current-voltage characteristics of prism OTFTs. (a) Output and (b) transfer characteristics of a p-channel (pentacene) OTFT. (c) Output and (d) transfer characteristics of a n-channel (C60) OTFT...... 43 Figure 3.1 Flow chart for a design process of integrated circuits ...... 47 Figure 3.2 An example of schematic design (a NAND gate)...... 48 Figure 3.3 An example of layout design (a NAND gate)...... 49 Figure 3.4 A gate bias dependency of p-type (pentacene) OTFT mobility...... 54 Figure 3.5 Equivalent circuit diagram of an OTFT model...... 56 Figure 3.6 Comparison of measured (symbol) vs. modeled (curves) drain current characteristics for a p-channel (pentacene) OTFT with W/L = 5000 μm/100 μm (a) transfer characteristic, (b) output characteristics...... 57 Figure 3.7 Comparison of measured (symbol) vs. modeled (curves) drain current characteristics for an n-channel (C60) OTFT with W/L = 8 μ/100 μ (a) transfer characteristic, (b) output characteristics...... 57

xii

Figure 3.8 Comparison of measured (symbol) vs. modeled (curves) drain current characteristics for an p-channel (pentacene) OTFT with W/L = 8 μ/100 μ. ....58 Figure 3.9 Complementary inverter. (a) Circuit diagram and (b) simplified circuit model...... 59 Figure 3.10 SPICE simulation results of (a) transfer curves with various transistor size ratio (SPICE simulation) and (b) noise margin if a complementary inverter...... 60 Figure 3.11 Photograph of complementary inverters under bending...... 61 Figure 3.12 (a) Voltage transfer curve (line with symbol) and noise margin window and (d) DC gain. All measurement was carried out inside a nitrogen glovebox...... 62 Figure 3.13 Unipolar p-type inverters. (a) Diode-load inverter and (b) depletion-load inverter...... 65 Figure 3.14 A circuit diagram of a bootstrap inverter...... 66 Figure 3.15 SPICE simulation result of (a) peak-to-peak output swing (b) noise margin of bootstrapped inverter...... 67 Figure 3.16 (a) Bootstrap NAND circuit and (b) truth table...... 68 Figure 3.17 (a) Bootstrap NOR circuit and (b) truth table...... 68 Figure 3.18 (a) Cross section of transistor and capacitor (b) Photograph of circuits on the flexible substrate...... 70 Figure 3.19 (a) Transfer characteristic and (b) output characteristics of a typical pentacene OTFT (W/L = 5000 μm/100 μm)...... 72 Figure 3.20 Measurement configuration of OTFT circuits...... 72 Figure 3.21 Voltage transfer characteristic (line) and noise margin window of (a) a diode load p-type inverter, (b) bootstrap p-type inverter...... 73 Figure 3.22 Measured typical transient output waveforms of (a) a diode load p-type inverter, (b) bootstrap p-type inverter...... 73 Figure 3.23 Measured transient waveforms of a bootstrap NAND gate...... 74 Figure 4.1 Schematic illustration of the metal (Nickel particle) filled polymer composite...... 81

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Figure 4.2 Resistivity of PE composites as a function of Ni concentration...... 82 Figure 4.3 Resistivity versus temperature during 5 heating and cooling cycles...... 85 Figure 4.4 A plasticizer effect on the crystallinity and resistivity of Ni filled PE composite with cooling rates...... 88 Figure 4.5 The resistivity of a Ni filled PE with DOP versus temperature with 5 heating and cooling cycles ...... 89

Figure 4.6 DSC thermo diagram of PEO (MW=1.5k), PE, and mixture of PE/PEO (with the ratio of 2:1)...... 91 Figure 4.7 Resistivity versus Temperature with different polymer ratios (40 wt% Ni). ...92 Figure 4.8 (a) DSC thermo diagram of PEO with different molecular weights. (b) Resistivity of PE/PEO binary polymers (weight ratio 2:1, 40 wt% Ni) versus temperature...... 94

Figure 4.9 Cross sectional SEM image of (a) a Ni filled PEO/PE (MW=1.5k) composite (weight ratio = 2:1) and (b) close-up image. (c) A SEM image of Ni particle...... 95 Figure 4.10 Resistivity of PE/PEO binary polymers (weight ratio 2:1, 40 wt% Ni) versus temperature over 6 thermal cycles...... 96 Figure 4.11 A block diagram of typical passive RFID architecture...... 98

Figure 4.12 A test circuit structure of wireless thermal sensor. L1 and R1 are the

inductance and series resistance of base station antenna, C1 is the

capacitance, and RS is the output resistance of signal generator. L2 and R2

are the inductance and series resistance of the tag antenna, C2 is the

capacitance, and RT is the resistance of the thermal sensor...... 99 Figure 4.13 A circuit diagram of wireless thermal sensor test structure, where M is mutual inductance (unit of henry) between the base station antenna and the tag antenna...... 100

Figure 4.14 A simulation of modulated voltages (V1) at the base station with the

change of RT...... 102 Figure 4.15 (a) A circuit diagram of the wireless thermal sensor tag. (b) Prototype of wireless thermal sensor tag and (c) the tag under bending...... 103

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Figure 4.16 The schematic of experiment set-up for wireless sensor calibration...... 104 Figure 4.17 Statistical data of readout voltage as a function of temperature...... 105

CHAPTER 1: INTRODUCTION

Carbon, alone of all elements, is able to form a diversity of compounds from methane, with one carbon atom, to DNA, with 10 billion carbons [1]. Organic electronics is a branch of electronics based on these carbon materials. The word „Organic‟ in organic electronics is originated from organic chemistry. Before the mid-1700s, it had referred to chemical compounds that were found in or derived from living organisms [1]. However, the modern definition of “Organic” evolved to include all other compounds contains carbon. Why did nature select carbon as a primary material for all living organisms? Why is carbon so special to us? The answer may be related to the special bonding properties of carbon.

The location of carbon atom in the periodic table is in the group IV, same as the silicon atom, which means that it can share four valence electrons. Carbon atom can form three different hybridization bonding configurations, which are sp, sp2, and sp3 hybridized bonding. The most common configuration is a carbon-carbon single bond, i.e. sp3 hybridized covalent bond. This bonding is found in the saturated compounds that constitute elements of most plastic materials [1]. The valence electrons of carbon backbone are tightly bounded in sp3 hybridized covalent bonds. Thus most organic materials show large band gaps, which is the main reason why most polymers such as thermal plastics are both electrical insulator and transparent. These polymers are used as

flexible and transparent substrates for organic electronics or as insulators for organic thin film transistors (OTFTs). In sp2 hybridized covalent bonds, carbon atoms form carbon- carbon double bonds. All the semiconducting and conducting properties of organic materials are based on the π-conjugated bonding [2], which is defined as an alternating carbon single and double bond.

Organic electronics has benefited from the above special bonding properties of carbon atoms. Semiconducting, conducting and insulating properties combined with the properties of typical plastics have enabled the unique features of organic electronics. In this dissertation, I focus on studying organic electronics devices, circuits, and also applications.

1.1 ORGANIC SEMICONDUCTOR

Semiconducting properties of organic materials are the foundation of organic electronics. Organic semiconductors are based on π-conjugated carbon compounds. The

π-electrons delocalize over the molecule, which enable the electrons to move in and out molecule. The formation of delocalized π-molecular orbital defines the highest occupied molecular orbital (HOMO) and the lowest unoccupied molecular orbital (LUMO). The

HOMO and LUMO levels determine the electrical and optical properties of the organic semiconductor molecules [3]. If conjugated molecules are brought to close proximity, the molecular orbitals will overlap. These overlapped molecular orbitals will split in

accordance to Pauli Exclusion Principle [3]. The nature of bonding in organic semiconductors is fundamentally different from inorganic semiconductors. Organic molecular crystals are held together by van der Waals interaction [2], which is a considerably weaker intermolecular force as compared to covalently bonded semiconductors, like Si or Ge. The consequences are manifested in their resulting mechanical and thermodynamic properties, such as reduced hardness, lower melting point and a weaker delocalization of electronic wave functions over neighbor molecules [3].

Due to weak intermolecular bonding, many electronic properties of organic semiconductors are determined by the structure of an isolated molecule. Also, the weak intermolecular overlap of electronic orbitals results in a low mobility of carriers.

Organic semiconductors can be generally categorized into oligomers and polymers based on molecular weight. In oligomeric semiconductors, the carbon atoms form larger molecules typically with aromatic rings as the basic unit and electrons become delocalized through the molecules [2]. Organic semiconductors such as pentacene, tetracene, C60 and oligothiophenes fall into this category [2]. These small molecules are usually deposited by thermal evaporation. On the other hand, in polymer organic semiconductors, the carbon atoms form a long chain and electrons become delocalized along the chain and adopt a one-dimensional π-conjugated system. Polymer semiconductors such as polythiophenes poly(3-hexyl thiophene) (P3HT), and poly(p- phenylene vinylene) (PPV) [4] are in this category and are usually deposited by solution processing. In general, small molecule semiconductors show better thin film charge

transport than polymer semiconductors. Thus small molecules (pentacene and C60) were chosen for the semiconductor layers in my experiments.

(a)

(b)

(e) (f)

Figure 1.1 Organic semiconductors (a) pentacene, (b) tetracene, (c) C60, (d) oligothiophenes, (e) polythiophenes poly(3-hexyl thiophene) (P3HT) and (f) poly(p- phenylene vinylene) (PPV) [2].

Organic semiconductors are the key materials of organic electronics. The special properties of organic semiconductors such as lower melting point, easy and cheap deposition process enable a number of advantages to organic electronics. Although the performance of organic electronic devices has significantly improved during the last

decade, the electrical performance of organic semiconductors is still not comparable to that of single crystalline silicon [2, 5]. Moreover, it is known that most organic semiconductors have a poor environmental stability [4]. Nevertheless, there are several unique properties of organic semiconductors conferred to organic electronics.

First, organic molecules have no dangling bonds [3]. Thus electrical properties of organic devices are not seriously affected by the interface states of junctions as the inorganic devices. Also, organic semiconductor layers can be deposited on a large variety of substrates with various deposition methods including printing or spin coating. They do not require epitaxial growth or high temperature process.

Second, properties of organic semiconductor materials can be chemically tuned to meet the requirements of specific applications through chemical synthesis [2]. Hence, this approach provides great motivation and infinite possibility to researchers.

Third, organic semiconductors can be processed at low temperatures. Organic semiconductors can be deposited on flexible substrates, such as plastic films, but they cannot withstand high temperatures. This mechanical flexibility will enable new applications. The perspective of low cost device fabrication on large, flexible substrates is clearly unachievable using standard inorganic semiconductor processing technologies.

1.2 ORGANIC THIN FILM TRANSISTOR

An organic thin film transistor (OTFT) is a field effect transistor using an organic semiconductor film as its active layer. The basic operation and characteristics of OTFT will be described here.

1.2.1 Basic Operation of OTFT

Organic thin film transistor is a three terminal device, where a voltage applied at the gate controls the current flowing from drain to source by modulating channel carrier density [2]. Two types of OTFTs are possible based on majority carrier type. In p-type

OTFT, holes are the majority charge carriers and a negative bias voltage is applied on the gate electrode to induce a hole channel layer. On the other hand, electrons are the major charge carriers for n-type OTFTs, where positive source-drain current is observed with positive gate bias voltage. The majority carrier type depends on which type carriers are injected by the contact. Therefore, whether the device is p-type or n-type is strongly related to the OTFT material and device structure, with which the transport characteristics are measured. The basic operational mechanism of a field effect transistor is based on metal-insulator-semiconductor (MIS) capacitor system. The energy band diagram of MIS structure is shown in Figure 1.2(a), where the Fermi levels of metal and organic semiconductor are assumed to be the same, thus there is no band bending without external bias. If a negative gate bias is applied to the gate electrode, the bands bend upwards. Thus holes are accumulated and confined to the organic semiconductor region near the insulator, which forms a conducting channel.

Vacuum Level (a) (b) qχ Vacuum Level qΦM qΦM qχ LUMO (EC) EG EF LUMO (EC)

HOMO (EC) EF VGS HOMO (EC)

Substrate

Figure 1.2 Energy band diagram of MIS structure (a) at equilibrium state, (b) with negative gate bias. (c) Cross-section of OTFT with negative gate bias. Here ΦM is metal work function and χ is organic semiconductor electron affinity. EC is the lowest level of the conduction band, EV is the highest level of the covalent band, EF is Fermi energy level, and EG is energy gap of organic semiconductor.

Lateral cross-section of P-type OTFT with gate bias is shown in Figure 1.2(c). The source and drain electrodes of an OTFT are separated by a lateral distance known as the channel length L. The source and drain regions are electrically disconnected unless there is an accumulation layer at the surface to provide a conducting channel between them.

When a channel layer is formed by applying a voltage on the gate electrode and a voltage is applied between the source and drain electrodes, carriers can enter the channel at the source and leave via the drain, resulting in a current flow. Current-voltage characteristics

of an OTFT can be described using a square-law model of MOSFET show as below. In

the linear region for VVVDS GS T ,

W VDS ICVVVDS  ox e GS  T  DS (2.1) L 2 where W and L are the channel width and length, Cox is the unit capacitance of gate insulator, μe is the field-effect mobility, and VGS, VDS, VT are the gate-source, drain- source and threshold voltages respectively. In the linear region, drain current increases linearly with VDS. However, when VDS increases above this limit, channel region near drain electrode becomes depleted. This depleted region functions as a limitation for current, which make current saturated with the further increase of VDS. In the saturation

region, where VVVDS GS T , drain current can be described as follows:

1 W 2 ICVV     (2.2) DS2 L ox e GS T

This model is based on the gradual channel approximation [6] and assumes that the field-effect mobility is independent of gate bias, and the contact resistances are negligible to channel resistance. This ideal current equation of MOSFET is simple and intuitive, but it cannot account for several non-linear behaviors of OTFT. Hence, transistor model can be improved by incorporating several nonlinear effects such as contact effects, bias dependent mobility, and leakage currents, in which I will described in detail in the

Chapter 3 of this dissertation.

1.2.2 Capacitance

The basic operational mechanism of OTFT is based on MIS capacitor systems. Thus significant capacitances inevitably exist between the electrodes. In an ideal OTFT structure, the source and drain electrodes do not overlap with each other, thus source- drain capacitance (CSD) is negligible. The gate-source and gate-drain capacitance are combinations of the channel capacitance (CGSI and CGDI) and the parasitic overlap capacitance (CGSO and CGDO) as shown in Figure 1.3. The values of channel capacitances depend on the bias conditions of the OTFT. The capacitance between gate and channel is assigned to gate-source or gate-drain capacitance according to the bias condition. In the

cut-off region where VVGS T , there is no conducting channel layer, thus both CGSI and

CGDI are zero. In the linear region, where VVVDS GS T , the total gate-channel capacitance is equally divided to source and drain electrodes as follows:

1 C C WLC (2.3) GSI GDI2 I

In the saturation region, where VVV, DS GS T

2 C WLC,0 C (2.4) GSI3 I GDI

LOV L LOV Source Drain Organic semiconductor

Insulator CGSOV CGSI CGDI CGDOV Gate Substrate

Figure 1.3 Capacitances of OTFT.

The overlap capacitance can be approximated as parallel plate capacitance as CGSOV =

CGDOV = W LOV CI, where W is channel width, and CI is unit capacitance of the gate insulator. LOV is the overlap length between the gate and the source-drain electrodes, which is necessary to ensure that the channel induced by the gate reaches the source and drain electrodes. LOV is usually large for the fabrication processes with poor alignment such as shadow masking or high-speed printing. Moreover, OTFTs on plastic substrates require an additional overlap margin to compensate for the expansion of the plastic with temperature or strain. Thus, overlap capacitance can be a dominant factor that decreases the operation frequency especially for short channel OTFTs on a flexible substrate. It may also vary depending on the alignment result. This overlap capacitance can be dramatically reduced if a self-aligned OTFT process can be developed.

1.2.3 Contact Resistance and Device Architectures of OTFT

In an ideal OTFT, the contact resistance is negligible compared to the channel resistance. But the contact resistance in many OTFT devices is comparable or even exceeds the channel resistance. Contact resistance is generally referred to as the resistance associated with carrier injection and collection, while the channel resistance is the resistance across the channel [2]. A major portion of contact resistance is from the contact barrier between metal and organic semiconductor, which is the resistance to access the channel region inside the organic semiconductor. Theoretical contact barrier height depends on the difference between the work function of the metal and the HOMO

(for p-type) or LUMO (for n-type) of organic semiconductor. Thus selection of matching metal contacts with the organic semiconductor is important to reduce this barrier height

[2]. As shown in Figure 1.4, the presence of a barrier for hole injection from a metal contact (Au) into an organic semiconductor (pentacene) and a Schottky contact is formed at the interface of Au and pentacene. For an ideal contact, the barrier height is given by

qBh  E g  q()  M   (2.5)

Vacuum Level Vacuum Level (a) (b) qχ qχ qΦM qΦM LUMO (EC) LUMO (EC) EG EG

VGS ΦBh ΦBh EF HOMO (EC)

HOMO (EC)

Figure 1.4 Energy band diagram of metal-semiconductor contact (a) at equilibrium state, (b) with negative gate bias.

Here, ΦM is the work function of the metal,  is the electron affinity, and EG is the energy gap which is determined by the gap between the HOMO level and the LUMO level. Applying a positive bias to the metal electrode injects holes from the metal to the organic semiconductor only if the holes can get over the barrier, which is called thermionic emission. Thus the electronic structure at the interface is very important to determine contact resistance and the performance of OTFTs.

A general method to decrease contact resistance in the inorganic transistor is through doping [7]. Heavy doping of semiconductor reduces the barrier width such that carriers can go through the barrier by tunneling. But this is not usually applicable to OTFTs. As a result, contact resistance in organic devices is much higher than that in inorganic counter parts, limiting the mobility of OTFTs. Thus, in OTFT, the selection of metal and organic material is very important in order to minimize the barrier height, and the selection of device structure can significantly impact contact resistance. There are four possible architectures for OTFT based on the positions of gate and source-drain electrodes relative to the organic semiconductor layer [2]. Top-gated device structures have not been widely used in the fabrication of OTFT, because device performance can be significantly degraded during the deposition of the gate insulator and gate electrodes. Also, the top surface roughness of organic semiconductor can induce additional degradation to the device performance. However, in recent years, top-gated devices have become more widely used for some organic semiconductors. Higher mobilities than bottom-gate devices were reported [8, 9], even though the exact reason is not well understood. The

bottom-contact OTFT in Figure 1.5(c) and the top-contact structure in Figure 1.5(d) are different according to the sequence of their fabrication steps.

(a) (b) Gate Gate Insulator Insulator Source Drain Organic semiconductor Organic semiconductor Source Drain

Substrate Substrate

Source Drain Organic semiconductor Organic semiconductor Source Drain Insulator Insulator Gate Gate

Substrate Substrate

Figure 1.5 OTFT architectures (a) top-contact with top-gate, (b) bottom-contact with top- gate, (c) top-contact with bottom-gate, and (d) bottom-contact with bottom-gate.

In bottom-contact OTFT devices, the organic semiconductor is deposited onto the gate insulator and the source/drain contacts. In top-contact OFET devices, the source and drain contacts are usually deposited on the organic semiconductor through a shadow mask. In case of the top-contact OTFT, injected charges need to travel from the metal- organic semiconductor interface to the accumulation layer, which adds access resistance to the overall devices. Thus the thickness of the organic semiconductor layer should not be too large [10]. In case of the bottom-contact OTFT, contacts are in the same plane as the channel. Thus only side areas of the contacts contribute to the charge injection to the

channel region. Also, additional contact resistance originates from the disturbed crystal growth at the edge of metal contacts, which results in an additional contact barrier at the interface of the metal and organic semiconductor [11, 12]. For example, the film at the edge of the contact is quite rough, and an organic semiconductor, such as pentacene, cannot form a well-defined packing structure. Smaller crystal size at the edge forms a large number of grain boundaries that contain many morphological defects [11]. These defects act as charge-carrier traps, and are considered to be responsible for degrading the performance in bottom-contact OTFTs [11, 12]. Also, top-contact structures have increased effective metal–semiconductor contact areas due to the top surface roughness of the organic semiconductor. Thus top-contact OTFTs generally exhibit much lower contact resistances than bottom-contact OTFTs. The contact resistance becomes a more critical issue when scaling down the device size, as channel resistance scales proportionally with channel length and contact resistance increases due to the contact area scaling.

1.2.4 Maximum Operating Frequency

Applications such as radio frequency identification cards (RFIDs), wearable electronics and sensor networks demand high speed and low-voltage circuit operation based on high performance organic transistors. Even with recent progress in the synthesis of organic semiconductors and dielectric materials to enhance the carrier mobility, organic thin film transistor (OTFT) performance is still insufficient for more demanding

electronic applications. For example, rectifying circuits of RFIDs operate at 13.56 MHz, but the maximum operating frequency of OTFT (fT) circuits is still less than 1 MHz [13-

15]. The fT is defined as

W  CV g e I GS f m L T 2CCCCC 2 (   ) G GSO GDO GSI GDI (2.5) W eCV I GS L eVC GS CH 2 2 (CCLCCCH  P ) 2 ( CH  P )

where μe is a field-effect mobility without correction for contact resistance, CCH is the channel capacitance and CP is the parasitic overlap capacitance. Continuous progress has been made in the synthesis of organic semiconductors and dielectric materials to enhance the carrier mobility [4], but the microscopic mobility upper limits of organic molecular crystal is between 1 to 10 cm2/vs [16]. Shortening channel length (L) and reducing parasitic capacitance (CP) are obviously alternate methods to increase OTFT operating frequency for a given organic semiconductor, which will be described further in Chapter

1.3 APPLICATIONS

As mentioned earlier, substantial research effort in organic electronics is on the fabrication process on large, flexible substrates. Many different products could be implemented based on the unique properties of organic electronics. One such application

is an organic passive RFID tag. RFID technology uses wireless radio communications to uniquely identify objects or people [17]. RFID tags based on silicon ICs are widely used nowadays, but its fabrication cost is still high to limit its mass volume applications. A passive RFID tag does not have a power source included; instead, it has to generate its own power by receiving and rectifying an externally generated RF signal [17]. RFID tags have received considerable attention in recent years for their application toward printed organic transistors. Again, the primary driver for this consideration is cost. The performance of organic electronic devices, such as OTFT or organic diode, is insufficient for a complete RFID tag. But given its history of drastic performance improvements, we expect commercial organic RFID tags to be ready in the near future. In Chapter 2, I will describe a new method to increase the frequency performance of OTFTs.

Sensor and sensor network is another possible application for organic electronics.

Organic materials offer unique characteristics, such as tunability of electronic properties via chemical synthesis, compatibility with mechanically flexible substrates, low-cost manufacturing. These characteristics have prompted the application of organic materials and their devices in physical, chemical, and biological sensors [18]. Organic materials offer many advantages in comparison with their inorganic sensor. Disposable and flexible properties can satisfy our increasing needs for sensor. As one potential application, a flexible temperature sensor is demonstrated in Chapter 4. The new flexible temperature sensor is ideal for monitoring the temperature of human body, perishable foods or medicines.

1.4 MOTIVATION AND ORGANIZATION OF THIS DISSERTATION

If we review the historical development of silicon industry, there were several key factors for the success of semiconductor microelectronics in our everyday life. The first is device engineering. Transistor is a fundamental building block for all modern electronics.

Down-scaling of transistor has continuously improved electronic circuit performances such as operating frequency, integration density, power consumption and costs [6, 7]. The second was circuit design methodology based on computer aided design (CAD) software.

Accurate device modeling, simulation, and design with CAD software have enabled integration of more than a billion transistors into a single silicon chip today.

In case of organic electronics, development of high performance organic materials is definitely the first step for the successful realization and implementation of electronic applications. The next phase of development will be device engineering and integration of discrete devices into circuits and systems, which are the main topics of this dissertation.

Modern fabrication and device technology of silicon cannot be directly applied to organic electronics because of the fundamental difference of semiconductor materials and the sensitivity of organic materials to silicon fabrication processes [2]. Thus I focused on the development of an optimized architecture for a high performance OTFT and the establishment of a fabrication process compatible with organic materials. Also, a proper circuit design methodology based on CAD software can upgrade organic electronics by minimizing the design effort and maximizing the circuit and system performance. Here, I

optimized a circuit design methodology for OTFTs and explored approaches to deliver higher performance circuits and applications based upon this design methodology. The remainder of this dissertation is organized as follows.

In Chapter 2, I explored device engineering for OTFTs. New device architecture and fabrication methods to improve the OTFT characteristics were proposed. A short channel self-aligned OTFT architecture was implemented on a non-planer substrate. The self- aligned structure enabled accurate self-alignment between the electrodes with a pre- defined prism-structure dimension, thus reducing parasitic overlap capacitance. This enabled us to fabricate short channel devices with the use of photolithography and achieve twice higher maximum operation frequency (fT = 10.1 KHz) compared with conventional top-contact OTFT devices with same device dimensions. This imprinting- based OTFT structure is scalable for a large area application and is compatible with flexible substrates, and allows for creation of short-channel OTFTs without photolithographic patterning of electrodes.

In Chapter 3, circuit engineering was studied. A new OTFT circuit design methodology is proposed to enable accurate analysis and verification in the design stage.

Based upon this methodology, various topologies of digital circuits such as complimentary and unipolar OTFT circuits are demonstrated. Specifically, a unipolar p- type circuit based on bootstrap technique showed comparable characteristic to complementary type circuit. The p-type-only logic circuits with the bootstrap structure showed full swing output, higher voltage gain and noise margin than the conventional

diode-load structure. These logic circuits are potentially useful to implement digital processors in organic electronic applications with air-stability and low manufacturing cost.

Chapter 4 focuses on application engineering, specifically on the implementation of disposable and flexible organic electronic sensors. Wireless temperature sensor based on conductive filled polymer was demonstrated. The stability and reproducibility was improved by adding a plasticizer or employing a binary polymer system. Binary polymer system also gives adjustability of sensitive temperature for various applications. Passive

RFID antenna structure was integrated with the temperature sensor on a plastic substrate, which can enable low cost wireless thermal sensor.

CHAPTER 2: DEVICE ENGINEERING

OTFT is a fundamental building block for organic electronics. In this chapter, I focus

on the development of an optimized architecture for a high performance OTFT and the

establishment of an OTFT fabrication process compatible with organic materials.

2.1 BACKGROUND AND MOTIVATION

Organic transistors have attracted much attention for flexible, low cost and large area

electronics applications [2, 19-22]. Applications such as radio frequency identification

cards (RFIDs) [19], wearable electronics and sensor networks [20, 21] demand high

speed and low-voltage circuit operation based on high performance organic transistors.

Even with the recent progress in the synthesis of organic semiconductors and dielectric

materials [2], OTFT performance is still insufficient for the more demanding electronic

applications [19, 23-26]. OTFT performance can be further improved by device

engineering such as down scaling, which was the main driving forces for the

development of semiconductor electronics over the past few decades.

In this chapter, various methods to pattern channel electrodes that define channel

length will be reviewed. Also, several approaches to implement self-align structure will

be compared. Then, I demonstrated a new fabrication method that implements self-

aligned short channel OTFTs. The parasitic capacitance of OTFT was observed to be

significantly reduced using a simple micro-imprinting process on flexible substrates. The surface topology resulting from the imprinted prism-like structures enables accurate alignment of both the gate and source-drain electrodes. As a result, the parasitic overlap capacitance can be reduced and the maximum frequency of operation is doubled. The

Prism-OTFTs were applied to both p-type (pentacene) and n-type (C60) organic semiconductors to fabricate both types of OTFTs.

2.2 A REVIEW OF CHANNEL ELECTRODES PATTERNING

METHODS

2.2.1 Shadow Mask Patterning

A top-contact OTFT device structure is desirable to reduce contact resistance and maximize device performance. Top-contact devices are usually fabricated by sequential deposition of functional materials. Specifically, the organic semiconductor and metal electrodes are each sequentially deposited through shadow masks to define the active channel regions. A shadow mask is a thin slab of material in which apertures are created.

The shadow mask is usually made of ceramic or metallic materials but flexible, polymer-based shadow masks [27] can also be used. For the source-drain electrodes, the shadow mask is clamped to the substrate, and a layer of metal is evaporated. When the shadow mask is removed from the substrate, the resulting source and drain electrodes are

patterned on top of the organic. Figure 2.1 shows a photo of a metal shadow mask and a layer of metal patterned with the same shadow mask.

(a) (b)

Metal Deposition (c)

Shadow Mask

Organic semiconductor

Gate Insulator Substrate

Source Drain Organic semiconductor

Gate Insulator Substrate

Figure 2.1 (a) A photograph of a metal shadow mask, (b) patterned metal (Al and Au) layers with the shadow mask and (c) a schematic diagram of shadow mask process.

Top contact OTFTs with shadow mask patterning are relatively easy to fabricate, as no lithographic equipment is required. In addition to simple processing, top contact OTFTs

offer great flexibilities, such as in choosing dielectric surface pretreatments, and taking advantage of the atomically smooth dielectric substrate surface so that the morphology of a pentacene film remain undistorted. For these reasons, top contact OTFT structure with shadow mask process is widely used.

However, this method also has a few drawbacks. One major disadvantage is that the channel length is limited to above 25 μm unless special masks are used [28]. It should be noted that top contact OTFT have been fabricated with channel lengths down to 400 nm by using a micro-machined shadow mask [67]. However, the micromachining process is quite tedious, and the resulting shadow masks are both fragile and expensive; therefore, in practice, this method is not scalable. Another drawback of shadow mask-patterned devices is that it is not trivial to align the shadow mask to eventual pre-existing patterns on the substrate. Also, the shadow mask technology can only be used for patterning materials that are deposited by vacuum evaporation. Hence, patterning polymeric solutions is not possible using the shadow mask approach.

2.2.2 Photolithography

Smaller features can be readily patterned using photolithography, a well-developed technique for fabricating micro- or submicron inorganic semiconductor devices.

According to the 2011 International Technology Roadmap for Semiconductors (ITRS

2011), features as small as 20 nm can be patterned using photolithography [8].

Light Exposure

Photomask

Photoresist

Gate Insulator Substrate

Organic semiconductor Source Drain Gate Insulator Substrate

Figure 2.2 A schematic diagram of photolithography process.

Combining photolithography with lift-off provides an effective method for fabricating electrodes for OTFTs. Obviously, the lithographic process allows for easy scaling down of the channel length of OTFTs. Furthermore, aligning the photolithographic mask to a pre-existing pattern can be performed down to submicron accuracy. The main drawback is that the process requires some rather expensive equipment, making it an expensive process. In addition, the source and drain electrodes can rarely be patterned on top of the organic semiconductor when using photolithography. This is because the chemicals used

during the subsequent processing steps (i.e. etchants, developers, etc.) and photo exposure can cause either degradation [9] or delamination [10] of the organic semiconductor. Therefore, the source and drain electrodes are deposited and patterned prior to the semiconductor deposition. This type is the so called bottom contact OTFT, in which the source and drain contacts are underneath the organic semiconductor film. Thus photolithography process is not well-suited for fabricating low-cost organic electronic devices. Inexpensive and non-invasive processing technologies that are both physically and chemically compatible with organic materials need to be developed so as to lower fabrication costs and maximize device performances.

2.2.3 Nano-Imprinting Lithography (NIL)

Imprint lithography is being investigated as a potential next-generation patterning technique that has gained popularity for generating nanoscale features. For example, nano-imprint lithography has been accepted as the next generation lithography by ITRS since 2003. Imprint lithography provides a higher resolution and lower cost alternative for fabricating nanoscale electrical circuitry components as compared to photolithography. A typical nano-imprint lithography for OTFT [29, 30] is as follows:

First, a substrate is coated with a resist, which can either be a thermal plastic or a functional layer. The mold for imprinting is typically fabricated on a silicon or fused silica template using photolithography or e-beam lithography [31, 32]. In the case of using thermal plastic as a resistor, the substrate is heated above the glass transition

temperature of the thermal plastic and followed with imprinting by the mold with an applied pressure. Upon mold contact, the resist is cooled below its glass transition temperature, effectively “locking in” the shape of the mold, which is subsequently removed. It is important to note that nano imprinting is a physical deformation process, not an ink-stamping process.

While nano imprint lithography is a promising next-generation lithography technique to produce excellent feature resolution, several concerns still exist before the technique will have industrial implications. In particular, commercially-available molds, resists, and processes still need to be developed. Austin and coworkers demonstrated a OTFT fabrication process based on nano imprint lithography with channel lengths below 100 nm [30]. They have patterned polymer layer using nano imprint lithography to generate source and drain electrodes via a lift-off process. Other various methods to fabricate short channel OTFTs with nano imprinting lithography [24, 33] also have been reported, but are all based on a bottom-contact structure. Thus nano imprint lithography shares the same problems as photolithography for OTFT fabrications.

2.2.4 Vertical Channel Device Structure

Although traditional OTFTs have lateral channel direction, several different approaches have been reported by using vertical shaped OTFT [34-37]. In these cases, the channel length was defined by the thickness of a specific layer and not by the high resolution photo lithography process needed for lateral OTFT. These devices should have

enhanced DC performance and a better switching speed with a shorter channel length, because vertical dimension can be better controlled through film thickness. The common feature of all the reported device structures is that the source and drain are vertically stacked and are separated by the thickness of the semi-conducting or the insulating layer.

Stutzmann and coworkers produced a self-aligned Vertical channel polymer FET [30].

Their unique fabrication procedure is the use of a solid-state embossing method to produce the device. Embossing is a non-lithographic patterning technique capable of imprinting nano scale patterns into a polymer thin film. The process was performed with a micro cutting tool having sharp wedges that can penetrate into a multilayer of metal contacts and semiconductor films.

Another approach to reduce the channel length of OTFTs while maintaining the top contact structure is to use a vertical channel configuration [35-38] as shown in Figure 2.3.

Here, the vertical channel length is regulated through the height of a microstructure made by the well-developed photolithography. As illustrated in Figure 2.3, organic semiconductor channels are on the sidewalls. Therefore, accumulated charges flow perpendicularly to the substrate surface from source to drain electrodes. The main advantage of the vertical-channel OFET structure is the easy and scalable fabrication process used to define the short channel length by the height of the multi-columnar structure, without the necessity for photolithography [35-38]. Also, top-contact geometry can be applied to short-channel devices, which allow good electrode contacts. Although a shorter channel length can be realized with a top-contact structure, the gate electrode was

not patterned in the reported structure [35-38]. Therefore the whole channel electrode area contributes to the parasitic capacitance of OTFT, which can limit frequency performance of the OTFT. A dominant factor that affects the operation frequency especially for short channel OTFTs is the parasitic capacitance. The overlap capacitance can be reduced dramatically if a self-aligned OTFT process could be developed.

Metal Deposition

Substrate Insulator Gate

Organic Semiconductor Source Source

Drain

Substrate

Insulator Gate

Figure 2.3 A schematic diagram of a vertical-channel OTFT [35-38]

2.3 A REVIEW OF SELF-ALIGNED STRUCTURES

Overlap capacitance can constitute a significant fraction of the total gate capacitance in a device. Overlap capacitance is especially problematic because it represents additional load on the device performance without contributing to its transconductance. In addition, it increases as a fraction of the total capacitance for a given design rule as the channel length decreases. In a silicon-based MOSFET, source and drain regions are defined by ion implantation [7] with the gate electrode as a self-aligned mask. As a result, the overlap capacitance can be controlled more precisely and uniformly, which enables the silicon industry to scale down the device geometry following Moore‟s Law [7]. But in the case of OTFT, source and drain regions are not defined doping. Thus, the parasitic overlap capacitance should be controlled by accurate alignment and reducing the overlap margin allowed for source/drain alignment to the gate, which has limitations and variations.

ION doping (N+)

Gate Insulator Source (N+) Drain (N+)

Si Substrate (P-)

Figure 2.4 Self-aligned structure of a silicon-based MOSFET.

An alternative approach for layer alignment is to deposit a high optical density gate and use this gate as a mask to align the source/drain layer. This process is also known as a back-substrate exposure photolithography process [33, 39, 40]. Using this self- alignment method, the source-gate and drain-gate overlap can be minimized. But care should be taken to avoid leaving ungated material at the channel edge, as it can lead to significantly increase access resistance to the gated channel. The overlap distance can be managed by adjusting the dose delivered in the backside exposure step [39]. However, self-aligned processes based on back-substrate exposure photolithography suffer from the same compatibility problem with organic materials as the case of photolithography. Other approaches for self-aligned structure rely on the selective functionalization of self- assembled monolayer (SAM) [41, 42]. In this process, a hydrophobic SAM layer enables selective area dewetting and patterning of successive electrode layer. Although all of those methods are important and useful, none of these methods could yet implement a short-channel and self-aligned OTFTs with top contact structure.

2.4 EXPERIMENTAL

The silicon master molds were made from (100) wafers with a 300 nm thermally grown oxide, and patterned using photolithography. The oxide was used as a mask for potassium hydroxide (KOH) etching. The KOH etching was carried out at a controlled bath temperature of 70 ℃ to ensure etch uniformity. The etch rate was approximately 1

um min-1, characterized by Tencor Alphastep 500. The oxide was stripped using buffered hydrofluoric acid, followed by vapor deposition of tridecafluoro-1,1,2,2,-tetrahydrooctyl trichlorosilane (Gelest) to facilitate the release of the mold. A 20 wt.% polymethyl methacrylate (PMMA) (Aldrich, Mw=120000, Tg=114℃) solution with toluene was spin coated at 500 rpm on PET substrate and impressed with a house-made press (170℃, >50

Mpa). An aluminum 80nm layer for gate electrodes were thermally evaporated on the prepared substrate with a 55 tilt angle. n aluminum oxide 20nm was subsequently deposited by atomic layer deposition L process at T=60 using ambridge

Savannah 200. An octadecylphosphonic acid (OPA) self-assembled monolayer (SAM) layer was deposited by soaking on OPA solution (3 mM in ethanol). For the p-type and n- type organic semiconductor, pentacene (Sigma-Aldrich) and C60 (Alfa Aesar) film (~40 nm) was vacuum-deposited, respectively onto the above-prepared substrates held at 50ºC and a deposition rate of 0.2-0.3 Å s–1. Finally, gold electrodes 40nm for source and drain were deposited subsequently with 55 tilt angle.

2.5 FABRICATION PROCESS OF PRISM OTFT

Herein, I propose a new OTFT structure, PRISM OTFT. PRISM-OTFT can implement relatively short channel length without photolithography process. Also it has both self- aligned and top-contact structure, which was not possible to fabricate using previous methods as discussed earlier. This PRISM OTFT was implemented on a flexible substrate

by imprinting of a prism-like surface topology. The self-aligned structure enabled accurate alignment between the electrodes with a pre-defined prism-structure dimension, thus reducing parasitic overlap capacitance. The fabrication process for prism OTFT can be divided into 3 parts, namely the fabrication of master mold, imprinting, and OTFT layer depositions.

S/D (Au) Organic Semiconductor Gate (Al) Gate Insulator

PMMA PMMA

PET Substrate

Figure 2.5 Structure of PRISM OTFT

2.5.1 Fabrication of a Master Mold for Imprinting

Silicon is a perfect material for the realization of prism structure gratings if optical transparency is not required. Due to the well-established silicon industry, many etching methods with a wide variety of properties are available. For a prism-shaped master mold structures, standard photolithography and wet-etching processes were used for the fabrication process. The fabrication process of a master mold is shown in Figure 2.6. First, the silicon master molds were started from (100) wafers with a 300 nm thermally grown oxide. Two-dimensional line structures were transferred into silicon oxide layer by

standard photolithography process and wet etching with buffered hydrofluoric acid. After that, the patterned oxide layer served as a mask for potassium hydroxide (KOH) etching.

The KOH etching was carried out at a controlled bath temperature of 70˚C to ensure etch uniformity.

(a) SiO2 (300nm)

Silicon Wafer (100)

(b) SiO2

Silicon Wafer (100)

(d)

Silicon Wafer (100)

Figure 2.6 Fabrication of a silicon master mold. (a) A silicon (100) wafers with a 300 nm thermally grown oxide. (b) Patterning of a silicon oxide layer by standard photolithography process. (c) Silicon wet etching with potassium hydroxide (KOH) . (d) Stripping the remaining oxide layer using buffered hydrofluoric acid.

The anisotropic etching behavior in KOH solution was used to define the prism-shape.

Depending on the wafer orientation, the groove direction on the wafer and the etching conditions, different types of profiles of linear gratings can be produced. For the realization of a triangular profile, the etch windows of the line structures must be parallel to the (110)-directions on the wafer. Anisotropic etching of <111> direction of a silicon crystal is much slower than all other directions. This produces prism-shaped structures with 54.74˚ sidewall angles relative to the surface. The mask pattern of the grating presented in Figure 2.6(b) consists of multiple small spacing between relatively large windows. Etching produces V-shaped grooves with narrow plateaus in between. The resulting profile has an approximate triangular shape. The minimum value of the spacing depends on the precision of lithography (accuracy of orientation, minimum width of mask) and on the width of the grooves determining the etch time to arrive the V-shape and consequently the resulting under-etching. After the wet etching process, the oxide was stripped using buffered hydrofluoric acid.

2.5.2 Imprinting of PRISM Structures

Imprint technology using compression molding of thermoplastic polymers is a low cost mass production technology and has been around for several decades. Features with sizes greater than 1 mm have been routinely imprinted in plastics. Compact disk based on imprinting of polycarbonate is one example. In this process, imprinting is used to make

replicates of the master mold by compression molding. Before the imprinting process, the silicon master mold was treated by vapor deposition of tridecafluoro-1,1,2,2,- tetrahydrooctyl trichlorosilane (Gelest) to facilitate the release of the mold before imprinting. Polymethyl methacrylate (PMMA) was our primary resist. For uniform deposition of the resist, PMMA (Aldrich, Mw=120000, Tg=114 ˚C) solution was spin coated at 500 rpm on a polyethylene terephthalate (PET) substrate and imprinted with a home-made press heated to 170 ˚C with a pressure of 50 Mpa. We have tested several commercially available polymers, e.g. polystyrene, polyethylene, and polyvinyl alcohol, and PMMA showed the best mold release and fidelity of the replicated shapes as shown in Figure 2.7.

(a) (b) (c) (d)

Figure 2.7 Microscope image of imprinted PRISM patterns of (a) PMMA, (b) Polyethylene, (c) polystyrene, and (d) polyvinylalohol substrate.

This is because PMMA has a small thermal expansion and pressure shrinkage coefficient [31]. Another requirement of the resist material for imprinting is compatibility with OTFT fabrication process, which includes several depositions of different layers.

Thus the prism structure should withstand the thermal budget of deposition process.

Fortunately, the glass transition temperature of PMMA is higher than the maximum process temperature, which was about 80 ˚C.

Figure 2.8 Scheme of prism substrate fabrication process. (a) A Silicon master mode with prism-shape arrays. (b) PMMA deposition on PET substrate. (c) Imprinting. (d) Imprinted prism-like structures.

2.5.3 OTFT Fabrication on Prism Structures

OTFTs were prepared by depositing gate electrode, gate insulator, organic semiconductor and source-drain electrode layers on this prism substrate. First, an aluminum (80 nm) layer for gate electrodes was thermally evaporated on the prepared substrate at a 55 tilt angle. Since thermal evaporation gives directional deposition, it enables triangular gratings to serve as shadow masks if deposition is carried out with a proper tilt angle. In our experiment, the tilt angle should be very similar to that of the prism angle according to our estimation. A tilt angle over 60˚ resulted in short-circuit between channel electrodes; while a tilt angle less than 50˚ gave no overlap between the gate and source-drain electrodes. This results in an increases of the contact resistance due to the fact that organic semiconductor regions are not properly gated. An aluminum oxide

(20nm) was subsequently deposited by an atomic layer deposition (ALD) process at T=60

C using Cambridge Savannah 200. We selected aluminum oxide (AlOX) via an ALD process as a gate dielectric material to provide good thickness control, conformality, smooth and dense film on our non-planer substrate [43]. Also, AlOX has a relatively high dielectric constant εr=9.1), which enables low voltage operation of OTFTs. An octadecylphosphonic acid (OPA, CH3(CH2)17PO(OH)2) self-assembled monolayer (SAM) layer was deposited by soaking on OPA solution (3 mM in ethanol). SAM treatment is generally known to reduce interfacial trap states and to improve the film morphology and crystalline order of organic semiconductor layers[27].

(a) ~55

Gate (Al)

54.74 PMMA

PET Substrate

Organic (b) Semiconductor

PMMA

AlOX PET Substrate

S/D (Au) S/D (Au)

PMMA

PET Substrate

Figure 2.9 Scheme of prism-OTFT fabrication process. (a) Aluminum (gate electrodes) layer deposition with a tilt angle. (b) Gate insulator and organic semiconductor deposition. (c) Gold (source-drain electrodes) layer deposition with a tilt angle.

For the p-type and n-type organic semiconductors, both pentacene (Sigma-Aldrich) and

C60 (Alfa Aesar) films (~40 nm) were subsequently vacuum-deposited, onto the above- prepared substrates held at 50 ºC and a deposition rate of 0.2-0.3 Å s–1. For conformal deposition of the semiconductor layer throughout the prism structure, the substrate was continuously rotated during deposition. Finally, gold electrodes (40 nm for source and

drain were deposited subsequently with 55 tilt angle using the same method as for the gate electrodes (from the opposite direction). As shown in Figure 2.9(c), the channel length (~8 μm) was defined by the length of the one side of the triangle. It is important to point out that such a short channel (<10 μm was not defined by photolithography or micro-fabricated silicon stencil masks but by creating a surface topology followed by angle depositions. The imprinted prism substrate has a triangular cross-section with a small flat top and bottom area between shapes, which was designed for the minimum overlap between the gate and the source-drain electrodes. The top and bottom flat regions define the overlap area between gate and source-drain electrodes, which was 0.5 μm and

1.0 μm, respectively, in this case. The channel and self-aligned overlap length can be further decreased by changing the master mold design and process optimization.

2.6 CHARACTERISTICS OF PRISM OTFT

2.6.1 Fabrication Results

This prism-OTFT shares several merits with the vertical-OTFTs [35-38], such as top- contact structure, short channel length defined by the pre-designed structure on the substrate. On the contrary, the most significant difference is that prism-OTFT is a self- aligned structure with patterned gate electrodes. Also, imprinting is capable of producing sub-10 nm features over a large area in a low cost and high throughput manner, making it highly suitable for organic electronics [31].

(a) (b)

Figure 2.10 (a) Cross-sectional scanning electron microscope (SEM) image of pentacene prism-OTFT and (b) close-up of the channel region.

Figure 2.10 shows a cross-sectional scanning electron microscope (SEM) image of the pentacene transistor. A gold layer for source-drain electrodes was deposited on the top and right side of the prism structure. On the other hand, an aluminum layer for gate electrodes was deposited on the top and left sides. Thus, the transistor channel region is formed on the left side of the PRISM structure, while the source-drain electrodes are on the right side of the PRISM structure.

2.6.2 Frequency Characteristic of PRISM OTFTs

As shown in Figure 2.11, the proposed self-aligned structure reduces the parasitic overlap capacitance by 80% as compared to an unpatterned-gate structure commonly used for vertical-OTFTs and conventional top-contact OTFTs. The corresponding fT in

Figure 2.12 measured with a current-gain method [39] was 10.1 KHz, which was twice higher than the fT of unpatterned-gate structure (4.9 KHz) with the same geometry. Thus, this structure would permit OTFTs to minimize overlap capacitance with top-contact device structure, which can ultimately enable OTFTs to follow the Moore‟s law of silicon

MOSFET[7] with channel length scaling.

(a) 5

3 Unpatterned-gate Structure Patterned-Gate Structure 2

Capacitance(pF) 1

0 -4 -2 0 2 4 Voltage (V) (b) 10 Unpatterned-gate Structure 8 Patterned-gate Structure

Capacitance(pF) 2

0 -4 -2 0 2 4 Voltage (V)

Figure 2.11 Measured capacitance between gate and source-drain electrode of (a) metal- insulator-metal (MIM, Al-AlOx-Au) structure (W=100 μm , L=8 μm) and (b) pentacene OTFT with voltage bias (W=100 μm , L=8 μm).

f =4.9KHz T 10-7

(A) f =10.1KHz

PP T

10-8 I (unpatterned-gate) IN I (unpatterned-gate) OUT I (patterned-gate) IN I (patterned-gate) OUT 10-9 103 104 Frequency (Hz)

Figure 2.12 Frequency characteristics of of pentacene OTFTs (W=100 um, L=8 um).

2.6.3 DC Characteristics of Prism OTFT

The current-voltage characteristics were measured inside a nitrogen glovebox. Drain currents showed linearly increasing behavior with drain-source bias voltage (VDS) in the linear region for both p- and n-type transistors, which is an evidence for good ohmic electrode-semiconductor contact. Also, good saturation behaviors of drain currents without short channel effect were observed in both transistors because of the thin gate insulator (AlOx 20nm) with a high dielectric constant εr=9.1). For pentacene transistors, the charge carrier mobility ranges from 0.08 to 0.11 cm2/Vs, the on-off ratio was around

5*105, and the average threshold voltage was -2.5V. C60 transistors had a mobility range between 0.05~0.09 cm2/Vs, 1.5x104 on-off ratio, and 0.4V average threshold voltage. The mobility and other transistor DC characteristics are comparable to the vertical-OTFTs

[35-38], even though they are a little lower than the typical top-contact OTFTs. This may be due to the less smooth substrate surface we have compared to the typical atomically flat Si substrates. The performances of OTFTs on the less flat glass or plastic substrate

[19, 20, 22] are comparable to what we obtained here. Figure 2.13 shows the current- voltage characteristics of the pentacene and C60 transistors, where W is 100 μm and L is

8 μm.

0.0 1.0 10-6 (a) -2 V (b) 10-7 -3 V 0.8 ) 10-8 -0.1 1/2

-4 V A

-9 A)

 0.6 A)

10 

(



(

1/2 -10 ) 10 DS

DS 0.4

I DS -0.2 VGS = -5 V -11 -I

(-I 10 0.2 10-12 -0.3 0.0 10-13 -5 -4 -3 -2 -1 0 -7 -6 -5 -4 -3 -2 -1 0

VDS (V) VGS (V)

VGS = 5 V -7 10 0.8 0.2 -8

10 1/2

4 V 0.6 A)

-9 



10 (

(A)

( 1/2

DS 0.4 3 V ) I -10 0.1 DS

I 10

DS (I -11 0.2 2 V 10

0.0 -12 10 0.0 0 1 2 3 4 5 -1 0 1 2 3 4 5 6 7 VDS (V) VGS (V) Figure 2.13 DC current-voltage characteristics of prism OTFTs. (a) Output and (b) transfer characteristics of a p-channel (pentacene) OTFT. (c) Output and (d) transfer characteristics of a n-channel (C60) OTFT.

2.7 SUMMARY

I have demonstrated the fabrication of short channel and self-aligned OTFTs on a flexible substrate by imprinting of a prism-like surface topology. The self-aligned structure enabled accurate alignment between the electrodes with a pre-defined prism- structure dimension, thus reducing parasitic overlap capacitance by 80% as compared to conventional top-contact OTFT structures. This enabled us to achieve a two-fold fT (10.1

KHz) as compared to conventional top-contact OTFT devices with the same device geometry. This imprinting technique is easily scalable for large area applications and is compatible with flexible substrates. This allows for the creation of short-channel OTFTs without photolithographic patterning of electrodes.

CHAPTER 3: CIRCUIT ENGINEERING

In Chapter 2, we have discussed the device engineering of organic thin film transistors

to improve the frequency performance and current capability. The next step of

development is an integration of OTFTs into circuits and systems. A proper circuit design

methodology can upgrade organic electronics by minimizing the design effort and

maximizing the circuit and system performance. In this chapter, I optimized a circuit

design methodology based on OTFTs and explore approaches to deliver higher

performance circuits and applications with this design methodology.

3.1 BACKGROUND AND MOTIVATION

OTFT has a low thermal processing condition that enables fabrication on flexible

substrate. OTFTs can also be fabricated with relatively simple processes which can

reduce processing cost. Even though the performance of OTFTs is not as high as Si

MOSFET, they are adequate for a specific range of applications such as RFID, e-paper,

flexible displays and sensors etc. Most OTFT-based applications can be implemented by

digital circuits, where some kind of elementary computation is performed. Although

many OTFT circuits already have been presented to show the possibility of organic

electronics applications [13, 14, 19, 44, 45], they were not based on a systematic design

approaches. In this chapter, I will describe a detail about an OTFT circuit design methodology, together with circuit topologies, for their use in digital logic circuits based on organic materials.

3.2 DESIGN METHODOLOGY FOR OTFT CIRCUITS

Multiple steps are needed to implement silicon integrated circuits [46] as illustrated in

Figure 3.1. In a design perspective, OTFT circuits need similar steps to implement various functions. However, each step should be optimized for OTFTs, because it has different characteristics and fabrication process compared with silicon MOSFETs. The first step is to define a circuit specification including inputs and outputs, which is usually set by the application requirements or by the limitation of the device performance based on a specific process technology. The second step is schematic drawing. This step is to represent the circuit with electrical symbols and also to be used as an input to analyze the circuit by computer simulations. The analysis and design of integrated circuits depends heavily on the utilization of suitable models for integrated-circuit components. Circuit simulation is only as accurate as the model used. Thus an OTFT model that can exactly describe several non-linear characteristic is essential for accurate simulation.

Circuit Specifications (Input & Output)

Schematic Drawing & Hand Ananlysis

Circuit Simulation

No Meet Spec.?

Yes

Physical Layout

No Verifications

Yes

Fabrication

TeTsetsint ga nadn dE vEavluaalutaiotinon

No No Meet Spec.?

Yes

Production

Figure 3.1 Flow chart for a design process of integrated circuits [46].

Once the detailed understanding and modeling of OTFT are done, this model can be then extensively used for analysis and design of OTFT circuits. Schematic editor and

Simulation Program with Integrated Circuit Emphasis (SPICE) simulation are typically used in this step. A Schematic editor is a tool for schematic capture of electrical circuits.

Simulating the circuit with SPICE is the industry-standard way to verify circuit operation at the transistor level before the fabrication of an integrated circuit. Further, the high costs of masks for patterning and other manufacturing prerequisites make it essential to optimize the circuit design before the integrated circuit is built. Also, circuit designers can obtain more information about the circuit characteristics affected by component variation and obtain the optimum design parameters with SPICE simulations.

Figure 3.2 An example of schematic design (a NAND gate).

A next step is to design a physical layout. This step is to create an accurate physical representation of circuit schematics that conforms to constraints imposed by the manufacturing process, the design flow, and the performance requirements shown to be feasible by simulation. OTFT circuits are made by multiple-step processes that result in transistors and wires being constructed and connected on a substrate. Layout design involves drawing various components (transistor or capacitor), and also wires for connecting the components. Thus, the layout can be thought of as the physical representation of the circuit.

Figure 3.3 An example of layout design (a NAND gate).

Once the implementation of the layout is complete, it is followed by a verification step.

This is not a trivial task and is a very important step. There are many possible failure mechanisms in integrated circuit design, and fixing errors after commencement of fabrication require a considerable cost and time. The verification step can be divided into two stages. First is the design rule check (DRC), which is to check the requirements of fabrication process rules. These design rules define the limits of a manufacturable design, such as width and space rules. Second is layout versus schematic (LVS). The schematic is a reference circuit and the layout is cross-checked to ensure the transistor‟s size and connectivity. Since there are various processes and architectures for OTFT, this verification tool was thus customized for the top-contact shadow mask OTFT process.

Finally, masks for patterning process are manufactured as the verified design and OTFT circuits were fabricated with the masks.

3.3 EXPERIMENTAL

Complementary OTFTs were built on a commercially available perfluoroalkoxy fluorocarbon (PFA) substrate (DuPont, thickness about 125μm . Prior to usage, the PFA film was baked at 100 °C for 5 hours in a vacuum oven for pre-compaction. The OTFTs were fabricated in the bottom gate top-contact architecture. First, an aluminum (80nm) layer for gate electrodes was thermally evaporated on the prepared substrate. An aluminum oxide (20nm) was subsequently deposited by the atomic layer deposition

(ALD) process at T = 60 C (Cambridge Savannah 200), and an OPA SAM layer was subsequently deposited by soaking on OPA solution (3 mM in ethanol). C60 (40nm, Alfa

Aesar) and pentacene (40nm, Sigma-Aldrich) were deposited at a rate of 0.2 ~ 0.3Å /s, respectively. Finally, top-contact Au source/drain electrodes (50 nm thick) for both p- channel and n-channel OFETs were deposited at a rate of 0.5 Å /s.

Unipolar OTFTs were also built on a PFA substrate. The first fabrication step was to deposit Al film patterns (70 nm thick) in vacuum as the gate electrodes and interconnections using a shadow mask. For the gate insulator, poly vinyl alcohol (M.W.

31000, 5 wt% in water) with 0.8 wt% of Ammonium dichromate as the crosslinker was deposited by spin-coating and cross-linked for 10 minutes with a UV lamp (250 nm) through a shadow mask. The shadow mask was designed to expose UV except for the via hole area. Thus gate insulator layer in the via hole area is not crosslinked and will be removed during the developing step. Prior processes [19, 47, 48] all required at least one additional photolithography step to pattern the gate dielectric for contact, but the approach described here does not require an extra step. The thickness of the PVA film was ~150 nm. Next, the UV exposed pattern was developed using de-ionized water, followed by baking for 1 hour at 100 ºC to remove the residual water. A pentacene

(Sigma-Aldrich) film (~40 nm) was vacuum-deposited onto the above-prepared substrates held at 60ºC and at a deposition rate of 0.2-0.3 Å s–1. Gold electrodes (40 nm) and interconnects were deposited subsequently through a shadow mask.

3.4 A CIRCUIT SIMULATION MODEL FOR OTFT

3.4.1 The Non-ideal Characteristics of OTFT

OTFTs, at a first glance, behave like Si MOSFETs even though they are composed of completely different materials and device structure. One can distinguish between a linear and a saturation regime and there is a threshold voltage that separates the on and off regime. This is because the basic structure of OTFT is based on metal-insulator- semiconductor (MIS) capacitor system, which is the same as silicon MOSFET. Hence, the square-law model of MOSFET is generally used to describe the electrical behavior of

OTFT. But there are some important differences between OTFTs and Si MOSFETs.

First, charge transport physics in disordered organic semiconductors [2] are quite different from those of crystalline Si. In organic semiconductors, the charge transport takes place within and between molecules, and through grains. The efficiency of the intermolecular or inter-grain conduction process strongly depends on the molecular arranges respect to each other. Thus films made of different deposition methods may present different transport characteristics. Due to the disorders, the energy state can be thought as relatively localized as compared to single crystalline semiconductors. These localized states affect the threshold voltage (VTH), field effect mobility, and leakage current.

VTH in Si MOSFET is defined as the gate to source voltage at the threshold of strong inversion. The transfer curve of MOSFET quickly changes from exponential to linear around VTH. Due to the absence of inversion in OTFTs, no clear definition of VTH is given for OTFT. It is instead considered simply as a fit parameter and the transition around this point is more gradual due to the localized states in the OTFTs. This effect cause gradual current change from exponential to linear with gate bias, which can be incorporated in OTFT model through the bias-dependent field effect mobility (Ueff) [49].

A typical Ueff of OTFT shows voltage dependence [50] as shown in Figure 3.4, and it is quite different from Si MOSFET.

Second, some non-ideal characteristics are originated from the structural difference between OTFT and Si MOSFET. Contact resistance and leakage current are good examples. P-type MOSFET is usually fabricated in an n-type doped Si substrate. The source and drain contacts of MOSFET are realized by ion implanting into the Si substrate, forming a highly doped p+ region in the substrate. When the transistor is turned on, an inversion layer of holes is formed under the gate dielectric, and holes can be easily injected from the source into the channel. When the transistor is off, the p-n diode is reversely biased between the channel and the source-drain region. Thus only a small p-n diode leakage current can flow across the channel, and different MOSFETs are isolated by reverse biased junctions.

0.6

0.5

Average /Vs)

2 0.4 Standard Deviation 0.3

0.2 Mobility (cm

0.1

0 -5 -4 -3 -2 -1 V (V) GS

Figure 3.4 A gate bias dependency of p-type (pentacene) OTFT mobility.

Unlike Si MOSFETs, OTFTs are operated in an accumulation regime and there‟s no p- n junction that can block channel leakage current. Also, source-drain regions are not formed by doping but by a metal electrode as a source-drain electrode. Thus contact resistance of OTFT is not as good as MOSFET, and is strongly dependent on the work function difference of organic semiconductor and metal electrode. All of these characteristics of OTFTs have actually much more similarity with amorphous or polycrystalline silicon thin film transistors, rather to single crystalline Si MOSFET. A poly-Si TFT also has disordered localized states and grain boundaries. Also, its device structures are more similar. Thus a circuit model of poly-silicon TFT [49] that is available in commercial SPICE software was adapted here to accurately describe OTFT characteristics.

3.4.2 Device Model for OTFTs

An OTFT SPICE model was developed based on the Rensselaer Polytechnic Institute

(RPI) poly-Si TFT model [49, 51]. This semi-empirical, physics-based model takes into account the bias dependent field-effect mobility and the deep localized states [49, 51].

OTFTs with top-contact bottom-gate structure were used in this study and OTFT SPICE parameters were extracted from the experimental data derived from these devices. SPICE simulation tool was then used to simulate the OTFT characteristics. The RPI poly-Si TFT model, coupled with appropriate OTFT SPICE parameters, can reproduce our measured device characteristics very well, except for the gate leakage current. The gate leakage current can be ignored in conventional silicon MOSFETs because thermal SiO2 is an excellent insulator. However, this is not the case with OTFTs, since thermal SiO2 is not an option for the gate dielectric.

Other organic or inorganic gate dielectrics are usually not a good insulator as the thermal SiO2. Also, relatively thin gate dielectric layer is often used for lower voltage operation [15], and the gate leakage currents can be significant. Indeed, the off-current is not always dominated by drain-to-source leakage, but rather by drain-to-gate leakage. If gate leakage is significant, it should be considered at the design step by incorporating gate leakage model into the transistor model. Thus additional gate leakage model was added to the RPI poly-Si TFT model as shown in Figure 3.5. The gate leakage model is composed of a DC bias and a diode, which represent work function difference and bias

dependent gate leakage current. This OTFT model is implemented in SPICE, and simulation results compared with measured data are shown Figure 3.6 to 3.8. Besides DC characteristics, the capacitance associated with OTFT should also be taken into account to predict the AC behavior. The associated capacitance was extracted from the measured

C-V curves of OTFTs and compared with the obtained simulation data. As shown in the

Figures 3.6 to 3.8, this OTFT model can accurately describe the I-V and C-V characteristics of the bottom gate top-contact OTFTs which are described in section 3.3.

Also, implementation of these models into the circuit simulator will then enable efficient design and simulation.

Gate

RGS RGD RDX RSX

VBGS Cgs C IDS gd VBGD Source Drain

RS RD

PRI TFT Model

Figure 3.5 Equivalent circuit diagram of an OTFT model.

(a) (b) -5 10 0 -6 Measured 10 Simulation 10-7 10-8 -1

(A) -9

10 A)



DS I -10 (

10 DS I -11 -2 Measured 10 Simulation 10-12 -5 -4 -3 -2 -1 0 -5 -4 -3 -2 -1 0 V (V) V (V) DS GS

Figure 3.6 Comparison of measured (symbol) vs. modeled (curves) drain current characteristics for a p-channel (pentacene) OTFT with W/L = 5000 μm/100 μm (a) transfer characteristic, (b) output characteristics.

(a) (b) 10-6 3 Measured -7 Measured Simulation 10 Simulation 10-8 2

-9 A)

 (A)

(

DS I

-10 DS 10 I 1

10-11

10-12 0 0 1 2 3 4 5 0 1 2 3 4 5 V (V) V (V) GS DS

Figure 3.7 Comparison of measured (symbol) vs. modeled (curves) drain current characteristics for an n-channel (C60) OTFT with W/L = 8 μ/100 μ (a) transfer characteristic, (b) output characteristics.

8 C (Measured) G 6 C (Simulation)

Capacitance(pF) 2

0 -4 -2 0 2 4 V (V) G

Figure 3.8 Comparison of measured (symbol) vs. modeled (curves) drain current characteristics for an p-channel (pentacene) OTFT with W/L = 8 μ/100 μ.

3.5 COMPLEMENTARY OTFT CIRCUITS

After verifying that the proposed OTFT model base on RPI TFT model is suitable for describing OTFT characteristics, next I use this model to design a complementary OTFT circuit, consisting of p- and n-channel transistors, in this section.

3.5.1 Complementary Inverter

One of the best known digital circuits is an inverter [46]. Despite the fact that it consists of only two transistors, an inverter is the most important building block in digital logic circuits. Indeed, more complicated logic blocks, such as the NAND and NOR gates, can be easily expanded from the basic inverter. In addition, the inverter itself can be used as logic NOT gate. There are several kinds of inverter architectures based on the

available transistor types and their required performance [15, 19, 52]. The complementary type inverter uses both an n-type and a p-type transistor, which is known to have merits such as low power and high noise margin when compared to unipolar types, which use only one type of transistors.

(a) VDD (b) VDD

RP P-channel VIN VIN VOUT VOUT N-channel N-channel

GND GND

Figure 3.9 Complementary inverter. (a) Circuit diagram and (b) simplified circuit model.

A complementary inverter consists of a pull-up p-type transistor and a pull-down n- type transistor as shown in Figure 3.9. The operation of a complementary inverter can be understood from a simplified circuit model. In digital circuit, a transistor can be simply thought as a combination of a switch and a resistor. When VIN is higher than VDD-VTHP, the n-type OTFT is on, while the p-type OTFT is off. A conductive path is formed between the output node and the ground node, resulting in a low output voltage. On the other hand, when the input is lower than VTHN, the p-type OTFT is on and the n-type

OTFT is off. A conductive path between the supply voltage (VDD) and the output

voltage (VOUT), leads to a high output voltage. When the input is between VTHN and VDD-

VTHP, both switches are on and the output voltage is determined by the ratio of p and n channel resistance.

(a) 5

3 nw:pw=20:1

nw:pw=20:3

OUT nw:pw=2:1 V 2 nw:pw=1:1 nw:pw=1:2 1 nw:pw=3:20 nw:pw=1:20 0 0 1 2 3 4 5 V IN

(b) 2.5 30

DC Gain DC

2.0 10 NoiseMargin (V)

0 0.1 1 10 OTFT size ratio (nw/pw)

Figure 3.10 SPICE simulation results of (a) transfer curves with various transistor size ratio (SPICE simulation) and (b) noise margin if a complementary inverter.

The switching performance of an inverter can be characterized by noise margin and signal gain. Noise margin represents the tolerance of the circuit to noisy inputs without

error. The value of noise margin should be as large as possible so as to minimize error rate in real applications. Noise margin can be calculated by the area embedded within the transfer curve loop. DC gain is defined by dVout/dVin and a higher gain in the transition region is more desirable. These inverter characteristics are affected by transistor dimensions, thus circuit design needs to include proper sizing of individual transistors. As shown in Figure 3.10, noise margin and DC gain are maximized at the 1:1 ratio of Wn/Ln to Wp/Lp. Also, switching threshold voltage was VDD/2 and switching curve was almost symmetric at this ratio.

3.5.2 Electrical Measurement of Complementary Inverter

Figure 3.11 Photograph of complementary inverters under bending.

Photographic images of the complementary inverters on the flexible substrate are shown in Figure 3.11. The electrical measurements were performed in a N2-filled

glovebox (O2, H2O < 0.1 ppm) at atmospheric pressure (1 atm). A probe station was employed to contact the inverter with external measurement equipment. As shown in the circuit diagram in Figure 3.10(a), a power supply (VDD) was applied to the source of the p-type OTFT and ground (GND) was applied to the source of the n-type OTFT.

5 (a) 4

(V)

OUT V 1

0 0 1 2 3 4 5 V (V) IN

(b) 25

20 IN

/dV 15

OUT

5 Gain dV :

0 0 1 2 3 4 5 V (V) IN

Figure 3.12 (a) Voltage transfer curve (line with symbol) and noise margin window and (d) DC gain. All measurement was carried out inside a nitrogen glovebox.

A measured voltage transfer characteristic (VTC) of complementary inverter is illustrated in Figure 3.12, which shows the output voltage (VOUT) as a function of the

input voltage (VIN). The performance between the p- and n-type OTFTs matched up very well against the simulation result, which resulted in a symmetric voltage transfer curve, a maximized noise margin of 1.81 V, and a DC gain of 23 in 5 V power supply (Figure

3.12). Noise margin was 1.81 V, which is 72% of the maximum theoretical value. This value is much higher than the typical organic unipolar inverters [19, 22, 28, 53].

As the results indicated, our complementary inverter on a flexible substrate showed maximized a noise margin and a high DC gain at 5V power supply. However, there are several difficulties related to the poor air stability of most n-type transistors. Also, there are cost and yield issues related to the need for patterning the p- and n-type semiconductors separately. N-type organic semiconductors in general have lower mobility or poor air stability compared to p-type transistors. The best reported air-stable n-type OTFTs [6] still have a much lower mobility compared to that of typical p-type

OTFT based on pentacene. An encapsulation technique can be used to extend the lifetime of the n-type OTFTs, but it is challenging and needs additional processing steps.

3.6 UNIPOLAR TYPE INVERTER

Despite the superior DC characteristics of complementary OTFT circuits, the majority of flexible applications in the literature have actually utilized unipolar OTFT circuits[13,

14, 19, 23, 25, 44, 54]. Unipolar circuits based on p-type OTFT are usually more stable and cheaper to fabricate as compared to complementary type circuit. However, they suffer from poor circuit performances such as reduced output voltage swings and a lower

voltage gain. If the unipolar circuit performances can be improved by circuit topologies, unipolar type circuits would be better suited for organic electronics.

3.6.1 Conventional Unipolar Circuits

A diode-load inverter is the most well-known unipolar circuit. It is composed of one driving transistor (TD) and a diode-connected load transistor (TL), as shown in Fig. 3.14

(a). Usually, a negative power supply VSS is required for p-type-only circuits, since a p- type transistor is “on” only when VGS (the gate source voltage) is more negative than VTH

(threshold voltage). If the driving transistor is turned on by applying a negative voltage to the input port (IN), the diode-connected load transistor is also “on”. Thus, there is a static current and voltage drop across the load transistor. When the driving transistor is “off”, the load transistor pulls down the output voltage. But no further pull-down occurs when the output voltage reaches a magnitude of the threshold voltage above VSS because the load transistor is turned “off”. Thus, the output voltage cannot be pulled down all the way to the VSS level. In order to have a sufficient noise margin in digital circuits, output swing and voltage gain should be maximized.

Another type of unipolar inverter is called as zero-VGS load inverter. The load transistor is a depletion type which is normally-on with zero VGS. As shown in Figure

3.14(b), the gate of the load transistor is connected to its source. This configuration lead to a bigger output swing and noise margin than diode-load type, because the load current is limited and does not require threshold voltage drop. However, different threshold

voltage of load transistor is required, this additional processes such as dual gate metal with different work function [8] or back gate biasing [11] is required. Also, the noise margin is still limited by asymmetric transfer characteristic [3], because zero-VGS load transistor always operates in off-current region.

In summary, both diode-load and zero-VGS inverters have their advantages and disadvantages. The zero-VGS inverter is relatively slow, as the pull-down current through the load transistor is limited. In contrast, the diode-load transistor in the enhancement-load architecture is able to draw more current, which makes it faster. On the other hand, the gain in this type of inverter is limited. Hence, the noise margin is limited, which makes it a fast but not very robust architecture.

(a) GND (b) GND

IN TD IN TD OUT OUT

TL VSS VSS

Figure 3.13 Unipolar p-type inverters. (a) Diode-load inverter and (b) depletion-load inverter.

3.6.2 Bootstrap Unipolar Digital Circuits

Bootstrap is a analog circuit technique that utilize charge storage characteristics of a capacitor. The bootstrap circuit usually uses a coupling capacitor to drive a signal line to greater than the supply voltage. This technique was employed to unipolar p-type OTFT circuits to extend the output swing. Figure 3.14 shows a p-type inverter with bootstrap technique [14].

GND

IN TD

CB X OUT

TB TL

VSS

Figure 3.14 A circuit diagram of a bootstrap inverter.

Initial voltage of node X is set to VSS-VTH by the biasing diode and dynamically boosted by capacitive coupling with the output voltage through capacitor CB. Capacitor boosting RB, and minimum voltage of node X (VX, MIN) can be calculated as

CCB gs_ TL RB  (3.1) CCCCB gs___ TL  gd TL  gs TB

VVVRVVX, MIN()() SS  TH  B SS  OH (3.2)

(a) 6 6

5 5

(V)

U 4 O

V 4 3 40 1 3 R (Width Ratio) 0.8 W 20 0.6 R (Boosting Ratio) 0 0.4 B

(b)

2 2 1.5 1.5 1 1

0.5 Noise Margin (V) Noise Margin 0 0.5 60 40 1 0 0.8 20 R (Width Ratio) 0.6 W R (Boosting Ratio) 0 0.4 B

Figure 3.15 SPICE simulation result of (a) peak-to-peak output swing (b) noise margin of bootstrapped inverter.

It is clear that the voltage on node X can become lower than VSS+VTH with bootstrapping if the second term is bigger than VTH, thus VOL can be extended to VSS.

VOH is the maximum output voltage level which is determined by voltage divide ratio between TD and TL. Thus output swing level and noise margin can be maximized by design optimization with RB and RW (RW=WTD/WTL). Circuit simulations for design optimization were carried out using the circuit simulation, and the results are shown in

Figure 3.15. As RB approaches “1”, both output swing and noise margin can be improved; however both the capacitor area and initial set-up time should be considered in a practical

design. Boosting capacitor size does not directly affect the output transient response, because capacitor is coupled to other parasitic capacitance. Hence, we chose RB=0.9 and

RW=10 as an optimum design point to get a maximum noise margin and a full output swing.

(a) GND (b)

A B A B OUT 0 0 1 VOUT T1 0 1 1 1 0 1 1 1 0

VCC VCC

Figure 3.16 (a) Bootstrap NAND circuit and (b) truth table.

(a) GND (b) A A B OUT B 0 0 1

VOUT 0 1 0 T1 1 0 0 1 1 0

VCC VCC

Figure 3.17 (a) Bootstrap NOR circuit and (b) truth table.

This bootstrap structure also can be extended to various logic circuits such as a NAND or NOR gate, shown in Figure 3.16 and 3.17. NAND and NOR gates are basic elements of digital logic circuits and used to make a decision between different signals. The

“N N ” function OUT = “0” is produced when both IN1 and IN2 are both “1.” The requirement for both inputs to be “1” is achieved by connecting the two P-type OTFT in parallel. The “NOR” function is also achieved by connection the two p-type OTFT in series.

3.6.3 Fabrication of Unipolar Digital Circuits

The fabrication process of unipolar p-type OTFT is similar to the previous complementary inverter, except for the n-channel organic semiconductor deposition.

However, interconnection becomes more complicated as the complexity of circuit increases. In OTFT process, there already exist two metal layers (i.e. gate and s/d) that can be used as interconnects. The remaining requirements are patterning those metal layers for wiring and connecting through via holes. There were several reports in patterning the insulator for the interconnection via in OTFT process. The most common method is using photolithography and dry-etching, but this method is not compatible to this shadow mask process. Another method is using laser to remove insulator in the via hole area, which is again impractical for a large scale production.

In this work, selective crosslinking of gate insulator was employed to pattern via holes.

The first fabrication step was to deposit Al film patterns (70 nm thick) in vacuum as the gate electrodes and interconnections using a shadow mask. For the gate insulator, poly vinyl alcohol was deposited by spin-coating and cross-linked with a UV light through a shadow mask. The shadow mask was designed to expose UV except for the via hole area.

Thus gate insulator layer in the via hole area is not crosslinked and will be removed during the developing step.

(a) Pentacene(40nm)

Au(50nm) PVA(150nm) Al(70nm) FPA(125um)

Transistor Via Capacitor Via

(b)

Figure 3.18 (a) Cross section of transistor and capacitor (b) Photograph of circuits on the flexible substrate.

Prior processes [19, 47, 48] all required at least one additional photolithography step to pattern the gate dielectric for contact, but the approach described here does not require an extra step. PV has a higher dielectric constant εr = 8.4) than most other organic dielectric materials, which enables low voltage operation [55]. A pentacene was vacuum- deposited onto the above-prepared substrates. Gold electrodes and interconnects were deposited subsequently through a shadow mask. Capacitors in the circuits were formed as a metal/insulator/metal (Al/PVA/Au) structure during the above processes without

additional steps. The capacitance and leakage current per unit area were measured to be

49.0 to 49.6 nF/cm2 and 0.1 to 0.4 μ /cm2, respectively.

3.6.4 Electrical Characterizations of Unipolar Digital Circuits

In this work, the fabricated transistor was designed with 100 μm minimum channel length and 50 μm gate to source/drain overlap margin so that top contact devices reliably can be made using shadow masks. Fig. 3.19 shows current-voltage characteristics of a typical pentacene transistor with W/L = 5000 μm/100 μm. The average mobility at the gate bias of -5 V was 0.48 cm2/Vs and the average threshold voltage was -2.59V with standard deviation of 0.37 V in 10 samples.

Table 3.1 Inverter output characteristics.

Quantity Diode-load Inverter Boostraped Inverter Voltage gain 3.1 (σ=0.38) 14.1 (σ=1.55) Noise margin 0.48 V (σ=0.03 V) 1.49 V (σ=0.17 V) Signal delay 48ms (σ=12 ms) 110 ms (σ=21 ms) Output swing 3.05 V (σ=0.11 V) 5.87 V (σ=0.06 V) Value is average of 10 working samples and σ is standard deviation.

Before electrical measurements, all circuits were subjected to a bending test with a 5 mm radius of curvature for 1 min for 5 cycles to determine their mechanical and

electrical stability against repeated bending. Since both the current source and sink capability of OTFT circuits are limited, the circuit output cannot be directly connected to the oscilloscope used to measure the output signals. Thus, a unit gain buffer circuit with an operational amplifier was employed between the OTFT circuits and oscilloscope. The input signals are supplied by the function generator and power supplies.

(a) 4 (b) 1E-5 0.0 VGS=3V

] -2.0 3 1/2 1E-6

A -4.0



[ [A]

1E-7 [ -6.0 VGS=4V

1/2

DS DS I -8.0 I VGS=5V 1 1E-8 -10.0

0 1E-9 -12.0 -5 -4 -3 -2 -1 0 -5 -4 -3 -2 -1 0 VGS [V] VDS [V]

Figure 3.19 (a) Transfer characteristic and (b) output characteristics of a typical pentacene OTFT (W/L = 5000 μm/100 μm).

Power Supply Unit Device under Test Gain Oscilloscope (OTFT circuits) Function Buffer Generator

Figure 3.20 Measurement configuration of OTFT circuits.

0 0

-2 -2 VOUT [V] -4 VOUT [V] -4

-6 -6 -6 -4 -2 0 -6 -4 -2 0 VIN [V] VIN [V]

Figure 3.21 Voltage transfer characteristic (line) and noise margin window of (a) a diode load p-type inverter, (b) bootstrap p-type inverter.

0 INPUT 0 INPUT OUTPUT OUTPUT -2 -2

-4 -4

OUTPUT[V] OUTPUT[V]

-6 -6 0 1 2 0 1 2 Time [S] Time [S]

Figure 3.22 Measured typical transient output waveforms of (a) a diode load p-type inverter, (b) bootstrap p-type inverter.

10 out of 12 total samples showed valid output swing and the results are summarized

Table 1. As expected from the simulation result, the bootstrap inverter output showed extended output swing and 3 times larger noise margin than diode-load inverter as shown in Figure 3.21. These results were comparable to the previous complementary type

inverter. Also, Figure 3.22 showed transient response of bootstrap inverter with extended output swing as compared to conventional diode-load inverter. The only drawback of the bootstrap inverter was signal delay, which is twice larger than the diode-load structure.

This delay can be explained by extended output swing and bootstrap delay. Bootstrap

NAND gate circuit output also showed full swing and stable logic operation as shown in

Fig. 3.23.

Figure 3.23 Measured transient waveforms of a bootstrap NAND gate.

3.7 SUMMARY

In this chapter, I have demonstrated a proper circuit design methodology can upgrade organic electronics by minimizing the design effort and maximizing the circuit performance. First, I proposed an OTFT circuit design methodology that enables accurate

analysis and verification in the design stage. Based upon this methodology, I demonstrated various topologies of digital circuits, such as complimentary and unipolar

OTFT circuits. In specific, a unipolar p-type circuit based on bootstrap technique showed comparable characteristic to complementary type circuit. With this bootstrap structure, the p-type-only logic circuit showed full swing output, higher voltage gain and noise margin than the conventional diode-load structure. In addition, gate insulator process with PVA and UV crosslinker enabled low voltage operation and patterning of gate dielectric layer for interconnection without any photolithography step. These logic circuits are potentially useful to implement digital processors in organic electronic applications with air-stability and low manufacturing cost.

CHAPTER 4: APPLICATION

ENGINEERING (A FLEXIBLE

WIRELESS THERMAL SENSOR)

In the previous chapters, I developed new organic device architecture, fabrication process, circuit simulation models and circuit topologies, covering most of the challenges and solutions that were encountered during these works. Although these technology developments have taken a large portion of the work, our final goals of the material, device and circuit engineering efforts in organic electronics are applications. Many different applications could be implemented based on the unique properties of organic electronics. In this chapter, I focus on the implementation of disposable and flexible organic temperature sensors by developing new composite materials.

4.1 BACKGROUNDS AND MOTIVATION

Radio-frequency identification (RFID) is a wireless identification and tracking system using radio-frequency electromagnetic fields. While RFIDs have been very successful in the inventory and smart card applications, the cost is still high for low cost and mass

volume applications, such as RF barcodes. Thus organic electronics have been considered as a low cost alternative technology for RFID tags [2]. Meanwhile, our demands for various sensors keep increasing and some applications require flexible, cheap and disposable sensors [20, 21]. Medical diagnostics, food safety, environmental monitoring are all the areas that would benefit from organic sensors and sensor networks. Although

RFIDs are originally developed for identification and tracking purpose, there are possibilities for RFIDs technologies to be expanded to other areas. If RFID technology can be combined with organic sensors, they would work as wireless sensors with the merits of organic electronics, such as mechanical flexibility, light weight and low cost.

Remote thermal sensor would offer the possibility of monitoring temperature of human body, perishable foods and medicines by simply attaching a flexible tag. Several types of thermal sensors can be fabricated on the flexible substrate. Thermocouple [56], resistive temperature detector (RTD) [57], and organic diode [58] are a few examples.

Thermocouple is based on the Seebeck effect and typically generates voltage difference around 40 to 70 μV/˚C [56, 59]. The resistance change of a standard 100 Ω RTD is only

0.4 Ω/˚C [56, 59]. Thus the readout of these temperature sensors require accurate and complex electronic circuits, i.e. high gain amplifier and high precision analog to digital converters (ADCs) [60], which are not compatible with low cost sensor applications. In this work, I developed new concepts for metal filled polymer composites as thermal sensor materials. These materials showed much higher sensitivity than other types of flexible thermal sensors previously reported. A wireless thermal sensor by combining a

passive RFID antenna and a thermal sensor based on metal filled polymer composites are demonstrated.

4.2 EXPERIMENTAL

Polyethylene (PE, ldrich, MW = 35k , polystyrene PS ldrich, MW = 280k , poly methyl methacrylate PMM ldrich, MW = 280k , poly vinyl acetate PV c

ldrich, MW = 100k , polyethylene adipate PE ldrich, MW = 10k and polyethylene oxide PEO, ldrich, MW = 400, 600 and 1.5k are used as the polymer matrix and were used as purchased. Ni microparticles manufactured by Novamet Type

255 were used as the conductive filler. The typical particle size is about 2 to 3 μm. The

Ni-filled composites were prepared by melt-mixing the materials on a hot plate IK ,

RET V81 at 130˚ with hand stirring.

The crystallinity of polymer was analyzed by differential scanning calorimetry (DSC,

TA instruments Q1000) in a nitrogen atmosphere. The sample was first heated to 150 ˚ to erase thermal history and then cooled down to -60 ˚ with 10 ˚ /min. Melting point and heat of fusion were measured at a 10 ˚ /min heating rate. The heat of fusion ( ) ∆Hf was measured by integrating the area under the melting peak. rystallinity χ of PEO was calculated by comparing to a reference value ( °, 215.6 J/g), which represents ∆Hf ∆Hf the heat of melting of the theoretical 100% crystalline PEO. χ=r∙ / , where r is ∆Hf ∆Hf weight ratio of PEO in the composite.

All polymer composite samples contained 40 wt% of Ni particles. To measure the resistance resistivity of the sample by the two-terminal method, two copper foil electrodes 5mm x 10mm were attached on a glass substrate with a 2mm gap and the polymer composite was pasted on the electrodes with 1mm thickness. The resistivity of the composite along the lateral direction as a function of temperature was measured using a digital multimeter TENM 72-4040 while the temperature of the sample was monitored using an IR thermometer Fluke 63 Mini . The sample was put on a metal plate, which was first cooled down with dry ice and subsequently heated on the hot plate

IK , RET V81 . In the two-terminal measurement method, resistivity ρ was calculated using equation  R S/ d from the measured values of resistance R, sample area S and sample thickness d.

The flexible temperature tag antenna was patterned with 5mm wide copper tape strips

(JVCC, 36 μm thick) on a 75 μm thick PET substrate. The rectangular shape antenna has

3 turns and an area of 15 cm2. The inductance and series resistance of the tag antenna loop were measured as L2 = 1.1uH and R2 = 0.97 Ω. The copper strip was also used as electrodes for the filled polymer. A base station antenna was implemented using 5 turns of copper wires (AplhaWire, D = 1.09 mm, covered with 0.45 mm thick polyvinyl chloride). The antenna loop was circular in shape with a diameter of 14 cm. The inductance and series resistance of the reader antenna loop were 3.3 μH and 0.33 Ω, respectively. A 5 V peak-to-peak sine wave was applied to the series connection of 4.7 nF capacitor and antenna loop. The internal resistance of the signal generator was set as

50 Ω. The flexible tag was put on a glass jar, which was heated using a hot plate (IKA

RET CV81). The glass jar was used for heat transfer, because the metal surface of the hot plate induces coupling with the reader and the tag coil. The temperature of the tag was monitored using an IR thermometer (Fluke 62 Mini). At the same time, the antenna of the reader was placed at the same plane with the tag. The demodulated voltage was measured using an oscilloscope (PCSGU 250).

4.3 THERMAL SENSOR BASED ON METAL FILLED POLYMER

4.3.1 Introduction to Conductive Filled Polymers

Although some organic materials based on π-conjugated oligomers and polymers show semiconducting and conducting properties [2], the majority of organic materials, including polymers, exhibit insulating properties. Polymers in this category, e.g. thermal plastics, usually consist of long chains of repeating units of monomers, which have carbon, hydrogen and other atoms. The valence electrons in the polymers are tightly bounded in sp3 hybridized covalent bonds. Thus most thermal plastics show large band gap, which is the main reason why they are electrical insulators and transparent. However, these polymers can be designed to be conductive or semiconductive by adding electrically conductive fillers, such as metal particles or carbon black [61, 62]. Such composites show a sudden transition from insulator to conductor at certain critical

concentration of the conductive filler. These composites are commercially available for antistatic and electromagnetic interference shielding materials [63]. Some polymer composites show a significant resistivity change with positive temperature coefficients

(PTC). These conductive polymers have been used as self-limiting heating elements, over-current protectors and resettable fuses [64]. The processability and the low cost of the polymer materials are the main reasons why these conductive polymers have become successful.

Ni Particle

polymer

Figure 4.1 Schematic illustration of the metal (Nickel particle) filled polymer composite.

Thermal sensor is another possible application for these conductive filled polymers.

However, there are several limitations of previously reported filled polymer as a thermal sensor. The most important one is the lack of reproducibility due to thermal history [65-

67]. Also, the PTC effect is nonlinear and the sensitive ranges previously reported [68-70] were over 70˚C, which is much higher than the temperature range for the applications such as medical diagnostics, food safety and environmental monitoring. Thus, in this

work, I first investigated methods to improve the reproducibility and adjustability of the

PTC behavior of the Ni filled polymer as a thermal sensor. The effect of plasticizer on the sensor characteristics was explored. Plasticizer is known to modify the properties of polymer such as flexibility, glass transition temperature, and crystallinity. Then, I developed a new concept using binary polymer composites to achieve better stability.

4.3.2 Ni Filled Polymer Temperature Sensor Development

1010 108

108 106

cm) 10 

104 MIN /R 4

10 MAX R 2

Resistivity( 10 102

100 100 10 20 30 40 50 Ni Content (wt%)

Figure 4.2 Resistivity of PE composites as a function of Ni concentration.

The resistivity versus temperature characteristic of the metal filled polymers is determined largely by the properties of the polymer itself. First I tested PE as a polymer matrix and Ni particles as conductive filler. The electrical resistivity at room temperature and the maximum resistance change with temperature change were measured as a

function of the Ni contents, which is shown in Figure 4.2. At lower Ni contents, the filler volume was not enough to form a conductive network. When the filler content increased up to 20 wt%, the room temperature resistivity of the filled polymer fell sharply and the resistivity change over temperature was also increased. I found 40 wt% Ni content was an optimum condition to get a maximum PTC effect with PE as a matrix polymer. The Ni filled PE composites started to lose mechanical flexibility over 50 wt% Ni content.

Table 4.1 PTC effects of various polymers

T b Polymer PT intensitya Crystallinity[71, 72] m Melting Point

6 7 PE 10 ~10 semi-crystalline 95 ℃ 3 PS 10~10 amorphous 240 ℃ PMM <10 amorphous 300 ℃ 2 PV c 10~10 amorphous N/ 6 7 PEO 10 ~10 semi-crystalline 46 ℃ 6 7 PE 10 ~10 semi-crystalline 40 ℃ a PTC intensity is defined by as the ratio of peak resistivity RP to the room temperature b resistivity RRT. Melting point. All polymer composite samples were prepared by mixing each polymer with 40 wt% Ni particles.

I also tested other polymers as a matrix polymer, as shown in Table 4.1. Most of the amorphous polymer composites, e.g. PS, PMMA and PVAc, showed small PTC intensity.

On the contrary, semi-crystalline polymer composites such as PE, PEO and PE showed

6~7 orders of magnitude change of resistivity near their melting point. It is known that

the transformation of the crystalline phase to the amorphous phase in a semi-crystalline polymer causes a significant volume expansion near melting point [61]. If we assume that the fillers mostly reside in the amorphous region [73, 74], the large PTC of semi- crystalline polymer can be explained by the expansion of the crystalline phase during the melting process. This process results in a reduction of the effective filler concentration and increase the inter-particle distances of conductive paths [61]. On the contrary, it is hard to obtain great PTC effect for amorphous polymer composites because the thermal volume expansion is gradual over temperature and not enough to produce significant resistivity change. This is the reason why all commercial PTC-devices are based on semi- crystalline polymers and why the self-limiting region is located in the vicinity of the melting point of the selected polymer [64]. Thus we choose semi-crystalline polymers, i.e.

PE and PEO, for our matrix polymer materials.

Figure 4.3 shows the PTC curves of a filled PE during 5 heating and cooling cycles.

The room temperature resistivity increased over 2 orders of magnitude and PTC curve itself shifted upward with thermal cycles. This shift is undesirable for practical applications. Several researchers have reported about the poor reproducibility and the degradation of PTC curves over thermal cycles [65-67]. According to the previous reports, the poor reproducibility of electrical conductivity could be improved by crosslinking [75], or by using mixtures of two kinds of fillers [67, 76]. However, the degradation issue was not completely solved yet.

107

106

105 cm)

 104

3 1st 10 2nd 3rd 2

Resistivity ( 10 4th 5th 101

100 20 30 40 50 60 70 80 90 100 Temperature (C)

Figure 4.3 Resistivity versus temperature during 5 heating and cooling cycles.

In the Ni filled polymer system, a conductive network was formed by aggregates that

Ni particles fused together. These aggregates are electrically connected but are not chemically bonded with each other. Thus we can assume that there are small gaps between the conductive particles. However, the gap should be small enough for electrons to tunnel or hop [77]. These gaps are considered as main potential energy barriers for electrons to overcome. The number and the width of these gaps greatly depend on the structure, size, shape of the aggregates and the polymer network structure [78]. Since the content of metal particle and polymer remains unchanged during the thermal cycling, the main reasons for the resistivity change could be attributed to the changes in the structure and morphology of polymer network [78]. The thermal degradation of the polymer matrix can break some existing conductive paths, which results in the increase of the

resistivity. Before the thermal cycle, the integrated polymer network held the metal particles together tightly to give the Ni filled PE an initial resistivity below 10 Ω/cm. The force keeping the conductive path can be explained by internal stress (thermal contraction of the polymer) during the cooling of polymer matrix [79]. This internal stress is supposed to pull the conductive particles together, thus maintains the gaps between the conductive particles. Any breakages in the polymer network can reduce the internal stress.

This consequently increases the gap between the conductive particles, which result in the increase in the resistivity of the network. If thermal cycles break the network and the original internal stress is not recovered, the total resistance of the conductive network will tend to increase with the thermal cycles.

Another factor that affects the resistance change of the filled polymer composite is the crystallinity of polymer. Kono and coworkers [73] reported that the crystallinity of slowly cooled polymer sample is higher than that of fast cooled sample. Slow cooling of polymer usually allows chains to move into alignment, thus gives higher crystallinity.

The crystallinity of polymer has an influence on the electrical conductivity of the filled polymer network, because metal particles tend to aggregate in the amorphous region [77].

The crystallinity of a Ni filled PE with different cooling rates was analyzed by differential scanning calorimetry (DSC, TA instruments Q1000) in a nitrogen atmosphere.

The results are shown in Table 4.2. The sample was first heated to 150 ˚ to erase thermal history and then cooled down to 0 ˚ with the specified cooling rates. Melting point and heat of fusion were measured at a 10 ˚ /min heating rate for all cases. With

slower cooling rates, the crystallinity based on heat of fusion was higher and the resistivity was lower. This result is consistent with previous reports [73, 80]. Thus I hypothesized that irreversible change of the polymer network and the polymer crystallinity change are the main causes of the poor reproducibility.

Table 4.2 Crystallinity and resistance of a Ni filled PE with different cooling rates. Resistivity @ RT Cooling rate ∆H (J/g) Melting Point Crystallinity f (Ωcm)

5˚C/min 64.3 97.0 36.6% 3.1

10˚C/min 62.0 96.2 35.3% 2.6

20˚C/min 58.3 95.2 33.2% 3.0

40˚C/min 55.3 94.4 31.5% 5.8 The heat of fusion ( ) was measured by integrating the area under the melting peak. ∆Hf rystallinity χ was calculated by comparing to a reference value ( °, 293 J/g), ∆Hf ∆Hf which represents the heat of melting of the theoretical 100% crystalline PE. χ=r∙ / , ∆Hf ∆Hf where r (=0.6) is weight ratio of PE in the Ni filled PE.

4.3.3 Plasticizer Effects

Plasticizer is widely added to polymers to achieve improved processing characteristics and mechanical flexibility. Plasticizer is also well known to effect on crystallization [81].

The effect is generally towards the reduction of crystallinity but in many cases crystallizing ability can be substantially increased by the increased mobility of the polymer chains or their segments [81]. There have been several reports describing that

plasticizer reduces crystallization time [82, 83]. Also, according to the gel theory of plasticizer [84, 85], plasticization reduces the polymer-polymer interaction, consequently reducing the rigidity of the polymer. In plasticized polymers, there exists a dynamic equilibrium involving solvation-desolvation of the polymer by the plasticizer and aggregation-disaggregation of the polymer chains themselves [81]. Thus plasticizer can help the polymer to reach and maintain the dynamic equilibrium in a certain temperature range and help to recover the original polymer network and internal stress. Here, we use this concept to address the stability and reproducibility issues of Ni filled polymer composites. Plasticizer can make the crystallinity of the polymer less dependent on the cooling rate or thermal history, while the resistivity of the filled polymer is related to crystallinity of the polymer matrix.

40 12

10 35

cm)  30 w/o plasticizer 6 w/ plasticizer

4 Crystallinity (%)

25 Resistivity ( 2

20 0 0 10 20 30 40 Cooling rate (C/min)

Figure 4.4 A plasticizer effect on the crystallinity and resistivity of Ni filled PE composite with cooling rates.

As shown in Figure 4.4, the crystallinity and resistivity at room temperature of a Ni filled PE indeed showed less change with different cooling rates by adding 10 wt% dioctyl phthalate (DOP, Aldrich) as a plasticizer to PE. In addition, DOP as a plasticizer decreased the melting point of the Ni filled PE slightly (3˚ .

107

106

105 cm)

 104

103 1st

2 2nd

Resistivity ( 10 3rd

1 4th 10 5th

100 20 30 40 50 60 70 80 90 100 Temperature (C)

Figure 4.5 The resistivity of a Ni filled PE with DOP versus temperature with 5 heating and cooling cycles

Figure 4.5 shows PTC behaviors of a filled PE with DOP during 5 heating and cooling cycles. The room temperature resistivity and PTC curve does not show any clear trend of degradation during thermal cycles. The PTC curves become more reproducible and reliable with thermal cycles compared with the previous Ni filled PE without adding of a plasticizer. I found that there was a hysteresis between heating and cooling curves in

Figure 4.5, which can be attributed to the lag in heat transfer. The filled polymer has low

thermal conductivity; therefore the temperature of the center of the sample may be lower than the temperature of the surface. The directions of temperature lag with heating and cooling is opposite, thus there is a gap between two curves. Although thermal sensor based on a Ni filled PE with plasticizer showed strong and reproducible PTC effect, the sensitive temperature range was limited around 60~90˚C which is near to the melting point of PE (~95˚C).

4.3.4 Binary Polymer Composites

Even though the plasticizer concept significantly enhanced the reproducibility of the thermal sensor based on Ni-filled PE composite, many applications, e.g. human body temperature measurement and controlling the quality of perishable foods or medicines, require a lower critical temperature range than the previous results. Although most conductive filled polymer composites are based on single polymer, a few studies about binary polymer composites have been reported [86-89]. The primary purpose was to obtain a conductive composite with a very low percolation threshold [86-88] or to eliminate the negative temperature coefficient (NTC) effect [89]. Here, I used the binary polymer concept to tune the sensitive temperature range. I expected such a binary polymer system to provide sensitivity at a required temperature range, while maintaining good reproducibility. One of the polymers, PTC polymer, is chosen with a melting point near the critical temperature range for a specific application. At the same time, the other

polymer is used as a matrix polymer having a much higher melting point to help maintain the composite structure and internal stress to reduce the.

PEO, also known as polyethylene glycol (PEG), is a polyether compound with many applications from industrial manufacturing to medicine. It also has been used as a plasticizer [81, 90]. It is a crystalline polymer with a melting temperature from -45 °C to

65 °C depending on its molecular weight. Thus I hypothesized that PEO can be used as a

PTC polymer to modify the critical temperature range with PE as a matrix polymer.

PEO(M =1.5k) W

46.7 C

PE/PEO(M =1.5k) W 95.9 C

47.2 C Endotherm Heat Flow PE 94.4 C

-40 -20 0 20 40 60 80 100 120 140 160 Temperature (C)

Figure 4.6 DSC thermo diagram of PEO (MW=1.5k), PE, and mixture of PE/PEO (with the ratio of 2:1).

Figure 4.6 shows a DSC thermo-diagram of the PE, PEO (MW=1.5k) and PE/PEO binary polymer composite. Indeed, the melting curve of PE/PEO blend shows two distinct melting points of PE and PEO crystallites. It indicates that each polymer keeps its

physical properties in the PE/PEO binary polymer composite. Based on the heat of fusion

(∆Hf) from the DSC analysis, PEO has high crystallinity (74%) and has a melting peak at

47 °C. Thus a possible assumption of the binary polymer composite is that PEO forms micro crystal domains inside the PE matrix and determine PTC effect of the binary polymer composite. The role of PE matrix is to maintain the macro structure and internal stress.

109

108

107

106

cm) 5

 10

104

103 PEO 100% Resistivity ( 102 PE:PEO = 1:1 PE:PEO = 2:1 101 PE:PEO = 10:1 PE 100% 100 20 30 40 50 60 70 80 90 100 Temperature (C)

Figure 4.7 Resistivity versus Temperature with different polymer ratios (40 wt% Ni).

Figure 4.7 displays the resistivity change of the Ni filled composite with different

PE/PEO blend ratio as a function of temperature. In case of PEO 100% composite, it showed negative temperature coefficient (NTC) effect on the temperature between 40 ˚C and 50 ˚C. NTC effect is known to originate from the movement and aggregation of

conductive particle above the melting point of the polymers when viscosity is low [74].

Thus NTC effect of a Ni filled PEO can be attributed to the low viscosity of PEO after melting. There were two distinct changes with the increasing PE ratio of the PE/PEO composite. First, NTC effect was reduced with the increasing PE ratio. As the melting point of PE (95˚C) is higher than PEO (47˚C) and the molecular weight of PE MW=35k is higher than that of PEO MW=1.5k , the PE matrix seems to prevent the movement and aggregation of conductive particles in the temperature range above the melting point of

PEO. Second, critical transformation temperature is changed from that of Ni/PEO composite close to that of Ni/PE composite with an increasing PE ratio. The resistivity of the binary composite (with the 2:1 ratio of PE/PEO) sensitively changes with temperature between 35˚C and 40˚C. If we consider the melting properties of both polymers, the strong PTC eﬀect of binary composites can be attributed to the melting and volume expansion of the PEO crystallites.

The critical temperature range of PE/PEO binary polymer composite could be changed with the different molecular weight of PEO. Figure 4.8(a) shows DSC melting curve of

PEO with MW 400, 600 and 1.5k. PEO with different MW showed distinct endothermic melting peaks, which are correspond to their melting points. The resistivity versus temperature curves of PE/PEO binary polymer composites also showed corresponding differences based on their melting points. The sensitive temperature with MW 400, 600

PEO was around -10 ˚C and 10 ˚C respectively. Thus we may argue that these results would be useful to monitor the temperature perishable food or medications. This result

also can be evidence that PEO is responsible for PTC behavior of PE/PEO binary composites.

(a)

PEO(M =400) W 4.9 C

PEO(M =600)

21.5 C

PEO(M =1500)

W Endotherm Heat Flow 46.7 C

-40 -20 0 20 40 60 Temperature (C) (b)

108 107

6 PEO 10 (M =1.5k) W 5

cm) 10  PEO 104 (M =600) W 103 2 PEO

Resistivity( 10 (M =400) W 101 100 -40 -20 0 20 40 60 Temperature (C)

Figure 4.8 (a) DSC thermo diagram of PEO with different molecular weights. (b) Resistivity of PE/PEO binary polymers (weight ratio 2:1, 40 wt% Ni) versus temperature.

Figure 4.9(a) and (b) show SEM images of PE/PEO binary polymer. The sample was prepared at room temperature. There are two separated regions. The first one is PE as a matrix polymer. PE regions show large plastic deformation and filamentary shapes [91,

92] because PE has a high molecular weight (MW = 35k) and a low glass transition

temperature (-125 ˚C). The second region is PEO as a PTC polymer. The Ni particles are mostly found in the PEO region, which is consistent with our assumption. The size of Ni particle was 2 to 3 μm as shown in Figure 4.9 (c).

(a) (b) PE

PEO PE

PEO

100um 10um

(c)

1um

Figure 4.9 Cross sectional SEM image of (a) a Ni filled PEO/PE (MW=1.5k) composite (weight ratio = 2:1) and (b) close-up image. (c) A SEM image of Ni particle.

Impressively, even over 6 heating and cooling cycles, the resistivity of PE/PEO binary polymer (weight ratio 2:1, 40 wt% Ni) did not show any distinct degradation as shown in

Figure 4.10. The PTC behaviors are reproducible and reliable with thermal cycles and there is minimum NTC effect.

107

6 10 1st 2nd 5 10 3rd

4th cm) 4  10 5th

6th 103

Resistivity ( 10

101

100 20 25 30 35 40 45 Temperature (C)

Figure 4.10 Resistivity of PE/PEO binary polymers (weight ratio 2:1, 40 wt% Ni) versus temperature over 6 thermal cycles.

The sensitivity, the accuracy and the operating temperature range for different thermal sensors are compared in Table 4.3. Even though our Ni filled polymer sensors are not as accurate as conventional RTD or thermister devices, they have higher sensitivity and larger temperature coefficient at the specific temperature range that we intended. Also temperature measurement for the temperature sensor can be simplified utilizing the orders of resistivity change. Further tuning of polymer composites should improve the accuracy. Importantly, this work demonstrated the feasibility of the thermal sensor based on the Ni-filled binary polymer composites.

Table 4.3 Properties of different thermal sensors [93].

Accuracy Operating Thermal sensor Sensitivity α- coefficient (3σ) Temperature Range

100Ω RTD 0.392 Ω/˚C 0.4 %/˚C ± 0.17 ˚C -200˚C to 1300˚C

10k Ω Thermistor 438 Ω/˚C -3 to -5 %/˚C ± 0.17 ˚C -80˚C to 150˚C

Ni filled PE 0.5~105 Ω /˚C 5 to 20 %/˚C ± 9.6 ˚C 50˚C to 90˚C

Ni filled PE/PEO 10~106 Ω/˚C 10 to 90 %/˚C ± 2.7 ˚C 35˚C to 42˚C

4.4 WIRELESS TEMPERATURE SENSOR

4.4.1 Wireless Temperature Sensor Architecture

Due to the extremely large resistivity change of our thermal sensors, they are easily integrated into an antenna circuit of RFID. Figure 4.11 shows a block diagram of typical passive RFID architecture [17]. A RFID system uses tags attached to the objects to be identified. Base station functions as a radio transmitter and receiver, which are called reader. It sends both energy and data to the tag and read its response. An RFID reader transmits an encoded radio signal to the tag. The tag receives the radio signal and responds with its identification information which is stored electronically in a tag. RFID tags can be either passive, active with a battery. An active tag has a battery that can operate internal circuits. A passive tag is cheaper and smaller because it has no battery.

Instead, the tag uses the radio energy transmitted by the reader as its energy source.

Base Station Transponder

Energy r ) o F

s R d s ( e e a a

n e r c c y n n o a i c o a a

c n n f f d o r r c e e n r m i a t Data t e e e e p g t t n n R u o o n n M A A r I I q L c e i r F M

Figure 4.11 A block diagram of typical passive RFID architecture.

Figure 4.12 shows the test structure we use for the wireless thermal sensor. It uses the same antenna structure of a passive RFID tag. The thermister, which is the filled polymer composite with PTC characteristic, is used to directly modulate the antenna circuit with the resistance change. The resistance change induces different loading to the LC resonant circuit, which causes voltage modulation of the tag and as a result the base station. The reader and the tag of the test structure operate through inductive power coupling.

Conceptually, the inductor of the reader antenna acts as a primary coil in a transformer, while the inductor in the tag acts as a secondary coil [17]. Coupling occurs between two coils through air. To increase the voltage generated by the harvesting process, the antenna stage on the tag is typically a resonant circuit with the antenna inductor connected in parallel with a capacitor [17]. The specific values of the inductance and capacitance are chosen so as to cause a resonance at the frequency of the reader

Base Station Transponder

Demodulator

Energy

C1 RT RS R1 R2 C2 r e

Data t s i

L1 L2 m r e

Signal h T generator Antenna winding Antenna winding

Figure 4.12 A test circuit structure of wireless thermal sensor. L1 and R1 are the inductance and series resistance of base station antenna, C1 is the capacitance, and RS is the output resistance of signal generator. L2 and R2 are the inductance and series resistance of the tag antenna, C2 is the capacitance, and RT is the resistance of the thermal sensor.

. Some of the flux generated by the antenna loop of the base station passes through the antenna winding of the tag. This coupling induces a voltage and current to the tag circuit.

Also the induced current effect in the tag antenna affect to base station antenna vice versa.

The mutual inductance, M, represents this coupling effect with the unit of Henry. If we apply the Kirchhoff‟s voltage low (KVL) to both base station and tag circuit loops in

Figure 4.13, we can obtain two equations.

1 vSS R   R1  j L 1 i 1  j Mi 2 (4.1) jC 1

RT 0 j Mi1  j L 2  R 2  i 2 (4.2) 1 j C2 RT

V1 V2 I1 I2

C1 RT RS R1 R2 M C2

VS L1 L2 Signal generator Basestation Tag Thermister Antenna Antenna winding winding

Figure 4.13 A circuit diagram of wireless thermal sensor test structure, where M is mutual inductance (unit of henry) between the base station antenna and the tag antenna.

Where j is an imaginary number and ω is angular frequency of a driving signal.

If we substitute i2 from the Equation 2 to Equation1, we find as follows.

22 1 M(1 j C2 RT ) vSS R   R1  j L 1  2 i 1 (4.3) jC1 RjLCRR 2 ( 2  2 2TT )  (1   LCR 2 2 )

The voltage across the antenna of base station (v1) is used for demodulation of the sensor signal.

v1() R 1 j L 1 i 1

R11 j L  22 vS (4.4) 1 M(1 j C2 RT ) RS   R11  j L  2 jC1 RjLCRR 2 ( 2  2 2TT )  (1   LCR 2 2 )

Equation 4.4 can be simplified if we set the resonant frequency as same as the driving frequency ω .

100

1 if   , then LC22

R11 j L vv1  22 S 1 M(1 j C2 RT ) (4.5) RS   R11  j L  j C1 R 2 j() L 2 C 2 R 2 RT

Thus the voltage across the inductor of the base station is changed with the resistance variation of the thermal sensor (RT). We can consider extreme cases of thermal sensor resistance to know the limitations of the demodulated voltage V1.

R j L If R  0 , vv 11 . T 1,max 1  22M S (4.6) RS   R11  j L  j C1 R 2 j L 2 R j L If R , vv 11 T 1,min 1  22M S (4.7) RS   R11  j L  j C12 R

Thus the demodulated voltage will have a value between this maximum and minimum as a function of temperature. A simulation was performed to get a general idea about the relationship between the resistance of the thermal sensor (RT) and the modulated voltage at the reader (V1). As expected, the magnitude of modulated voltage (V1) has a value between maximum and minimum in Figure 4.14. V1 shows a large sensitivity when RT is from 10 Ω to 10 KΩ. A RT below 10 Ω shorts the resonance circuit. Thus loading of the tag to the base station circuit is minimized and the modulated voltage shows a maximum value. On the contrary, a RT above 10 KΩ does not affect the resonant circuit of the tag.

Two parameters are related to the minimum value of V1. The first parameter is coupling

101

coefficient k, which is determined by the geometrical configuration, material, and distance between two antennas. Another parameter is Q factor of the tag LC circuit.

Series resistance of inductor (R2) is inversely proportional to Q factor. Thus R2 should be minimized to increase V1 range.

4.5

4.0

3.5

(V)

1 V

3.0

2.5 100 101 102 103 104 105 106 R ( T

Figure 4.14 A simulation of modulated voltages (V1) at the base station with the change of RT.

4.4.2 Flexible Wireless Temperature Sensor Tag

The flexible tag with a temperature sensor is composed of a loop antenna, a chip-type capacitor (4.7 nF) and the Ni filled polymer as a thermal sensor. The Ni filled polymer composite was prepared as discussed before. The tag antenna was patterned with 5mm wide copper tape strips on a 75um thick PET substrate. The rectangular shape antenna has 3 turns and an area of 15cm2. The inductance and series resistance of the tag antenna loop were measured as L2=1.1uH and R2=0.97 Ω. The copper strip was also used as

102

electrodes for the filled polymer. The inductive antenna loop, a capacitor and a thermal resistor constitute a parallel resonant circuit as shown in Figure 4.15. A base station antenna was implemented using 5 turns of copper wires (AplhaWire, D=1.09mm, covered with 0.45mm thick polyvinyl chloride). The antenna loop was circular shape with 14 cm diameter. The inductance and series resistance of the reader antenna loop were 3.3uH and 0.33 Ω. A 5 V peak to peak sine wave was applied to the series connection of 4.7nF capacitor and antenna loop. The internal resistance of the signal generator was set as 50 Ω.

Antenna (a) (b) Capacitor Thermistor winding

RT R2 C2

Thermister

(c)

Figure 4.15 (a) A circuit diagram of the wireless thermal sensor tag. (b) Prototype of wireless thermal sensor tag and (c) the tag under bending.

103

Computer IR Thermometer Sensor Tag Oscilloscope

Base station Base station Circuit Antenna

Heat Transfer Signal Medium generator (Glass)

Hot Plate

Figure 4.16 The schematic of experiment set-up for wireless sensor calibration.

Figure 4.16 shows experiment set-up of sensor calibration and measuring. The tag was put on a glass jar, which was heated using a hot plate (IKA RET CV81). The glass jar was used for heat transfer, because the metal layer in the hot plate induces coupling with the reader and the tag coil. The temperature of the tag was monitored using an IR thermometer (Fluke 62 Mini). At the same time, the antenna of the reader was placed at the same plane with the tag. The demodulated voltage was measured using an oscilloscope (PCSGU 250).

The average and standard deviation of readout voltage as a function of temperature are shown in Figure 4.17. The sensitivity, which is defined as the voltage change per unit temperature change, was 0.1 to 0.3 V/˚C in the temperature range between 35 and 42 ˚C.

These sensitivity values are 3 orders of magnitude larger than the standard thermocouple

104

devices (40 μV/˚ ) [93]. However, the maximum inaccuracy of our temperature sensor

3σ was ± 3.1 ˚ , which still needs to be improved for most applications. To demonstrate the wireless temperature sensor operation, the voltage amplitude values of the oscilloscope were read by a windows program and converted to a temperature values based on the calibrated data.

4.2

4.0

3.8

3.6

3.4

Average 3.2 Standard Deviation

3.0 VoltageAmplitude (V)

2.8

2.6 20 25 30 35 40 45 50 Temperature (C)

Figure 4.17 Statistical data of readout voltage as a function of temperature.

4.5 SUMMARY

Wireless thermal sensor based on conductive filled polymer was demonstrated. The stability and reproducibility were improved by adding a plasticizer. Binary PEO/PE composite enabled removal of NTC effect and also gave adjustability of PTC temperature.

We obtained strong PTC effect around 35˚C to 42˚C, which is optimal for human body

105

temperature monitoring. Also, I demonstrated lower PTC temperature range by using

PEO with lower MW. The sensitivity was up to 0.3 V/˚C, which is 3 orders of magnitude higher than the standard thermocouple device. However, the maximum inaccuracy 3σ was ± 3.1 ˚ , which still needs to be improved. The large resistive change enabled design and fabrication of wireless temperature sensor on a plastic substrate. Such a simple tag offers opportunity of in-situ wireless monitoring a temperature. It can potentially open up new sensor applications.

106

CHAPTER 5: CONCLUSIONS AND

OUTLOOK

5.1 CONCLUSTION

In this dissertation, extensive studies have been performed to improve the characteristics of organic electronics. The topics described span from device engineering of OTFT to practical applications. In particular, the following theme areas were identified:

Demonstrated the fabrication of short channel and self-aligned OTFTs on a flexible substrate by imprinting of a prism-like surface topology. The self-aligned structure enabled accurate self-alignment between the electrodes with a pre-defined prism- structure dimension, thus reducing parasitic overlap capacitance and increasing maximum operation frequency of OTFTs. The imprinting technique that used to fabricate the prism-structure substrate is scalable for large area applications and is compatible with flexible substrates. This approach allows for the creation of short-channel OTFTs without photolithographic patterning of electrodes.

Proposed an OTFT circuit design methodology that enables accurate analysis and verification in the design stage. Circuit simulation model for OTFTs was proposed to

107

describe non-linear characteristics and also circuit design methodology was optimized with computer aided design software.

Various topologies of digital OTFT circuits were demonstrated. Specifically, a unipolar p-type circuit based on bootstrap technique showed comparable characteristic to complementary type circuit. With this bootstrap structure, the p-type-only logic circuit showed full swing output, higher voltage gain and noise margin than the conventional diode-load structure.

Demonstrated a wireless thermal sensor based on Ni-filled polymer composites. The stability and reproducibility were improved employing binary polymer composites. This structure gave adjustability of PTC temperature. Strong PTC effect around 35˚C to 42˚C was obtained, which is optimal for human body temperature monitoring. The sensitivity was 3 orders of magnitude higher than the standard thermocouple device.

5.2 OUTLOOK

The future of organic electronics looks very promising. Organic materials still have chances to be further improved with material design and chemical synthesis. Also, the development of organic electronics can be accelerated by the device and circuit engineering efforts, which are the main topics of this dissertation. I expect that prism-

OTFT with nano imprinting technology will enable further down-scaling of OTFTs. Thus

108

it is possible to implement OTFT circuits with MHz operating frequency. Imagine organic RFID tag combined with the proposed thermal sensor. It would work as a RFID and also as a temperature sensor with mechanical flexibility, light weight and low cost.

109

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