7. Trigger Interface Board. 151

RJ45 connectors between the clock board and the TIB, and the ones of the RJ45 connectors of the links between the TIB and the backplanes, are assigned as it is shown in table 7.1. The signal named as CABLE DETECT, not yet mentioned, is used to ensure that the plug is connected properly and just consists on a 1 kΩ resistor to ground in the reception side, and an input pin of the FPGA with a weak pull-up in the transmission side. So, the FPGA detects if it is properly connected or not.

to clock board from clock board to/from central to-from not central backplane backplane Pin Signal Signal Signal Signal 1 CAMERA TRIGGER + CLK 10MHZ + L1 TRIGGER + TRGTYPE CLK + 2 CAMERA TRIGGER - CLK 10MHZ - L1 TRIGGER - TRGTYPE CLK - 3 TRGTYPE0 + SOFT ARRAYTRIG + CAMERA TRIGGER + TRGTYPE DATA + 4 TRGTYPE1 + SPARE 1+ BUSY + RES TOPO1 + 5 TRGTYPE1 - SPARE 1- BUSY - RES TOPO1 - 6 TRGTYPE0 - SOFT ARRAYTRIG - CAMERA TRIGGER - TRGTYPE DATA - 7 CABLE DETECT CABLE DETECT SPARE + RES TOPO2 + 8 GND GND SPARE - RES TOPO2 -

Table 7.1: Pinout definition of the RJ45 connectors between the TIB and the clock board and the central backplane

Apart from these RJ45 connectors, others will be available in the TIB as spares, or with the aim to be used to implement advanced features like the ones explained in section 7.3. It is important to point out that the TIB is compatible with two different front-end boards (NECTAr and Dragon), two different clock boards (MUTIN and White Rabbit) and will work in LSTs and MSTs. A lot of coordination work has been required to achieve this compatibility.

7.2 Hardware stereo trigger

As was explained in section 3.2.8.1, the hardware stereo trigger function consists of looking for simultaneous triggers in neighbour telescopes, inside a time window of a few tens of nanoseconds, with the aim to readout only the events which triggered more than one telescope. As the probability of having more than one telescope triggered by NSB inside this short time window is rather low, the stereo trigger detects most of the events caused by Cherenkov showers, while rejecting most of the NSB events. The rejected events are never digitized, not contributing to the dead time. Thus, the telescope readout rate is reduced, so it is possible to reduce the Level 1 thresholds and increase the sensitivity to low energy γ-rays4.

7.2.1 Timing restrictions

In order to look for coincidences inside the mentioned time window (typically 50 ns), the TIB in each LST camera must receive the Level 1 trigger signals from its neighbour LSTs plus its local Level 1 trigger. However, as the neighbour LSTs are far away (at distances of around 100 m), their trigger signals will reach the TIB some time after the local Level 1 trigger. In this way, the local trigger must be delayed a time equivalent to the propagation delay before looking for coincidences. The situation

4To optimize the sensitivity to low energy γ-rays, the thresholds must be as low as possible, while maintaining a sustainable readout rate. 152 7. Trigger Interface Board. becomes more complicated if we take into account that each neighbour LSTs can be separated a different distance. Moreover, the time of flight of the Cherenkov light is different depending on the pointing direction. At the end, all these delays mean that the data must be stored in the analog memory buffers until all the triggers from the neighbour LSTs reach the local telescope, the TIB decides if there has been a coincidence or not and, in the positive case, the camera trigger signal is distributed to all the clusters in the camera. Therefore, the analog memory buffer must be long enough to keep the signal stored until the trigger arrives. The Dragon front-end boards are equipped with four DRS4 [56] chips with 1024 analog memory cells in each channel, which means that it is able to store up to 4096 ns with a sample frequency of 1 GHz. This is required to implement the hardware stereo trigger in the LST subarray, and thus achieving the best sensitivity to low energy γ-rays. In the next subsections the different sources of time delay are analyzed and how the Dragon front-end board buffer can cope with them.

7.2.1.1 Compensation of the fixed delays

The approximate fixed delays which contribute to the minimum length of the memory buffers, considering optical fibers with a refraction index of 1.5, are the following:

• 220 ns corresponding to Level 0, Level 1 and the distribution through the clusters until reaching the TIB (break down in table 3.1).

• 500 ns for the 100 m optical fiber between the TIB and the LST basement (see figure 7.5).

• 500 ns if the neighbour LST is placed at 100 m from the local one, or 700 ns if it is 141 m away (see figure 7.6).

• 500 ns for the 100 m optical fiber between the LST basement and the TIB.

• 170 ns for the trigger distribution of the camera trigger signal down to the clusters

This means that all the inputs must wait for the trigger from the furthest telescope, which needs at least 2090 ns to reach the telescope which we are considering as local.

7.2.1.2 Compensation of the Cherenkov light time of flight

The Cherenkov showers are generated at ca. 10 km height, which is far enough to consider the photons as forming a plane wave front. Thus, if all the telescopes are pointing to the zenith, the wave front will reach them at the same time and only the fixed delays explained in section 7.2.1.1 need to be taken into account. However, in real operation the telescopes will not be generally pointing to the zenith, but to a certain location defined by specific azimuth and elevation angles. In this conditions the distance travelled by the photons is not the same for each telescope, and therefore the shower images will be formed at different times. The delay differences due to the different time of flight of the Cherenkov photons must be compensated in order to perform the coincidences of the images caused by the same shower. 7. Trigger Interface Board. 153

Figure 7.5: Sketch of the optical fiber from the camera to the basement, with an estimated length of 100 m

100 m m m 1

0 4 0 1 0 m 0 1 1

100 m

Figure 7.6: Expected LST layout, in a 100 m square rectangular grid

As it is easy to understand from picture 7.7, when two telescopes are aligned with the pointing direction, the different distances travelled by the Cherenkov photons depends on the elevation angle θ as defined by equation 7.1:

∆d = d cos θ (7.1)

However, as the telescopes are not usually aligned with the pointing direction, the additional distance at ground level that the Cherenkov photons must travel through (d in equation 7.1) depends on the the azimuth angle ϕ. 154 7. Trigger Interface Board.

∆d

θ θ d

Figure 7.7: Different distance travelled by the Cherenkov photons depending on the elevation angle θ

ϕ ϕ

π/2 1 2 ϕ 1 2 π/2 d l ϕ ϕ d

3 l 4 3 4

(a) Light path difference between IACTs aligned (b) Light path difference between IACTs aligned parallel to the axis ϕ = 0 parallel to the axis ϕ = π/2

Figure 7.8: Different time of flight depending on the azimuth angle

Considering four LSTs placed at the corners of a square, and oriented with respect to the coor- dinate system as shown in figure 7.8, the distance d used in equation 7.1 for telescopes 3 and 4 with respect to 1 and 2 respectively, are defined by equation 7.2, for ϕ < π/2.

d = l cos ϕ (7.2)

On the other hand, the distance d for LSTs 2 and 4 with respect to LSTs 1 and 2, is given by equation 7.3, for ϕ < π.

d = l sin ϕ (7.3) 7. Trigger Interface Board. 155

Thus, for θ < π/2 and ϕ < π/2, the different time of flight of the Cherenkov photons coming to LST 3 with respect to LST 1 will be given by equation 7.4, while for LST 4 with respect to LST 3 it will be given by 7.5.

l ∆time of flight = cos ϕ cos θ (7.4) 31 c

l ∆time of flight = sin ϕ cos θ (7.5) 43 c

Similar equations can be obtained in a similar way for any two pair of telescopes. It is easy to see that the maximum time difference to be compensated in the TIB will be the one required by the photons to travel a distance equivalent to the maximum telescope separation in ground, i.e. 141 m. In fact, the telescopes will never point at elevation angles lower than 15◦5, so the maximum distance difference is 136 m, corresponding to 454 ns. This time should be added to the 2090 ns due to fixed delays, so a buffer of at least 2544 ns is required. Moreover, some more time should be added to perform the logic operations in the TIB, generate the optical pulses, send the different signals through the RJ45 cables in the camera or just as a safety margin. Therefore 3 µs can be considered as the minimum time difference required6, so the 4096 cells of the Dragon front-end board, operating at 1 GHz sampling rate, should be enough. It is worth to mention that in normal operation the IACTs will be tracking the γ-ray sources through the sky during some time, from several minutes to hours. During this time the azimuth and elevation angles change, and therefore the delay differences to be compensated. Thus, the pointing direction must be updated quite often and the compensation times must be recalculated. As an example, in order to compensate time errors lower than 2 ns, the pointing direction should be updated for every change of 0.34◦, corresponding to 82 s in the worst case, when the IACTs are pointing near the zenith. The pointing direction is provided by the slow control system.

7.2.1.3 Synchronization with local trigger

The delay adjustments explained in sections 7.2.1.1 and 7.2.1.2 are useful to verify if the Level 1 triggers generated in the local LST and its neighbours are happening inside the coincidence win- dow, and thus fulfilling the stereo trigger condition. Due to statistical fluctuations in the shower development, there is a certain jitter in the arrival times of the Cherenkov photons, which makes the optimum duration of the coincidence window to be around 50 ns. This effectively means that, for every single event, the stereo condition can be accomplished at any time during inside the window, with an uncertainty of several tens of nanoseconds. Due to this uncertainty, it is rather inconvenient to generate the camera trigger signal synchronized with the time at which the trigger condition is fulfilled (see figure 7.9). As it was briefly mentioned in the introduction of chapter 3, one of the targets of the trigger system is to minimize the jitter to reduce the amount of samples required for each event (and, as a consequence, the dead time) and to allow the calibration of the DRS4 cells. Therefore, a jitter of up to 50 ns in the trigger time is not acceptable.

5For lower angles, the length of the path in the atmosphere which the Cherenkov photons must travel through, is very long and the telescope response is degraded. 6CTA consortium specified 3500 ns 156 7. Trigger Interface Board.

(a) Early trigger condition

(b) Late trigger condition

Figure 7.9: If the camera trigger signal is synchronized with the trigger condition, the time required to generate the trigger command is variable

Nevertheless, the time uncertainty in the compliance with the trigger condition is not a real problem. In fact, every LST has to read its local data, and these local data are synchronized with the local trigger, not with the trigger condition. So, the camera trigger signal must be generated a fixed and precise time after the local trigger, as shown in figure 7.10, whenever the trigger condition was satisfied. This fixed time must be somewhat longer than the longest time required to compensate the delay differences and to finish the coincidence window.

7.3 Advanced features

Interfacing with the other trigger generating subsystems and implementing the hardware stereo trigger for four LSTs are the two basic functionalities of the trigger interface board. However, there are other interesting features that can be implemented in the trigger interface board, which are described in this section. 7. Trigger Interface Board. 157

(a) Early trigger condition

(b) Late trigger condition

(c) No trigger condition

Figure 7.10: If the trigger command is synchronized with the local trigger, the time required to generate the camera trigger signal is fixed 158 7. Trigger Interface Board.

7.3.1 More LSTs

In principle, there will be four LSTs in the CTA array, both in the north and south hemispheres. However, in the future more LSTs could be built if there were a special interest in improving even more the sensitivity or reducing the observation time at low energies7. In anticipation of this possible enlargement, the trigger interface board is able to handle up to nine LSTs and perform the stereo trigger algorithm with all its inputs.

100 m 100 m m m m 1

0 0 4 0 1 0 0 m 0 1 1 1

2 82 100 m m 100 m m m m

0 0 0 0 0 0 1 1 1

100 m 100 m

Figure 7.11: 9 LST possible layout

With a layout like the one showed in figure 7.11, the required buffer size needs to be increased in 700 ns corresponding to the additional 141 m of optical fiber between the most separated LSTs (eq. 7.6), plus 470 ns corresponding to the increment in in the time of flight (eq. 7.7). Thus, the buffer must be able to store at least 3714 ns of signal, and there would be 382 ns of margin for the TIB logic operations, distribution, etc, considering 4096 memory cells and a sampling frequency of 1 GHz.

141m ∆toptical fiber = c = 700 ns (7.6) 1.5

141m ∆t = = 470 ns (7.7) maximum time of flight c

7The higher the number of LSTs, the larger the number of recorded low energy events and, at the end, the shorter the time required to obtain statistics and scientific results. 7. Trigger Interface Board. 159

7.3.2 MSTs contributing to the LST stereo trigger

The readout of the MSTs will be based on NECTAr chips8, which only have 1024 memory cells, so it cannot store more than 1024 ns in its buffer if sampling at 1 GHz. This means that the MST cameras can not wait for the trigger information from the neighbour IACTs, nor be triggered in a hardware stereo mode. However, they can contribute to the stereo trigger algorithms running on their LST neighbours, as sketched in figure 7.12. Provided that the distances are short enough, the MSTs can use their trigger interface boards to broadcast their local Level 1 trigger pulses to their neighbour LSTs, which can wait for them and thus take this information into account in their stereo trigger algorithms. This idea can take advantage from the TIB capability to handle up to 9 trigger inputs, without requiring to build more expensive LSTs. Nevertheless, as the MSTs and LSTs are optimized for different γ-ray energy ranges, the gain in performance of the LST will be minor.

Figure 7.12: A possible stereo trigger scheme with LSTs and MSTs

7.3.3 Slow controllable functionalities

As will be described in section 7.4, the TIB is a flexible system essentially implemented in an FPGA and with a micro-PC used for slow control. This architecture makes possible to implement additional functionalities in a straightforward way, as well as to control important parameters dy- namically. For instance:

8In fact, only some MSTs will be based on NECTAr, while others will follow different architectures. Anyway, if the TIB would be used in this other MSTs, the situation would be the same. 160 7. Trigger Interface Board.

• The duration of the coincidence window can be changed by the slow control system.

• The trigger condition can be changed, in order to choose to look for coincidences of 2, 3, 4 or even more telescopes. Disabling the stereo mode and triggering only in mono mode is also an option.

• The local Level 1 trigger rate, stereo trigger rate and the trigger rates from the neighbours can be monitored by the slow control system, which can take decisions based on this information (change Level 1 thresholds, change Level 1 trigger region size, change stereo trigger condition, etc.).

• The temperature and the status of the optical links can also be monitored, generating alarms if a failure is detected.

7.3.4 Busy state

One of the additional functionalities foreseen in the TIB is a busy state, to avoid distributing new camera trigger signals to the clusters while the readout is still digitizing. This can be required if the readout system is not able to discard these triggers by itself, and it would be as simple as ignoring all the triggers produced during the dead time started after a trigger command. This scheme could be more complex if different dead times among clusters are considered. For instance, if a scheme like Colibri is used, only the clusters which are effectively read-out would suffer dead time and, as they would start digitizing at slightly different times, their dead times would also finish at slightly different times. In this case, a BUSY signal (already considered in section 7.1), obtained as the global OR of the busy state of all the clusters, would be required.

7.3.5 Topologic stereo trigger

The next step to improve the stereo trigger performance and the noise rejection in an stereo scheme consists on using not only the information about when an IACT was triggered but also what part of the camera caused the trigger. This information can be used by the stereo system to check if the local triggers are compatible with the expected patterns for single γ-ray-like events or, on the contrary, they correspond to different events which occurred at the same time just by chance. In the last case, it is very likely that some of these events were caused by NSB, so they should be discarded[143]. Figure 7.13 show several examples of stereo trigger patterns compatible with Cherenkov showers or not. The implementation of a topolologic stereo trigger working as described in the previous paragraph is much more complex than the basic functionality, requiring to send to the neighbours not just the trigger pulse, but also a piece of information containing which cluster was fired, or at least in which part of the camera was placed the cluster that was fired. Nevertheless, the optical links between telescopes can be used to broadcast this information, and the FPGA firmware can be improved to handle it, so in principle it is not impossible to implement the topologic stereo scheme with the TIB. An important difficulty would be how to send the number of the local fired cluster to the TIB. The discussion about this is still an open issue, and the topologic stereo trigger will be an important line of work during the next years. 7. Trigger Interface Board. 161

(a) (b) (c) (d)

Figure 7.13: Several topologic stereo trigger patterns. 7.13(a), 7.13(b) and 7.13(c) would fire the stereo trigger, but not 7.13(d)

7.4 Technical description

7.4.1 General architecture

The TIB is implemented in a single PCB housed inside a 19” 1U rack box, as shown in figure 7.14. This rack box will be placed inside the camera, connected to the central backplane, the slow control unit, the clock board, the calibration box, the TIBs in other neighbour IACTs and the power supply unit, as was described in section 7.1. At the same time, the Trigger Interface Board is composed of several electronic subsystems, most of them handled by an FPGA as it is shown in figure 7.15.

Figure 7.14: Trigger Interface Board prototype inside the 1U rack box

The different subsystems are described in the following subsections.

7.4.2 Optical links

Some essential hardware elements of the Trigger Interface Board are the optical links. Even in the case of MSTs triggering in mono, where no communication with neighbours would be required, some 162 7. Trigger Interface Board.

External Short Power Thermometer Supplies Delay Unit

External Long FPGA Delay Unit Raspberry Pi

Optical RJ45 SFP Drivers Connectors

Figure 7.15: Internal block diagram of the Trigger Interface Board optical links are needed for the communication with the calibration box (calibration and pedestal triggers), or as an alternative possibility to implement fixed delays with optical fibers. The main components of the optical links are described in the following subsections.

7.4.2.1 Optical fibers

Between every two modules connected (TIBs of neighbouring telescopes, calibration boxes, etc.), there will be a cable containing two multimode optical fibers 50/125 OM3 [144] [145]. This kind of optical fibers are suitable for links of up to 550 m length, handling bit rates of up to 10 Gbps, corresponding to pulses as short as 100 ps. As the distance between telescopes will never be longer than 182 m (supposing an unlikely 9 LST subarray), and the transmitted trigger signals are expected to be around 5 ns width, this kind of optical fibers are very appropriate for our system. Additionally, as this kind of optical fiber cables are very common in LANs, they are quite cheap, with prices around 0.50 AC/m.

The optical fiber cables are terminated with standard LC multimode duplex connectors, like the one shown in figure 7.16.

7.4.2.2 Transceivers

Two options were considered to implement the optical transceivers: Using standard SFP modules, or using discrete VCSELs and PiN photodiodes mounted inside LC housings. 7. Trigger Interface Board. 163

Figure 7.16: Duplex LC connector

7.4.2.2.1 SFP modules

The first option considered for the transceivers was to use a standard SFP module like the AFBR- 5715ALZ from Avago Technologies which is shown in figure 7.17(a). These transceivers consist of a transmitter section based on a 850 nm VCSEL (Vertical Cavity Surface Emitting Laser) and a receiver section containing a PiN photodiode, together with their drivers, amplifiers and other an- cillary electronics [146]. One of the optical fibers in the cable is connected to the transmitter and other to the receiver, in order to build the bidirectional link. The transceiver mentioned above is suitable for OM3 optical fibers, reaching a maximum data rate of 1.25 Gbps. These means that the shortest pulses will be 0.8 ns wide, still shorter than the expected pulses (around 5 ns). Apart from the transmitted and received trigger signals, the transceivers generate two control electronic signals named TX Fault and LOS to indicate possible failures in the transmission or the reception respectively, and receive one signal TX Disable, which switches off the transceiver when it is set to high level. Subsection 7.4.4.7 explains how these signals are handled by the FPGA. Regarding the mechanics, the transceivers comply with the Small Form Factor Pluggable (SFP) standard. This allows to use housings from different suppliers, like the one shown in figure 7.17(b), able to house up to 4 transceivers inside. When some link is not in use, the transceiver can be pull out from the box, or just never being installed, saving resources.

(a) Transceiver AFBR-5715ALZ (b) 4x SFP box

Figure 7.17: Transceiver and housing for 4 SFP transceivers

Nevertheless, the SFP transceivers have a minor difficulty: the transmitter must be driven by LVPECL signals, and the receiver also provides LVPECL output signals. This logic standard can not be managed directly by the FPGA, requiring an intermediate stage for translating the LVPECL 164 7. Trigger Interface Board. signals to LVDS or other standard supported by the FPGA. This translation can be implemented with the differential translators SN65LVDS100 and SN65LVDS101, from Texas Instruments [147]. SN65LVDS100 performs the conversion of the LVPECL signals into LVDS ones, while SN65LVDS101 is used in the LVDS to LVPECL translation. In spite of this inconvenient, the AFBR-5715ALZ SFP transceivers were selected to be mounted in the first TIB prototype due to their simplicity and with the aim to use standard solutions.

7.4.2.2.2 Discrete VCSELs and PiN photodiodes

Due to some problems found during the tests of the first TIB prototype (see section 7.5.9), an ad hoc design for the transceivers has also been considered. Designing the optical transmitter and receiver with discrete VCSELs and PiN photodiodes is an option which provides with great flexibility to optimize the bandwidth, the cost or the power consumption. The drawback is that some analog processing stages need to be designed in order to feed the VCSEL with a signal inside its input range, and to recover an LVDS signal from the analog output of the photodiode. The most critical characteristic is the bandwidth, which must be as large as possible in order to have pulses with very sharp edges, thus maintaining the timing information. The design of the transmitter is shown in figure 7.18. The VCSEL chosen emits at 850 nm and has 1 GHz bandwidth. It was provided by AFE ltd. [148] who also assembled it in an LC plastic housing. Considering a single-ended input signal between 0 and 3.3 V from the FPGA, the AD8009 [149] operational amplifier is used to adjust the voltage range of the signal and to avoid overloading the FPGA. The AD8009 is a very fast operational amplifier (5500 V/µs and 1 GHz bandwidth), able to drive the VCSEL. Finally the pulses are injected through a decoupling capacitor used to separate the bias.

Figure 7.18: Schematic of the optical transmitter implemented with a discrete VCSEL 7. Trigger Interface Board. 165 Figure 7.19: Schematic of optical receiver designed with a discrete photodiode 166 7. Trigger Interface Board.

The design of the receiver is somewhat more complicated. The photodiode chosen was the S5973-01 from Hamamatsu [150], also with 1 GHz bandwidth and assembled into the LC housing by AFE. First the current signal from the photodiode is introduced into a PACTA [95] transimpedance amplifier. The output of the PACTA is a differential voltage signal, which is converted into single- ended with an AD8009 configured as a substractor (the scheme is similar to the one described in section 4.2). Then the single-ended output is compared with a threshold with an ADCMP604, which generates the LVDS output. All the receiver circuit is shown in figure 7.19

7.4.3 External delays

As it was previously explained in sections 7.2.1.3 and 7.4.4.1, the camera trigger at the output of the TIB must be generated a long9 and fixed time after the local Level 1 trigger arrives. This delay must be as accurate as possible to know in which cells of the analog memory buffer the signal is. These requirements for the Delayed local signal make inadvisble to delay it with the flip-flop chains described in 7.4.4.2: first because the accuracy with those delay lines can not be better than 2.5 ns, and second because it would be a waste of logic resources for a delay which, in principle, does not need to be programmable. Several options have been tested to implement the long asynchronous delay:

• The most obvious way to implement a long delay is to use a long transmission line. Using an optical link like the ones described in section 7.4.2 and a long optical fiber, it should be possible to obtain a very accurate fixed delay. However, this solution would be very bulky because a reel of around 500 m of optical fiber would be required for each telescope.

• The programmable delay line 3D3428-15 from Data Delay Devices inc. [151] can add delays of up to 3825 ns in steps of 15 ns, in a single chip.

• The chip DS1123L-200, from Maxim Integrated [152], is able to add a delay of 512 ns in steps of 2 ns. So, a chain of 8 of this chips connected in cascade, should be able to add up to 4 µs.

The possibility to use external chip delays was studied in depth during the first steps of the TIB design. Both delay chips were found to introduce long delays, with a fine precision, high accuracy, low jitter and good stability, according to their data sheets. The 3D3428-15 was preferred, but there were no stock in Europe for this chip, so a chain of 8 DS1123L-200 was included in the first prototype of the TIB. Whatever the solution, it must be tested and characterized, specially in which respects to jitter, as shown in section 7.5.10.

7.4.4 FPGA and firmware

Both the interfacing and the stereo trigger functions consist of properly managing fast digital trigger pulses: replicating, delaying, looking for coincidences, counting, etc. These kind of functions are the typical ones which can be performed by an FPGA, so this technology appeared as the natural option to develop the logic of the TIB. As the FPGAs are programmable devices, they do not only provide with a high performance, but also with a great flexibility. Thus, the firmware installed in

9around 3 µs 7. Trigger Interface Board. 167 the FPGA can evolve with the aim of improving or implementing new functionalities as the ones commented in section 7.3. The FPGA chosen for the TIB was the Xilinx Artix-7 X7A100T-3FGG676 (figure 7.20, [153]) for several reasons:

• It belongs to the newest FPGA Series at the moment of developing the TIB, which means more time until it will become obsolete. As the CTA telescopes will have to work during 20 years, this is an important point.

• The Artix 7, being the less powerful FPGA family of the 7 Series, is the most suitable for the TIB, which does not require very high computing power. On the other hand, Artix 7 family is optimized to reduce its power consumption, which is important for all the systems installed in the camera.

• Despite the TIB does not need high computing power, it requires high speed, specially to implement accurate programmable delays as will be described in subsection 7.4.4.2. The standard synchronous logic inside the selected FPGA can work with clock frequencies as high as 500 MHz.

• The selected FPGA has 676 pins, which can be very useful to manage additional interfaces to implement advanced features.

Figure 7.20: Xilinx Artix-7 FPGA

The firmware running in the FPGA contains several logic modules implemented in VHDL. The code can be consulted in [154], but in the following subsections a high level description of the most important modules is presented.

7.4.4.1 High level architecture

Figure 7.21 shows a general scheme of the firmware modules implemented in the FPGA. Some functions are programmed directly using libraries provided by Xilinx [155]. For instance, the local Level 1 trigger input is replicated to be sent to the neighbours by using the FPGA input and output buffers. In a similar way, the internal clock frequencies (4 KHz, 50 MHz, 100 MHz and 400 MHz) are obtained from the external 10 MHz input clock by means of the internal PLLs [156], properly 168 7. Trigger Interface Board. configured with the Xilinx Core Generator [157] and one simple frequency divider. Nevertheless most of the specific functions of the TIB require the development of specific firmware modules.

400 MHz 100 MHz Input 0 10 MHz PLLs 50 MHz arraytrig 4 kHz pedestals Trigger calibration Collector output Delayed_local Trigger type Delay Stereo Stretchers Inputs 0..7 Lines Logic External Delay

control Output 0 Optical Output 1 Trigger ITR Output 2 output links counters Output 3 Slow Input 0 control Output 4 Control Output 5 Output 6 Thermometer SPI link from/to Raspberry Pi Output 7

Figure 7.21: TIB firmware architecture

The stereo logic involves 3 logic modules. First, the local Level 1 trigger input from the central backplane and the inputs from the neighbour telescopes (up to 8) are delayed a programmable num- ber of clock cycles to compensate the delays due to the cable lengths and the pointing direction, as was mentioned in section 7.2.1. The 9 delayed signals are then connected to 9 programmable stretchers, which extend the duration of the trigger pulses until making them as wide as the coin- cidence window. Then, the delayed and stretched trigger inputs are sent to the stereo logic module which has a counter which is able to provide the number of active inputs for every rising edge of the 400 MHz clock. If the count is greater than a programmable trigger condition, a stereo trigger will be generated. However, to be consistent with what was explained in section 7.2.1.3, the camera trigger pulse is not generated just when the condition is accomplished but it is synchronized with a delayed copy of the local input named “Delayed local” in figure 7.21. Once the stereo trigger is generated in the stereo logic module, it is sent to the collector, which is essentially an OR gate that generates a trigger output when the stereo trigger or other input is active. Depending on the input that caused the trigger output, the collector module generates the corresponding trigger type which is sent to the central backplane and to the clock board as described in section 7.1.1. With the aim of being also able to work only with local triggers in mono mode, or to disable the different trigger inputs, the collector also receives a mask to enable/disable each input. The delay for each input, the coincidence window, the trigger condition and other parameters are configured by the slow control module, which receives these parameters from the Raspberry Pi through an SPI link. Additionally, the trigger inputs and the trigger output are sent to a set of counters which monitor the trigger rates. These rates can be read by the slow control module, 7. Trigger Interface Board. 169 providing with valuable feedback to select the thresholds, choose a suitable trigger condition or to detect failures. Finally, the slow control module is also able to monitor and control the status of the optical links, to configure the external delay and to monitor also the temperature from a chip thermometer. The following subsections explain some technical details of the most complex modules:

7.4.4.2 Programmable delay lines

The programmable delay lines used to delay each input a different amount of time, are based on chains of flip-flops as the one shown in figure 7.22. With every clock cycle, the signal present at the input of each flip-flop passes to the output. So an input pulse requires as many clock cycles as flip-flops in the chain to go through all the flip-flops and reach the output. This means that, with this structure, the amount of delay is as accurate as one clock cycle, so high clock frequencies are required to get a fine delay tuning. A clock frequency of 400 MHz was chosen, obtaining a resolution of 2.5 ns in the delay adjustment. Additionally, the input pulses do not reach the output exactly after N · Tclk ns, but introducing certain jitter. This jitter results from the fact that the flip-flop outputs can only be updated synchronously with the clock leading edge, while the input pulses can happen at any time. Thus, the input pulse will reach the output of the first flip-flop after an unknown amount of time between 0 and 2.5 ns depending on the arrival time of the input pulse with respect to the rising edge of the clock. Nevertheless, as the delayed outputs from the delay lines are only used to check for coincidences inside a time window of several tens of nanoseconds, and the camera trigger output is synchronized with the local Level 1 trigger, an uncertainty lower than 2.5 ns is not very harmful for the trigger performance. It is also worth to mention that the input pulses will never be narrower than 2.5 ns, so they will always be captured by at least one leading edge of the clock.

GRB GRB GRB GRB IN D Q D Q D Q D Q OUT

CLR Q CLR Q CLR Q CLR Q CLK

Figure 7.22: Delay line implemented with a chain of flip-flops

The delays introduced by the delay lines can be as long as 4000 ns, which means that the chains should have at least 1600 flip-flops. The first obvious solution to be able to select every possible amount of delay is to connect each flip-flop output to the input of a 1600-input multiplexer. Such a multiplexer does not exist inside the FPGA, so it should be implemented as a multilevel hierarchy of 8 and 4-input multiplexers. A complicated structure like that is not a good solution from a timing point of view, because the output signal from the selected flip-flop would have to go through many multiplexers in cascade and reach its destination in a single clock cycle. So in order to avoid the 1600-input multiplexer, a logarithmic structure like the one shown in figure 7.23 was designed. The amount of delay which should be added by the delay line is configured by the slow control module by means of a 12 bits word. So, every bit set to “1” introduces a delay correspondent to 2p clock cycles, being p the position of the bit in the 12 bits word. If the flip-flops in the chain are set 170 7. Trigger Interface Board.

IN 9 2 cycles 28 cycles 27 cycles 2 cycles 1 cycle OUT

Bit 9 Bit 8 Bit 1 Bit 0

Figure 7.23: Logarithmic delay line in subchains of powers of 2 units as shown in figure 7.23 and the bits of the control word are used to connect these subchains to the signal path or to bypass them, the output of the chain provides with the desired delayed output, just with 11 2-inputs switches. Only 11 from the 12 bits of the delay word are used, providing with an adjustment capability of up to 2048 clock cycles (i.e. 5120 ns at 400 MHz). Moreover, as the longest delays can only be applied to the local input (the inputs from the neighbours have an inherent delay due to the travel through the optical fibers), the delay lines used in the neighbour inputs only use 10 bits and comprise 1024 flip-flops instead of 2048, saving logic resources.

7.4.4.3 Stretchers

The stretchers are used to make the pulses coming from the delay lines as wide as the coincidence window. The duration of the coincidence window is programmable by means of a 6 bit number configured by the slow control module, which expresses the duration in clock cycles. The stretchers use the same 400 MHz clock used for the delay lines, so the finest resolution is limited to 2.5 ns. In fact, the stretchers use a delay line like the ones described in section 7.4.4.2 to produce the stretching, but with 6 bits instead of 10 or 11. A copy of the input pulses is sent to the input of this delay line, obtaining at the output a delayed signal. Both the delayed signal and the original input feed the state machine shown in figure 7.24.

Input = 1

State 0 State 1 Output = 0 Output = 1

Input = 0 & Delayed = 1

Figure 7.24: Diagram of the state machine running in the stretcher modules

After the FPGA reset, the state is 0, as well as the output of the stretcher. When the input changes to “1”, the state machine changes to State 1, and the output changes immediately to “1”. This situation remains until the delayed input coming from the delay line changes to “1” and only if the non-delayed input has already changed to “0”. This means that:

• If the input is narrower than the coincidence window (as usually expected), the output pulse width is the coincidence window duration.

• If the input is wider than the coincidence window, the output width is similar to the input width. 7. Trigger Interface Board. 171

If the input pulses arrive at the stretchers separated by less than the coincidence window width, this scheme does not work properly, so that the system can consider several close input triggers as a single one, or to produce outputs shorter than the coincidence window. This situation would mean that a high pulse rate is present at the output of the stretchers, which will be detected by the ITR counters (see section 7.4.4.6), which in turn will be read by the slow control system, which will take the appropriate measures.

7.4.4.4 Stereo Logic

The delayed and stretched inputs from the local and the neighbour telescopes are sent to the Stereo Logic module, which generates a stereo output if the trigger condition is accomplished. The trigger condition consists of having coincident triggers in the local telescope and in one or more neighbours during the coincidence window. This is implemented by connecting the inputs to a fast counter which provides, with every leading edge of the 400 MHz clock, the number of inputs which are set to “1”. The result of the counter is expressed as a 4 bits number, which is compared with the number of coincident triggers required to satisfy the trigger condition. The trigger condition can be reconfigured in a very simple way, just modifying this number by slow control. If, besides satisfying the required number of coincidences, one of the coincident inputs is the local one, the signal named “Stereo trigger” in figure 7.25 is generated.

Delayed and Delayed stretched Stereo Count _stereo_ inputs trigger > trigger trigger Counter condition? State Armed Machine Stereo Output Delayed local

Figure 7.25: Stereo logic block diagram

However, as was previously said in subsections 7.4.4.1 and 7.2.1.3, the Stereo Output cannot be simply generated when the stereo trigger condition is accomplished. Instead, it must be generated a fixed time after the local trigger, i.e. synchronized with the signal named “Delayed local” in figures 7.21 and 7.25. To do this, the Stereo trigger signal is sent to a programmable delay line as the ones described in section 7.4.4.2 and, once delayed it feeds a state machine which generates an “Armed” output. When this Armed signal is set to “1”, a stereo output is generated when Delayed local appears. The delay line is required to set Armed = 1 only some tens of nanoseconds before the expected arrival of Delayed local. Of course it is impossible to know accurately when the stereo trigger condition is going to be accomplished and therefore when Armed is going to be set to one (it can happen at any time inside the coincidence window). However, what it is possible is to know how much time the local trigger is being delayed in the Programmable Delay Lines module to compensate the neighbour’s delays before checking for coincidences and how much delay is introduced in the Delayed local path. Thus, introducing an additional delay of Tstereotrigger ns, calculated according to equation 7.8, it is possible to ensure that Armed will be set to “1” between Tcoincidencewindow + Tsecuritymargin ns and Tsecuritymargin ns before the arrival of Delayed local. 172 7. Trigger Interface Board.

Tstereotrigger = Tdelayedlocal − Tcoincidences − Tcoincidencewindow − Tsecuritymargin (7.8)

Figure 7.26 illustrates this calculation. If Stereo trigger is not delayed, Armed could be activated a long time before the arrival of the corresponding Delayed local pulse and this could cause the acceptance of previous local triggers which did not comply with the coincident condition as stereo ones. On the contrary, if Armed is set to “1” just a few nanoseconds before the time at which Delayed local is expected, is very unlikely that a local trigger different from the one which caused the coincidence could be accepted.

Delay introduced to Additional delay Armed gets compensate applied to activated Security neighbour’s delay stereo_trigger during this margin time Tcoincidences Tstereo trigger Tcoincidence window

TDelayed _local Fixed delay applied to Delayed_local

Figure 7.26: Stereo trigger delay scheme

1 = D r Armed e e g la ig Armed = 1 ye tr d _ _ o lo re c te a s l _ = d 1 e y la e D

Waiting Shooted Armed = 0 Armed = 0

Delayed_stereo_trigger = 0

Figure 7.27: State machine which controls the generation of the Armed signal

Regarding the state machine which controls the activation of the Armed signal, its scheme is shown in figure 7.27. It is more complicated than just setting Armed to “1” when Delayed stereo trigger arrives, with the aim to produce only one stereo trigger when the trigger condition is accom- plished during a long time. Thus, starting from the waiting state, it changes to armed when delayed stereo trigger appears. Then, when Delayed local arrives and generates the Stereo Out- put the state changes to shooted, setting Armed to “0”. In this state, Delayed stereo trigger must be “0” to make the state machine go back to waiting state and then being ready to get armed again. 7. Trigger Interface Board. 173

So, if the trigger condition is fulfilled during a long time, the state machine remains in shooted state, avoiding several triggers to be generated for a single long event.

7.4.4.5 Collector

The Collector module implements the interfacing function with the different trigger origins, generating the trigger output signal every time a trigger comes from any of the inputs. Thus, the trigger output is implemented in a simple way with a 5 input OR gate and an AND gate, as it is shown in figure 7.28.

Stereo Output calibration Trigger pedestals Output arraytrig

Input 0 Mono trigger

Figure 7.28: Trigger output generation in the collector module

The AND gate allows to generate a trigger output directly from the local telescope trigger (Input 0 signal), whenever the mono trigger mode is selected, as will be the case in the MSTs. It is important to notice that, whatever the input, the trigger output is generated in a completely asynchronous way, keeping the timing information in the leading edge of the trigger output and introducing very low (24ps RMS). For the trigger type generation, the input trigger signals are copied and stretched in order to work with them synchronously with the state machine of figure 7.29.

Trigger Output = 1 & Last_Trigger_Output = 0

State State waitting transmitting TXStart = 0 TXStart = 1

TXDone = 1

Figure 7.29: State machine which controls the generation and transmission of the trigger type information

When the stretched copy of the trigger output signal changes from “0” to “1”, the 3 bits of the trigger type corresponding to the effective triggering input are calculated, and then a signal called TXStart is set to “1”, indicating to the SPI module10 that there are data to transmit. From this moment, the state machine ignores the possible new triggers, remaining in the transmitting state

10The SPI module is a free implementation. 174 7. Trigger Interface Board. until the SPI module finishes transmitting the trigger type. Then, The SPI sets to “1” a signal named TXDone, indicating to the collector module that it is ready to accept new transmissions. It is worth to say that the collector state machine works with the 400 MHz clock, evaluating the different variables every 2.5 ns, while the SPI module receives a 50 MHz clock for its state machine, sending the bits at 10 MHz.

7.4.4.6 ITR counters

The Individual Telescope Rate (ITR) counters are a set of counters in charge of counting the number of input triggers from each telescope (local and neighbours), as well as output triggers, during a certain period of time, with the aim to provide the slow control module with information to calculate the trigger rates. The trigger rate monitoring is very important to set the Level 1 thresholds and the trigger condition to the lowest possible levels, while maintaining the trigger rate below the maximum telescope readout rate11. The design of digital counters entails a compromise between the number of bits of the counter and the maximum counting speed. As it has been represented in figure 7.30, the counter is composed by a chain of 2 bit adders. The time between one addition and the next one must be long enough to allow a carry bit to ripple through the whole chain of full adders and to have the result ready at the input of the counters to start the next addition. Thus, the more bits in the counter, the longer the time required to propagate the carries and the lower the maximum frequency at which the counter can work12.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Input Half Carry 67 Full Carry 56 Full Carry 45 Full Carry 34 Full Carry 23 Full Carry 12 Full Carry 01 Full pulse Adder Adder Adder Adder Adder Adder Adder Adder 7 6 5 4 3 2 1 0

Out 7 Out 6 Out 5 Out 4 Out 3 Out 2 Out 1 Out 0

Figure 7.30: Structure of an 8 bit ripple-carry counter

In the particular case of the ITR counters, the inputs will be separated by some µs during normal operation (i.e. the expected trigger rates are below 1 MHz). If the counters are fed with the input pulses after going through the stretchers, the pulses to be counted will be long enough to allow the counters to work at lower frequencies, and therefore to reach higher ranges. The coincidence window, and the correspondent pulse width of the stretched pulses will be around 50 ns, but it is programmable so, in order to have some safety margin, a minimum pulse width of 10 ns has been considered. Assuming this condition, the counters have been designed to have 8 bits and being updated at 100 MHz. Every 10 ns each counter checks if its input has changed from “‘0” to “1”. If so, they increment the account, otherwise they do nothing. In principle, the counters are read-out and reset to 0 every 250 µs (4 kHz rate), so they are useful to monitor rates between 4 kHz and around 1 MHz. If the rate is higher, the counters maintain their

11Limited by the dead time 12For this reason it is not possible to implement the delay lines described in section 7.4.4.2 by counting the number of clock cycles. 7. Trigger Interface Board. 175 maximum value (28 − 1 = 255), so the slow control module will know that the rate is too high and it will take the appropriate actions. If it were required to measure higher or lower trigger rates, it would be possible to do it just by changing the frequency at which the counters are read and reset.

7.4.4.7 SFP control

The optical links used to send and receive triggers to/from the neighbours, as well as the cali- bration and pedestal signals, are implemented in the first TIB prototype by means of TX/RX SFP modules [146], which provide with several bits to monitor and control the link status:

• TX Disable: When the FPGA sets this bit to “1”, the optical transmitter is switched off.

• TX Fault: If a laser fault happen, the SFP module sets TX Fault to “1”, and disables the laser.

• RX LOS: A Loss of Signal (LOS) bit indicates that the received optical power is too low to recover the signal, due to a disconnected or broken fiber, switched off transmitter or other reason.

The SFP control module simply gathers all these bits from all the SFP modules, forming words which can be read by the slow control module. Additionally, it generates a generic alarm signal directly connected to the Raspberry Pi if any of the control bits is indicating a failure. In this way, the slow control module does not need to read the SFP status periodically, but only when a problem is detected.

7.4.4.8 External delay control

In the first TIB prototype, the external delays described in section 7.4.3 are implemented with a chain of Maxim DS1123LE-200 [152] programmable delay chips. These chips need to be configured by sending an 8-bits word to each chip through an SPI link. All the chips share the clock, MISO and MOSI lines, while they have independent chip selects. With the aim to handle these links and send the configuration information properly, a firmware module was implemented. This module receives from the slow control nine 8-bit words (one for each chip) and a signal indicating when the configuration of all the chips must be updated (Write ex dels). When the updating command arrives, the module sends the 8-bit word to one chip after the other until programming all of them. Figure 7.31 shows the state machine of the firmware module. The process of updating the configuration uses a variable n to select each chip. Thus, when com- ing from Waiting state, the chip corresponding to n=0 is updated in the Writing state (TX start=1 starts the SPI communication). Then, when that message has been sent, TX done changes to “1” and the state changes to Handshaking. This state increments n and in the next step the state changes to Writing again to send the configuration message to the next chip. The process is repeated until programming all the delay chips. Then the state comes back to Waiting. With the aim to initialize all the chips with a known value after the reset of the system, the state is set to Writing instead of Waiting, so the initial values are loaded. 176 7. Trigger Interface Board.

Reset = 0 Reset

Writing 1 T X = TX_start = 1 _ ls d e o d n _ e x e = _ n 1 te ≤ ri a W m o u n t_ e x d e lc Hand h Waiting ip s Shaking TX_start=0 TX_start=0 n=0 n=n+1 n > amount_exdelchips

Figure 7.31: External delay control state machine

7.4.4.9 Thermometer

The trigger interface board is equipped with a TC77 [158] chip thermometer, readable by a SPI interface. The thermometer firmware module is in charge of controlling this SPI interface, reading the temperature every 250 µs and writing the data in a register accessible by the slow control module.

7.4.4.10 Slow control module

The Slow Control firmware module implements an slave SPI interface which allows the Raspberry Pi to read and write 32 bit words. These words are composed of an 8-bit prefix which defines what information is being read or written and 24 data bits. Table 7.2 contains the different codes and the data corresponding to each one.

Prefix Data bits Information Read/written by the Raspberry Pi 0x00 0x01 12 LSB Local trigger delay, in clock cycles Written 0x02 12 LSB Neighbour 1 trigger delay, in clock cycles Written 0x03 12 LSB Neighbour 2 trigger delay, in clock cycles Written 0x04 12 LSB Neighbour 3 trigger delay, in clock cycles Written 0x05 12 LSB Neighbour 4 trigger delay, in clock cycles Written 0x06 12 LSB Neighbour 5 trigger delay, in clock cycles Written 0x07 12 LSB Neighbour 6 trigger delay, in clock cycles Written 0x08 12 LSB Neighbour 7 trigger delay, in clock cycles Written 0x09 12 LSB Neighbour 8 trigger delay, in clock cycles Written – – – – 7. Trigger Interface Board. 177

0x11 12 LSB Output trigger duration, in clock cycles Written – – – – 0x20 7 LSB Coincidence window, in clock cycles Written 0x21 4 LSB Trigger condition, in number of coincidences Written 0x22 8 LSB If =0xFF, mono trigger enabled Written 0x23 12 LSB Additional delay Tstereotrigger, in clock cycles Written – – – – 0x30 8 LSB Stereo count, for rate monitoring Read 0x31 8 LSB Local trigger count, for rate monitoring Read 0x32 8 LSB Neighbour 1 trigger count, for rate monitoring Read 0x33 8 LSB Neighbour 2 trigger count, for rate monitoring Read 0x34 8 LSB Neighbour 3 trigger count, for rate monitoring Read 0x35 8 LSB Neighbour 4 trigger count, for rate monitoring Read 0x36 8 LSB Neighbour 5 trigger count, for rate monitoring Read 0x37 8 LSB Neighbour 6 trigger count, for rate monitoring Read 0x38 8 LSB Neighbour 7 trigger count, for rate monitoring Read 0x39 8 LSB Neighbour 8 trigger count, for rate monitoring Read – – – – 0x40 10 LSB SFP enables Read 0x41 10 LSB SFP TX Fault Read 0x42 10 LSB SFP LOS, Loss of Signal Read – – – – 0x50 13 LSB Temperature Read – – – – 0xF0 8 LSB Unknown prefix Read Table 7.2: Slow control registers

When an SPI message is received and its prefix does not correspond to a defined one, the slow control module sets an alarm line directly connected to the Raspberry Pi to “1”, and writes the unknown received prefix in the 0xF0 address. In this way, the Raspberry Pi can read what was received, which can be useful for debugging. Another useful function of the slow control module is to write the initial values of the different parameters, before receiving them from the Raspberry Pi. This allows to test the different func- tionalities, even without the Raspberry Pi (see section 7.4.5.2). With the aim to have the updated information about the slow control always accessible, a wiki page has been created [159].

7.4.5 Raspberry Pi

The TIB contains a Raspberry Pi micro-computer (figure 7.32), which is in charge of the FPGA configuration during the booting of the system and the slow control communication. In spite of its small size and very low price13, the Raspberry Pi is a complete PC running a Linux operating

13Around 30 €at the time when this thesis was written. 178 7. Trigger Interface Board. system14 which is stored in an SD card used as hard disk [160]. It has several buses: two USBs, one RJ45, several general purpose pins, one audio connector and even an HDMI. In the case of the TIB, the Ethernet interface will be used to communicate with the camera slow control system, while the General Purpose Input/Output (GPIO) pins are used to interface with the FPGA.

Figure 7.32: Photograph of a Raspberry Pi micro-computer

7.4.5.1 Interface with the FPGA

The Raspberry Pi have 26 pins in its GPIO interface, assigned to different signals as shown in table 7.3. The signals can be divided in several groups:

• SPI MOSI, SPI MISO, SPI clock, SPI Chip Select 0 (CS0) and SPI Chip Select 1 (CS1) constitute an SPI interface able to control two SPI devices. In fact, all the lines are connected to the FPGA: CS0 is active during the transmission of the FPGA configuration file in the initialization (see section 7.4.5.2), while CS1 is used during the transmission of the slow control parameters. In both cases the Raspberry Pi is the master, while the FPGA is the slave device, which means that the clock is generated by the micro PC.

• I2C serial data (SDA) and I2C clock implement an I2C standard link connected to the FPGA. This interface is not currently used, but the lines are reserved for future uses.

• UART TX and UART RX can be used to implement a serial communication interface between the Raspberry Pi and the FPGA. As in the case of I2C, it is not currently used but reserved for future uses.

14We choose the most popular distribution optimized for Raspberry Pi, called Raspbian [161] 7. Trigger Interface Board. 179

Pin Function Pin Function 1 +3.3 V Power supply 2 +5 V Power Supply 3 I2C[162] Serial Data 4 +5 V Power Supply 5 I2C Clock 6 Ground 7 SPI error 8 UART15 9 Ground 10 UART receiver 11 Reset out 12 Program B 13 Temperature alarm 14 Ground 15 SFP alarm 16 INIT B 17 +3.3 V Power supply 18 DONE 19 SPI MOSI 20 Ground 21 SPI MISO 22 RESET 23 SPI clock 24 SPI Chip Select 0 25 Ground 26 SPI Chip Select 1

Table 7.3: Raspberry Pi GPIO pinout

• PROGRAM B, INIT B, RESET and DONE are used during the initialization. See section 7.4.5.2

• Programmable inputs are used for managing alarms.

• Pin 11 is a programmable output used for resetting the default values in the FPGA.

• +5 V is an input power supply, while +3.3 V is an output power supply for low power de- manding devices.

7.4.5.2 FPGA-initialization

The Xilinx Artix 7 FPGAs can be configured in different ways. Taking advantage of the presence of the Raspberry Pi, the so called “slave serial mode” has been chosen [163]. According to this configuration scheme, the Raspberry Pi sends the firmware to the FPGA during the initialization by means of an SPI interface. Figure 7.33 shows the connections between the Raspberry Pi (labeled as Microprocessor or CPLD), the FPGA and the JTAG connector. CCLK, DIN and PROGRAM B correspond to the 3 typical SPI lines, clock, data and chip select respectively. The Raspberry Pi plays the role of master in this communication, generating the clock. The JTAG connector provides with an alternative and effective way to load the firmware in the FPGA and run tests. In the first prototypes of the TIB an external JTAG connector is present in the front of the box with the aim to debug problems. In the final Trigger Interface Boards it will be an internal connector.

7.4.5.3 Interface with the slow control unit

The Raspberry Pi is in charge of communicating with the central camera slow control unit, using the Ethernet camera network. This interface requires coordination with several CTA teams working 180 7. Trigger Interface Board.

Figure 7.33: Slave serial mode FPGA configuration scheme [163] on this issue and it was still under definition by the time this thesis was written. However, some guidelines have been given to develop the slow control software. The most important decision has been to use OPC-Unified Architecture [164] as the base communication architecture. OPC-UA works efficiently to control different parts, whether they are simple or complex, and is multiplattform, offering different APIs for software development. The Raspberry Pi will run an OPC-UA server implementation for the Java virtual machine.

7.4.5.4 Other functions in the Raspberry Pi

Apart from interfacing the FPGA and the camera slow control system, the computing power of the Raspberry Pi is very useful to perform certain functions and calculations locally, reducing the workload of the camera slow control. Some of these additional functionalities are:

• Calculation of the number of clock cycles that every trigger input must be delayed, depending 7. Trigger Interface Board. 181

on the pointing direction. The camera slow control can send the pointing direction or directly the delay in ns, and the Raspberry Pi calculates the delays in clock cycles.

• Centralization of the alarms. The Raspberry Pi checks periodically the trigger rates, the status of the optical links and the temperature, warning the central slow control only if necessary.

• SSH accessibility, useful for debugging.

7.4.6 Power supply

The Trigger Interface Board receives a single +24 V DC power supply from the camera power supply system. From this voltage, the power must be provided to the different subsystems, which require different supply voltages. Table 7.4 shows the power consumption requirements of the dif- ferent active hardware elements. In order to satisfy the power requirements efficiently, a two levels power supply system has been designed, according to the diagram shown in figure 7.34.

+24 V Thermometer +5 V Switched Raspberry Pi Delay lines Power Supply LVDS to PECL +3.3 V translators Switched Power Supply Optical +2.5 V +1.8 V +1 V transceivers Linear Linear Linear Power Supply Power Supply Power Supply

FPGA Artix 7

Figure 7.34: Block diagram of the TIB power supply system

As the most demanding power supply voltages are the +5 V and the +3.3 V, two switched DC-DC modules have been used to generate them from the +24 V general supply. This first step from +24 V must be done with switched DC-DCs because the voltage drop is too high to use linear regulators efficiently. On the other hand, the +2.5 V, +1.8 V and + 1 V are generated from +3.3 V by means of less noisy linear regulators. The Trigger Interface Board is not very sensitive to the noise in the power supply because it is a digital design where the most important signals are differential, so the switched noise introduced by the DC-DCs is not critical. Nevertheless, the noise in the power supplies has been measured and the results are shown in section 7.5.1.

The different power supply modules have been designed with the Webench Power Designer on- line tool from Texas Instruments [165]. Their schematics, as well as the schematics of all the TIB hardware modules can be seen in appendix A.2. Table 7.5 summarizes the most important characteristics of the designed power supplies. 182 7. Trigger Interface Board. +1V 73 mA 73 mA 73 mA +1.8V 191 mA 191 mA 239 mA +2.5V 393 mA 393 mA 982 mA 21 mA 0.4 mA +3.3V 420 mA 732 mA 270 mA 2460 mA 4083 mA 13475 mW +5V 700 mA 700 mA 3500 mW 1 1 9 1 12 12 12 Quantity +1V 73 mA +1.8V 191 mA +2.5V 393 mA 21 mA 35 mA 61 mA 30 mA 0.4 mA +3.3V 220 mA Total current flowing (mA) Table 7.4: Expected power consumption according to datasheets and FPGA simulations Total power consumption (mW) +5V 700 mA TC77 Artix 7 DS1123L Transceiver Raspberry Pi Component SN65LVDS100 SN65LVDS101 7. Trigger Interface Board. 183

Output Maximum power Type output Efficiency voltage current +5 V Switched 1 A 84 % +3.3 V Switched 6 A 93 % +2.5 V Linear 500 mA 75 % +1.8 V Linear 300 mA 54 % +1 V Linear 250 mA 30 %

Table 7.5: Characteristics of the power supplies modules

Taking into account the efficiencies of table 7.5 and the power demands of table 7.4, the global power consumption of the TIB can be estimated according to equation 7.9.

I · 2.5V I · 1.8V I · 1V  1 I · 3.3V I · 5V Power consumption = 2.5 + 1.8 + 1 · + 3.3 + 5 = 21.009 W η2.5 η1.8 η1 η3.3 η3.3 η5 (7.9)

7.4.7 Temperature monitoring

The Trigger Interface Board includes a TC77 thermometer chip [158], which is read by the FPGA as was explained in subsection 7.4.4.9. Contrary to what it could be expected, the components with the most restrictive operating temperature range are not the transceivers (which have a VCSEL) but the Raspberry Pi [160], the FPGA [153] and the programmable delay lines DS1123LE [152]. Table 7.6 gathers the operating temperature range of the different components, showing an overall temperature range between 0 and +70 ◦C. The delay line is the most restrictive element, but it is still not clear if the DS1123L will be present in the final versions of the Trigger Interface Board. Taking into account the temperature limits from table 7.6 and the temperature measured with the sensor, it will be possible to operate the camera cooling system [108] between safety margins.

7.4.8 TIB PCB design

The TIB is a complex board which needs to handle many input and output signals, which in many cases consist of differential pairs. First, there are 24 differential pairs to and from the optical links, and other 32 differential pairs connected to the RJ45 connectors. Additionally, there are single- ended lines for the optical links monitoring, 15 lines for the communication with the Raspberry Pi, 12 for the control of the external delays implemented with the DS1123L and still some more for the JTAG interface and the reading of the thermometer. So many lines connected to the 676 pads FPGA, together with the different power supply rails described in section 7.4.6 required a complex 16 layer PCB design (figure 7.35) which was developed with Altium Designer [166]. The PCB design considered several restrictions such as the delay equalization of the lines coming from the neighbours, the controlled impedance of the differential pairs, the coupling between adjacent lines or the noise from the power supplies. Additionally a 3D model of the board (figure 7.36(b)) 184 7. Trigger Interface Board.

Component Minimum Temperature (◦C) Maximum temperature (◦C) Raspberry Pi 0 +85 Avago AFBR5715 ALZ -40 +85 SN65LVDS100/101 -40 +85 Xilinx Artix 7 FPGA 0 +100 TC77 thermometer -55 +125 LP36890DT-2.5 -40 +125 LM22672MR-5.0 -40 +125 CDCV304PWRG4 -40 +85 DS1123L-200 0 +70 LP38691DT-1.8 -40 +125 CSD18534Q5A -55 +150 B240A-13-F Schottky Diode -65 +150 LP3878SD-ADJ -40 +125 LM3151MHE-3.3 -40 +125 Ceramic Capacitors -30 + 85 Leds -55 +85 Fuses -55 +125 Inductors -40 +85 Resistors -55 +125 Electrolitic capacitors -40 +85 Tantalum capacitors -55 +105 Global temperature range 0 +70

Table 7.6: Operating temperature range of the electronic components in the TIB

Figure 7.35: TIB prototype PCB stack-up was used to ensure the mechanical compatibility with the rack box. Figure 7.36 shows two views of the board design and a photo of the manufactured prototype. 7. Trigger Interface Board. 185

(a) PCB layout, with the different color lines corresponding to different PCB layers

(b) 3D design

(c) Photo

Figure 7.36: Views of the TIB design and first prototype 186 7. Trigger Interface Board.

7.5 TIB measurements

Two boards of the first prototype of the TIB have been manufactured and tested. The goal of this prototype is to test the different functionalities, to improve the FPGA firmware, to develop the slow control software which will run in the Raspberry Pi and finally to provide with a TIB for several CTA camera integration tests which will take place during 2014. In order to perform the tests, the auxiliary boards shown in figure 7.37 were manufactured.

• Board in figure 7.37(a) simulates the central backplane interface.

• Board in figure 7.37(b) mimics the clock board.

• Board in figure 7.37(c) simulates an optical interface.

• Board in figure 7.37(d) is a generic adapter from RJ45 into SMA connectors.

The first three boards include an MCP2200 chip [167] each one, which can generate input pulses controlled by a computer through an USB interface. The results obtained from these tests and the new requirements requested by the LST and MST camera developers will be taken into account for a second, upgraded, version which should be the one finally installed in the LST and MST cameras. The next sections show the main features tested in the TIB.

7.5.1 Power supplies

The first systems to be tested were the power supplies. They work as expected, providing with enough current for the different subsystems. Table 7.7 contains the measured DC voltage levels and the noise, measured as the AC coupled RMS voltages, corresponding to the different power rails (figure 7.38). The table shows that the measured DC levels are very close to the nominal ones and the noise power is very low. Looking at the numbers it is possible to notice that the RMS voltages is higher in the +5 V and +3.3 V power supplies. This is because these two power supplies are switched ones, in contrast to the others which are generated by means of linear regulators. The only problem related with the power supplies is that the +1 V LED indicator does not shine (figure 7.38(d)) because it was not selected properly and its threshold voltage is higher than 1 V.

Nominal voltage Measured DC (V) Measured AC RMS (mV) +5 V +5.01 4.15 +3.3 V +3.36 5.37 +2.5 V +2.55 1.97 +1.8 V +1.78 2.68 +1 V +1.09 3.74

Table 7.7: Measured DC voltage and AC coupled RMS voltage for the different voltage rails present in the TIB 7. Trigger Interface Board. 187

(a) Board simulating central backplane (b) Board simulating clock board

(c) Board simulating an optical interface (d) Adapter from RJ45 to SMA

Figure 7.37: Auxiliary boards used for the tests of the Trigger Interface Board

7.5.2 FPGA configuration

The next system to be tested was the FPGA. First it was tested through the JTAG interface, observing that the FPGA was properly installed and the communication was possible. The next step was to configure the FPGA with the Raspberry Pi, and this target was also accomplished.

7.5.3 Clock generation in the PLLs

In order to test the different firmware modules running in the FPGA, different frequencies must be generated in the PLLs from the original 10 MHz input clock. In the first tests a problem with the matching of the input clock was found, which made the PLL to consider clock reflections as clock cycles and at the end to generate higher output frequencies than expected. The problem was caused because the Xilinx core generator does not activate the internal termination of the input buffer, represented in figure 7.39. Once the problem was found, it was corrected by activating the termination explicitly in the VHDL code and the output frequencies were the expected ones. 188 7. Trigger Interface Board.

(a) +5 V and +3.3 V AC RMS measurement (b) +2.5 V and +1 V AC RMS measurement

(c) +1.8 V AC RMS measurement (d) Power Supply LEDs

Figure 7.38: Measurements of the noise in the power supplies and photo of the failing LED

Figure 7.39: Internal differential clock input buffer and first PLL, in blue

7.5.4 FPGA delay lines

Once the high clock frequencies were available, it was possible to test the other firmware modules. The next ones were the flip-flop based delay lines described in section 7.4.4.2. In order to test them, 7. Trigger Interface Board. 189 a copy of the input and the output of a delay module were directly connected to two spare RJ45 pairs which, after an adapter board like the one shown in figure 7.37(d), were connected to an oscilloscope. Delays from 0 to 1600 cycles (4 µs) were tested, observing a minimum delay of 6.2 ns corresponding to 0 cycles, which behaves as an offset added to the configured delay. This offset is due to propagation inside the TIB, and it does not mean any trouble. Regarding the maximum jitter, it was always limited to around 2.5 ns for all the delays tested, which corresponds to the minimum clock period, just as expected. Figures 7.40 and 7.41 show several delay measurements.

Figure 7.40: 0, 2.5, 12.5, 25 and 30 ns delayed outputs (blue and green) and input (yellow)

7.5.5 Stretchers

The next module to test were the stretchers. As in the case of the delay lines, the output of the stretchers was connected to an spare RJ45 connector in order to measure the width of the pulses. Figure 7.42 contains several measurements showing that the stretcher modules work as expected, i.e. stretching the pulse up to the configured width when the pulse is narrower than the coincidence window, and not changing the output width when the input pulse is wider than the coincidence window width, as it was described in section 7.4.4.3. 190 7. Trigger Interface Board.

Figure 7.41: 4 µs delayed output (green) and input (yellow)

(a) Input width 2.7 ns, configured width 10 ns (b) Input width 2.7 ns, configured width 50 ns

(c) Input width 15 ns, configured width 10 ns (d) Input width 30 ns, configured width 10 ns

Figure 7.42: Several pulse width measurements at the output of the stretchers 7. Trigger Interface Board. 191

7.5.6 Stereo Logic

The tests of the stereo logic were difficult to perform with the oscilloscope because there are many signals involved, and not all of them can be represented in the screen at the same time. The available oscilloscope only have 4 channels and the outputs from the RJ45 connectors consist of differential pairs, so only 2 signals could be simultaneously represented without using the memories. Additionally, measuring the signals involved in the stereo logic outside the FPGA adds additional delays due to the cables, connectors, etc. which can distort the real situation when looking for coincidences. In this situation, it was preferred to use a Xilinx tool named ChipScope [168]. This tool uses the spare resources in the FPGA to implement a virtual logic analyzer, which can be used to see the internal signals, sampling them with an internal existing clock (the 400 MHz one was chosen), triggering with a selectable signal (the local trigger input was chosen) and storing the samples in the RAM blocks existing in the FPGA. By means of this powerful tool, all the internal signals participating in the logic could be represented in a PC like in a logic analyzer. The figures 7.43 and 7.44, in the following pages show several typical situations. Figure 7.43(a) shows a typical situation where a trigger output is generated. The 2nd, 3rd and 4th rows in the figure (inputs< 0 >, inputs< 1 > and inputs< 2 >) correspond to the Level 1 trigger signal coming from the backplane and two Level 1 trigger inputs coming from neighbour telescopes16. These input trigger pulses are delayed and stretched, so 6th, 7th and 8th rows represent the signals coming into the stereo logic module. In real conditions the inputs would show a longer separation in time and the delays required to compensate them would be longer too. For these tests, short delays have been selected in order to see all the signals which are important for the logic in the same screen. In this way, the 9th signal (condition) is set to “1” when the trigger condition is accomplished, which in figure 7.43(a) happens for 3 coincident inputs. The 10th row, named stereo trigger requires condition to be set to “1” and also checks that one of the active inputs is the local one. If this is the case, the stereo trigger signal can be delayed, as will be shown in figure 7.44(b), or not delayed as shown in figure 7.43(a), generating in any case the 11th signal, labelled as delayed local. This signal changes the state of the state machine shown in figure 7.27, which is represented by the signal state FSM FFd, changing from waiting to armed, which means that a stereo trigger output will be generated when the delayed copy of the local input will arrive. This delayed copy is named as delayed local in figures 7.43 and 7.44. When it arrives, the stereo output signal (stereo output) is generated, changing the state from armed to shooted during the trigger output duration and, finally changing to waiting again. The last signal, named Stereo T, represents the trigger output from the FPGA. Figure 7.43(b) shows the signals in a case in which the trigger condition is not fulfilled because there are never 3 coincident signals, and therefore condition is never set to “1”. On the other hand, figure 7.44(a) shows a situation in which the trigger condition requires 2 coincident telescopes, but stereo trigger is shorter than condition because the local trigger is only active during part of the time. Finally, figure 7.44(b) shows a case in which delayed stereo is delayed with the aim to reduce the time during which armed is enabled, reducing the probability of generating a trigger output due to a previous non-coincident local Level 1 trigger.

161st and 5th signals (stereo trigger top/inputs and ../stereo logic/inputs are 3-bit buses containing the decimal representation of signals 2nd, 3rd and 4th or 6th, 7th and 8th respectively 192 7. Trigger Interface Board. (a) Complying condition of 3 coincident trigger inputs (b) Not complying condition of 3 coincident trigger inputs Figure 7.43: Measurements of the signals involved in stereo logic, requiring 3 coincident trigger inputs. 7. Trigger Interface Board. 193 (b) Delayed stereo used to reduce the armed time (a) Complying condition of 2 coincident trigger inputs, but requiring also local trigger Figure 7.44: Measurements of the signals involved in stereo logic, showing local trigger requirement and utility of delayed stereo. 194 7. Trigger Interface Board.

7.5.7 Collector

The collector module inside the FPGA was also tested, obtaining output triggers corresponding to the different trigger inputs. The mask allows to enable or disable the trigger inputs, and the trigger type is generated correctly. Figure 7.45 shows the output corresponding to a software trigger coming from the clock board. The corresponding code “101” is read in the leading edges of the 10 MHz clock. As it was required to represent 3 differential signals with a 4-channel oscilloscope, the trigger output was stored in memory (blue line) and, using it as trigger, the clock and data lines are represented with the yellow and green lines respectively.

Figure 7.45: Trigger output pulse (blue) and trigger type clock (yellow) and data (green).

7.5.8 ITR counters

The ITR counters were also measured, just by setting different input trigger frequencies and reading the accounts, which are updated every 250 µs as it was explained in section 7.4.4.6. The results are gathered in table 7.8, showing that the counters work as expected: As it was expected from their implementation, the ITR counters cannot measure rates with an accuracy better than 4 kHz (because of the updating period), or to measure rates higher than 1.02 MHz, (because they are 8-bit counters). Nevertheless, the current characteristics of the counters are suitable for the expected rates to be measured in CTA.

7.5.9 Optical links

The optical links were implemented in the first prototype with SFP transceivers, like the ones used in optical Gigabit Ethernet networks [146]. These transceivers are easy to control, and very 7. Trigger Interface Board. 195

Input rate (kHz) Counts in a period of 250 µs Measured rate (kHz) 2 0 0 4 1 4 10 2 8 12 3 12 20 5 20 40 10 40 100 25 100 200 50 200 300 75 300 500 125 500 800 200 800 1000 250 1000 1500 255 1020

Table 7.8: Measured rates using the ITR counters adequate for data transmission through cheap OM3 optical fibers in distances of up to 550 m length. However the tests showed that the SFP transceivers were not a suitable option for sending trigger pulses. When testing an optical link, it was observed a high level of noise in the received signal. This was caused because, in the transmitter, the differential LVPECL inputs are AC coupled as shown in figure 7.46. If the signal is changing very fast, like it is the case in the Ethernet signals17, it works properly but, this is not the case of the digital trigger pulses. These trigger pulses sent by the camera telescopes consists of pulses of a few nanoseconds width (around 10 ns), which are sent at a maximum rate of some hundreds of kHz. This means that the baseline is set to “0” during most of the time. Looking at the scheme of figure 7.46, it is easy to understand that the DC levels of such a differential signal are removed by the capacitors, so the DC voltage is the same in the positive and negative inputs of the receiver (points marked as TD+ and TD- in the figure). In this situation, the slightest noise fluctuations are recognized by the transmitter as “0s” or “1s”, sending noisy pulses. Real pulses are effectively sent, but together with thousands of noise pulses.

Figure 7.46: Emitter part of an SFP, transceiver, AC coupled [146].

The solution to this problem will consist of replacing the SFP transceivers of the first TIB

17Optical Gigabit Ethernet uses 8b/10b encoding, which achieves DC balance by mapping 8 bit symbols in 10 bit symbols, where there are never more than 5 consecutive zeros or ones [169]. 196 7. Trigger Interface Board. prototype by analog optical links implemented with discrete VCSELs and PIN photodiodes, as was described in section 7.4.2.2.2. The transceivers have been implemented in test boards and tested with two optical fibers of 2 and 500 m. Figure 7.47 shows the measured signals corresponding to the 2 m link. The purple line was measured with a probe18 with the aim to show that this kind of links can handle pulsed signals properly. On the other hand, figure 7.48 shows the input and output with a 500 m optical fiber, demonstrating that the optical power and the sensibility of the receptor are adequate. The bandwidth is large enough to allow sharp edges and, as a result, the jitter is very low: only 77 ps with the 500 m optical fiber.

Figure 7.47: Inverted copy of the input signal (magenta), received analog signal at the input of the comparator (purple) and LVDS output (yellow) of the analog optical link, with a 2 m optical fiber

7.5.10 External delays

The different ways to implement the external delays described in section 7.4.3 have been tested:

7.5.10.1 Delays with DS1123LE-200

The external delays implemented with the Maxim DS1123LE-200 chips [152] were the option chosen for the first TIB prototype. They were tested and, in fact, used to delay the local trigger

18The length of the probe cable is longer than the one of the cable which connects the LVDS output to the oscilloscope. This is why the LVDS output appears before the analog pulse. 7. Trigger Interface Board. 197

Figure 7.48: Inverted copy of the input signal (magenta) and received LVDS output (yellow) of the analog optical link, with a 500 m optical fiber and generate the delayed local signals shown in figures 7.43 and 7.44. Figure 7.49 shows the result of delaying an input pulse 0, 50, 100, 150 and 200 steps of 2 nanoseconds with only one delay chip, and it can be seen that the delay accuracy is very good and the standard deviation of the jitter is around 20 ps.

However, when longer delays were implemented with a chain of 8 chips in cascade the results were not so good. For a delay of 2.6 µs, a standard deviation of the jitter of 1.4 ns was measured. This jitter is too high, and discards these chips as an option to implement the asynchronous delay of the local input which at the end is used to read the camera, and which should have a jitter lower than 1 ns.

7.5.10.2 Delays with 3D3428

In spite of the difficulties with the supply of this chip, it was finally possible to get a sample and test it. The measurement corresponding to the expected required delay is shown in figure 7.50. As it can be see in the figure, the jitter is much lower than with the Maxim device: for a 2.7 µs delay, the std. deviation of the jitter is 606 ps. Therefore this chip will be the chosen one for the upcoming version of the TIB. 198 7. Trigger Interface Board.

Figure 7.49: Input signal (yellow) and delayed 0 (green), 50, 100, 150 and 200 steps of 2 ns (blue) with DS1123LE-200.

7.5.10.3 Delay with an optical fiber reel

The delay can be implemented with a long optical fiber and the analog optical links described in section 7.4.2.2.2. The measurements shown in figures 7.47 and 7.48 show that this is a feasible option. With the 500 m length optical fiber, a delay of 2.53 µs with a jitter of only 77 ps standard deviation was achieved, which is better than with any existing chip. However, this solution is very bulky and not very feasible to be implemented in an IACT.

7.5.11 Test conclusions

The tests have shown that the first prototype of the TIB can comply with most of the require- ments. Most of the concepts have been successfully tested:

• The stereo trigger and the trigger gathering functions can be implemented in an FPGA, working at 400 MHz.

• A Raspberry Pi is very useful to configure the FPGA and perform the slow control function- alities, avoiding complex Ethernet implementations.

• The delay lines and the stretchers based in flip-flop chains work as expected, with a jitter limited by the FPGA clock frequency. 7. Trigger Interface Board. 199

Figure 7.50: Delay measurement with 3D3428 delay line

• A complex logic has been developed, which can generate trigger outputs which are synchronous with a local Level 1 trigger signal, but not with the FPGA clock.

• The trigger type generation worked as expected.

• The trigger rates can be measured in the FPGA.

• The SPI control of external chips, such as the DS1123L or the thermometer worked properly.

• In spite of the board complexity, no crosstalk problems between lines were observed.

• The designed power supplies add very little noise.

In addition, there are two important points to improve in the next prototype version:

• The optical SFP transceivers must be replaced by the ones based on discrete VCSELs and PiN photodiodes, capable of working with trigger-like pulsed signals.

• The 8 delay chips DS1123LE-200 from Maxim must be replaced by one 3D3428 from Data Delay Devices, with much lower jitter.

Anyway, it must be pointed out that the first TIB prototype fulfils the requirements for the forthcoming integration tests, with only one camera. When the improvements, which are already 200 7. Trigger Interface Board. tested, will be included in the second TIB prototype, it will be possible to accomplish all the requirements of CTA LSTs and MSTs. Chapter 8

Conclusion and Outlook

8.1 Conclusions

During the last four years I have been working at GAE-UCM, together with other Spanish groups from Ciemat, IFAE and UB and in coordination with other foreign institutions, specially from France and Japan, with the aim to build the best possible trigger system for the large and medium sized telescopes of the forthcoming Cherenkov Telescope Array. On the base of our previous knowledge and our experience with the MAGIC telescope, we conceived a system with a great expected performance according to MonteCarlo simulations (see section 3.2), and which is feasible to be constructed and operated.

The proposed trigger architecture follows a multi-level scheme, able to support many of the most powerful trigger techniques: majority trigger, sum trigger, variable trigger region sizes, partial readout, sliding window, two-thresholds strategies, Colibri, PMT transit time calibration, hardware stereo trigger and even software array trigger with the digitized data. Such a global architecture is the result of the collaboration between all the mentioned teams mentioned above. Nevertheless, each group developed a different hardware element: IFAE team designed the Level 0, Ciemat team is in charge of the backplane, UB worked in ASICs and at UCM-GAE we designed the Level 1 and the TIB, which are the core of my thesis.

The Level 1 implements successfully the required functionalities: it combines the inputs from sets of clusters and decides if the camera should be triggered or not. It does it in a very short time, with a negligible jitter, complying with the bandwidth requirement and adding very low noise. It is able to implement the sumtrigger scheme, it supports Colibri (as described in chapter 5) and includes the necessary hardware to implement the delay compensation system described in chapter 6. Several prototypes have been tested with the other systems and the current design is ready for industrial production. Additionally, the development of the Level 1 produced 2 extra-outcomes:

• Usability of microwave techniques and technologies adapted to short pulse handling. The typical spectrum of a PMT output pulse ranges from low frequencies to up to 1 GHz and, at these high frequencies the RF and microwave technologies can be useful. The case of the Wilkinson splitters [6] or the use of Schottky diodes are examples of this. 202 8. Conclusion and Outlook

• Patent of a new family of logic gates, able to work with LVDS and other differential logic standards.

Regarding the TIB, two boards of the first prototype have been designed, manufactured and tested, and the results are very satisfactory. The current TIBs have been able to comply with the very demanding requirements needed to implement the LST hardware stereo logic, gathering the different trigger origins and generating the trigger type. The use of chains of flip-flops in a FPGA have showed the expected performance in the delay lines and in the stretchers, and the Raspberry Pi has been a good solution to implement the slow control communication and to configure the FPGA. Thus, the current prototypes are useful for the single camera demonstrator tests which will take place during this year. Two problems with the optical links and the external delays have been detected, and the solutions are ready to be implemented in the next version of the TIB, which is scheduled to be ready some time before two telescopes will be ready to work together in a stereo trigger scheme. In short, it can be said that the work carried out during these years has made possible to present an excellent trigger system, able to comply with the demanding requirements of CTA LSTs and MSTs.

8.2 Outlook

The CTA project is now at the end of its prototyping phase. From 2014 to 2016, prototypes for large demonstrators and complete MSTs and LSTs will be built, tested and assessed. These complete prototype telescopes will be also used to test and adjust the trigger distribution system, check the accuracy of the different calibration algorithms (flat-fielding, trigger amplitude, delays...) and to finish the implementation of all the details required for the correct data taking, such as those related with the data format, event building, time stamping, slow control, etc. In summary, all the details required to make CTA telescopes work, but which can not be tested without a complete camera, will be implemented and tested in this phase. Additionally, building these first telescopes implies the first industrial production of several elements, such as the camera front-end boards and backplanes, and their assembly in clusters with PMTs. These elements must be tested before being mounted in the camera, according to a quality control protocol which still needs to be defined. Defining the measurements to be done in each step, the acceptable values, and developing the corresponding test setups is an intensive work which also needs to be done in this stage. Part of this work will be subcontracted to companies, but always under the control of the groups which developed the systems. All this work will not leave much time for developing new ideas. However, there are two main innovative lines to be developed, as soon as the other tasks allow us.

8.2.1 Trigger integration in ASICs

One interesting idea, with the aim of reducing the number of components, simplifying the assem- bly, reducing costs and power consumption, is to develop ASICs concentrating the different trigger functionalities. Our partners in ICCUB (Institute of Science of the Cosmos, University of Barcelona) 8. Conclusion and Outlook 203 in Spain and our french colleagues at IRFU (Institut de Recherche sur les lois Fondamentales de l’Univers) have some experience developing ASICS ([58], [95], [98]), so that we (mainly ICC-UB and Ciemat, with UCM and IFAE collaborating in the specification and testing) have taken advantage of their experience and collaboration to design and manufacture ASICs for the trigger. In this way, one ASIC for Level 0 and other for Level 1 have been designed, and a first version produced and tested, while other ASIC for the Level 0 fan-out function is in the design phase. Some functionalities like the ones related with the SPI slow control used in the Level 1 to adjust the threshold levels have been easy to include, because they have been already implemented for NECTAr. However, the ones related with differential to single-ended conversion or the addition of analog signals were more complicated requiring to be redesigned. This was so because several basic functions are easier to implement in an ASIC in a different way from how they are implemented with discrete components. For instance, the Wilkinson splitter functionality can be implemented in a more straightforward way replicating the signals with current mirrors. In general, replicating and adding currents, is preferable when working with ASICs. Regarding the ASICs manufacturing, Europractice [170] has allowed us to share the silicon wafer with other projects, making the prototype production much cheaper. After the production, the ASICs are in the process of being fully characterized to check if they can substitute the Level 1 with discrete components. The GAE-UCM group which I belong, has contributed with the Level 1 ASIC specification and will also help with its characterization. Before being directly soldered in the front-end board, a first batch of ASICs will be mounted on mezzanines compatible with the ones implemented with discrete components. In this way, the ASICs can be tested with the front-end boards, and their behaviour can be compared with the one obtained with discrete components. The GAE-UCM group will be in charge of the production of the L1 mezzanines with the Level 1 ASIC designed by the Ciemat team. The target is to have the ASICs characterized and ready for integration in the front-end boards and in the backplane for the massive production phase, when most of the telescopes will be built. If it is not possible, designs with discrete components are the default solution.

8.2.2 Topologic stereo trigger

In the case of the Trigger Interface Board, there are still a few improvements to include regarding firmware debugging and software development. As was mentioned in section 7.3, there are several advanced functionalities which could be implemented if required, although the baseline which consists of looking for temporal coincidences between 4 LSTs and gathering the different trigger origins is working as expected. One of the most promising improvements is the topologic hardware stereo trigger. As it was briefly described in section 7.3.5, it consists of looking not only for coincidences inside a time window, but also for images compatible with Cherenkov showers. Adding this additional condition, most of the NSB triggers which happen by chance inside the time window can be rejected, while keeping the γ-ray-like showers. As the trigger rate can be further reduced, it is possible to lower the thresholds until reaching the maximum reading rate again at a smaller energy threshold. A similar topologic scheme has been proposed for the MAGIC telescopes, which could serve as a baseline design for the CTA LSTs. The first simulations results, whose performance is represented in figure 8.1, show improvements above 20% in the collection area below 100 GeV [171]. In the case 204 8. Conclusion and Outlook of CTA LSTs, having 4 telescopes instead of only two, an even larger gain is expected. This case with 4 LSTs is currently under study with simulations.

(a) Absolute effective area

(b) Normalized effective area

Figure 8.1: Simulation results of the topologic scheme for the MAGIC telescopes

The practical implementation of a topologic hardware stereo trigger in CTA would require some minor changes in the current trigger hardware. The trigger system presented in this thesis can handle all the trigger information in a pulse: a trigger pulse means that the trigger threshold has 8. Conclusion and Outlook 205 been exceeded somewhere in the camera, a known amount of time before receiving the leading edge of the pulse. To implement the topologic scheme, the information about which cluster triggered, or at least which area of the camera was triggered, is required by the Trigger Interface Board to look for valid patterns.

There is only one spare line in the RJ45 interface between the TIB and the central backplane (see table 7.1), so in order to send more information to the TIB, this information must come from other backplanes apart from the central one. Considering this second option, two schemes have been proposed, which are described in subsections 8.2.2.1 and 8.2.2.2.

8.2.2.1 Sectorization

In these scheme the special backplanes which provide information to the TIB are the 7 ones around the central backplane. According to the current distribution scheme for the trigger, when one cluster is fired, it sends its trigger to a neighbour which, in turn, sends it to other neighbour and this process repeats until reaching the central cluster. The path followed by the trigger signal changes depending on the specific cluster, but always is composed of some “diagonal” jumps until finding their corresponding main path (or none if the fired cluster is in the main path), and some “radial” jumps until reaching the central cluster. This is illustrated with red arrows in figure 8.2.

Figure 8.2: Sectorization scheme 206 8. Conclusion and Outlook

This way of collecting the trigger signals means that, any of the six special backplanes surrounding the central one receives the triggers from a triangular sector which covers 1/6 of the camera. So, once the special cluster which received the trigger is known, it is possible to deduce in which camera sector it was generated. Additionally, if the number of jumps is encoded in the pulse width of the trigger pulse, it is possible to restrict even more the possible trigger origins to one of the areas with the same color in figure 8.2. The clusters corresponding to the last two jumps have been coloured with the same color (i.e. included in the same region) to avoid very small regions, however they can be divided in other two regions corresponding to one or two jumps away from the special cluster. With this scheme, as it is described by figure 8.2, the TIB can know in which of the the 37 regions of the camera the trigger was originated. This information can be codified with 6 bits and broadcasted through the optical links to the other LSTs. So, considering 4 LSTs, the TIB can manage a table with 374 = 1874161 possibilities: some of them will be accepted as images produced by a γ-ray shower, while others don’t. If this granularity is not enough to get good results from the topologic trigger, the triangulation scheme can be used.

8.2.2.2 Triangulation

The triangulation scheme is more complex, but it allows to know exactly which cluster was trig- gered. When a cluster is triggered (orange in figure 8.3), it distributes a signal to all its neighbours, which in turn send their signals to their surrounding neighbours and so on, generating a trigger circular wave front which expands throughout the camera (red circumferences). The number of jumps is codified in the pulse width, so the special clusters (red ones in figure 8.3) can know how far from them a trigger has happened. In this way, the TIB, which will be additionally connected to these special clusters, also knows how far from each special cluster a trigger happened and can triangulate the position of the trigger origin. The propagation of the trigger wave throughout the backplanes network would be independent from the standard trigger propagation, and could be done using spare lines in the connectors between neighbour clusters. However, the way in which it could be propagated to prevent the wave from coming back, or how would it solve special cases like two clusters triggering at the same time is still under development. Additionally, knowing which cluster from the 265 in a camera was triggered in the 4 telescopes means 2654 ≈ 5 · 109 possibilities to be analyzed by the TIB FPGA. This is probably too much to take the decision with a look-up table in a short time, so maybe some kind of region reduction would be required, partially loosing the greatest advantage of this scheme. 8. Conclusion and Outlook 207

Figure 8.3: Triangulation scheme

Appendix A

Schematics

A.1 Level 1 schematics 210 A. Schematics

4 3 21 TABLE OF CONTENTS

SHEET NO. SHEET NAME BLOCK NAME D D 1 page1 l1delaymasterv3

2 page2 l1delaymasterv3

3 page1 diff2single

4 page1 divider3

5 page1 divider3

C 6 page1 adder4 C

7 page1 diff2singleb

8 page1 div2

9 page1 div2

10 page1 atenuator

11 page1 atenuator

B B 12 page1 lvds_or

13 page1 lvds_or

14 page1 3comparator

15 page1 3comparator

16 page1 lvds_and

17 page1 width2amp

A 18 page1 read_pulse_amp A

TITLE: DATE: L1 DELAY MASTER V3 7/03/2013 ENGINEER: PAGE: 1 LUIS A. TEJEDOR 43 2 1

Figure A.1: L1: Schematic Index N

A. Schematics 211 F E D C B A

15 2 1 10U

OF

2 1

APPR. 100P

2

1 C122C123 2 100N

AN_TRG_OUT0_P AN_TRG_OUT0_N

2 1 1 C121 2 100P 10U

1 C18 2 10U

SHEET 1 C120 2 100P

I87

2 1 1 25/5/2012 C119 2 AN_TRG_OUT1_P CALIB_IN_P AN_TRG_OUT1_N CALIB_IN_N 10U 100P

14 11 2 5 OUTP

OUTN 1 C17 C118 2 AGND\G DELAY_ADC_CS 100N

1 1 C117 2 DGND\G DELAY_ADC_SDO L1_DAC_CLK 100N

1 2 C116 +3.3V_DIGITAL\G AGND\G 100N

RF2B RF1A 1 C16 C115 2 DD=+2.5V_DIGITAL;GND3=DGND;GND5=DGND;GND6=DGND;GND8=DGND;GND9=DGND;GND11=DGND;G 10U

I128 LVDS_OR U26 ADG936_1 V

2

POWER OR GATE C114 1 +3.3V_DIGITAL\G 100P adg936

VTH_A VTH_B

CS*

IN1P IN1N IN2P IN2N IN3P IN3N INA RF2A INB RFCA RFCB RF1B

1 C113 2 100N SCLK 1 10 2 I115 8 POWER INPUT IN AP2141 C112 18 16 10 CALIB_EN

I98 1 2 VREF U12

100U

100 100

VOUT_B 100 VOUT_A SDATA_OUT DRAWING NO. 2 1 2 1 2 2 1 1

10U

VDD GND 3 C111 9 R8 R9 R10

1 2 1 C110 2

100P 10U ad5663r

PULSE_IN READ_PULSE_AMP

2 1 2 C108 C109 1 DGND\G 100N 100P DIN SCLK SYNC* LDAC* CLR* L1 DELAY MASTER V3 DGND\G

I88 I90 2 C106 C107 1 2

+3.3V_DIGITAL\G AGND\G 100N

4 5 8 7 6 100K 1

+3.3V_DIGITAL\G 2

OUT1P OUT2P OUT3P OUT1N OUT2N OUT3N 2 OUTP OUTN C105 VTH VTH_A

REVISIONS

R110

1 2 R127 10U 50

REV. DGND\G

1 2 LVDS_OR C104 100P 2 3COMPARATOR

DGND\G DGND\G

INAD1 INAD2 INAD3

1 2 2 C103 +3.3V_DIGITAL\G 100N

IN1P IN1N IN2P IN2N IN3P IN3N

IMPLEMENTS COLIBRI AND

C132 L1 TRIGGER MEZZANINE DELAY CALIBRATION SYSTEMS

L1_DAC_CLK L1_DAC_CS L1_DAC_SDI

200 200

200 10U

2 1 2 1 2 1 1 C102 2

C -3.3V_ANALOG\G +3.3V_DIGITAL\G C

C

C

1 2 SIZE R2 R3 R4

33U

100 100 100

1 2 1 2 1 1 2 SCALE R109 POWER IN TRIG3 CONNECTOR DRAWING TITLE

10K

C101 R90 R91 R92 AGND\G

1 +3.3V_CALIB\G 2 AGND\G AGND\G 100N 1 3 1 C14 OUTAD2 OUTAD1 OUT OUTAD3

I95 I114 2 1

OUT 100P I173 GND 2 C13 U13 DGND\G

OUT1P OUT2P OUT3P OUT1N OUT2N OUT3N IN EN FLG

ap2141_sot25 VTH

1 ZONE LTR2 DESCRIPTION DATE VTH_B 10N 5 4

WIDTH2AMP C100

1 2 OUTAD1 OUTAD2 OUTAD3 1N 2 2 2 3COMPARATOR

INP INN INAD1 INAD2 INAD3 C62

1

2 C65 C64 C63

1N

10U 10U 10U 200 200 200 2 1 2 1 2 1 I48 C61 R5 R88 R89 U14 CALIB_EN

4 1 1 1

1 2

1N

100

2 1

Y

C60

+3.3V_DIGITAL\G +3.3V_DIGITAL\G

GND

sn74lvc1g32 VCC 3

5 I3 1 2 R108 DGND\G AGND\G AGND\G AGND\G 1N A B 3 C59

2 1

2 1 A0 A1 1N OUTPUT2 OUTPUT3 OUTPUT1 C58

OUTP I113 OUTN 1 2 CADENCE 1N

C57 ENABLE OUTAD3 OUTAD2 OUTAD1

1 2 +3.3V_DIGITAL\G 1N C5

LVDS_AND

ADDER4

1 2 A0 NAND A1 1N CADENCE DESIGN SYSTEMS,INC. C4 THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO CADENCE DESIGN SYSTEMS INC (CADENCE). USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF CADENCE IS EXPRESSLY FORBIDDEN. COPYRIGHT (C) CADENCE 1988 A0* A0YA1\G

IN1P IN1N IN2P IN2N 11 3 6 8

ENABLE_3\G

1 2 1Y 2Y 10UF

C6

GND

I172 VCC

2 1 7 U2 14

DGND\G 100P

INPUT11 INPUT12 INPUT13 INPUT14 INPUT21 INPUT22 INPUT23 INPUT24 INPUT31 INPUT32 INPUT33 INPUT34 100 100

1 12 C99 2 NAND

74hc00

2 1 100N 1A 1B 3A3B 4A4B 3Y 4Y 2A 2B C98 R106 R107 POWER SWITCHING NETWORK AND ADG936 AGND\G

2 4 5 9 1 2 1 68U 13 10 12 C97 A0 A1

A0 A1 CL0_ADDER1 CL1_ADDER1 CL2_ADDER1 CL6_ADDER1

1 2 CL1_ADDER2 CL3_ADDER2 +3.3V_DIGITAL\G CL0_ADDER2 CL2_ADDER2 CL0_ADDER3 CL1_ADDER3 CL5_ADDER3 CL6_ADDER3 10U

4 CALIB_IN_P CALIB_IN_N DELAY_REF_P DELAY_REF_N

1 C150 2 +2.5V_DIGITAL\G 100N

DGND\G

1 C149 2 100P

C148

2 1 2 1 10U 10UF

C3

1 C153 2 100N

1

2 CL0_ADDER2 CL1_ADDER2 CL1_ADDER1 CL2_ADDER2 CL3_ADDER2 CL5_ADDER3 CL6_ADDER3 100NF 8 8 8 8 8 8 8

1 C152 2 C1 AGND\G DGND\G CL6_ADDER1 100P 8

I12 I13 I14 I15 I16 I17 I18 1

C151 2 GND=AGND GND=AGND GND=AGND GND=AGND GND=AGND GND=AGND GND=AGND U5 U6 U7 U8 U9 U10 U11 RF2 RF2 RF2 RF2 RF2 RF2 RF2 100PF

VDD VDD VDD VDD VDD VDD VDD I19 1 1 1 1 1 1

C56 1 GND=AGND U4 RF2

+3.3V_DIGITAL\G

VDD adg901 adg901 adg901 adg901 adg901 adg901 adg901 1 adg901 CTRL RF1 CTRL RF1 CTRL RF1 CTRL RF1 CTRL RF1 CTRL RF1 CTRL RF1 +2.5V_DIGITAL\G +2.5V_DIGITAL\G CTRL RF1 NAND GATE FILTER +2.5V_DIGITAL\G +2.5V_DIGITAL\G 2 4 2 4 2 4 2 4 2 4 2 4 2 4 A1 +2.5V_DIGITAL\G +2.5V_DIGITAL\G +2.5V_DIGITAL\G +2.5V_DIGITAL\G 2 4 A0 C0A2 A1 C1A1 C2A2 A0 C3A2 C4A3 C5A3 C1A2 A0YA1\G C5A1 A0YA1\G A0YA1\G A0YA1\G DGND\G DGND\G DGND\G DGND\G DGND\G DGND\G DGND\G DGND\G DGND\G DGND\G 5 DIG_TRG_OUT0_P DELAY_REF_N DIG_TRG_OUT6_P NC NC DIG_TRG_OUT4_N DIG_TRG_OUT5_P DIG_TRG_OUT6_N DIG_TRG_OUT1_P DIG_TRG_OUT1_N DIG_TRG_OUT2_P DIG_TRG_OUT2_N DELAY_REF_P DIG_TRG_OUT4_P DIG_TRG_OUT0_N DIG_TRG_OUT5_N -3.3V_ANALOG\G +3.3V_DIGITAL\G CL0_ADDER3 CL1_ADDER3 C1A1 C1A2 C2A2 CL2_ADDER1 C3A2 C4A3 C5A1 C5A3 CL0_ADDER1 C0A2 I9 DIV3_1 DIV3_2 10 12 14 16 18 54 56 2 4 6 8 20 22 24 26 30 32 34 36 38 40 42 44 46 48 50 52 58 60 28 I68 I8 I67 U2 U3 54 56 30 32 36

DGND\G qmss-016-024-25-l-d-dp-a-pc4

61 61 OUTPUT OUTPUT OUTPUT2 OUTPUT2 OUTPUT3 OUTPUT2 OUTPUT3 OUTPUT2 OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT1 12 11131517 12 19 14 16 18 20 53 55 34 56 78 910 21232527 22 29 24 31 26 33 28 35 3739 34 4143 38 45 40 47 42 49 44 51 46 48 57 50 52 59 58 60 DIV2 DIV2 3 5 7 9 1 DIVIDER3 DIVIDER3 53 55 13 15 17 19 23 25 27 29 33 35 37 39 43 45 47 49 57 59 11 31 41 51 21 ATENUATOR ATENUATOR INPUT INPUT INPUT INPUT INPUT INPUT +2.5V_DIGITAL\G AN_TRG_OUT1_N +2.5V_DIGITAL\G -3.3V_ANALOG\G AN_TRG_OUT0_P DGND\G AN_TRG_OUT1_P DGND\G DGND\G DELAY_REF_P DELAY_REF_N DGND\G DGND\G A0 A1 DGND\G NC DELAY_ADC_SDO DGND\G L1_DAC_CLK L1_DAC_SDI L1_DAC_CS DELAY_ADC_CS DGND\G DGND\G AN_TRG_OUT0_N DGND\G 6 +3.3V_DIGITAL\G

DGND\G

2

2 1 10U

1 C91 2 10U

1

R105 2 C90 0 10U

2 C89

2 1 10U

1 1 C86 2 C88 10U 10U C87 1 AGND\G CLUSTER1 CLUSTER2 CLUSTER0 GROUND COMMON POINT CLUSTER4 CLUSTER5 CLUSTER3 NC NC AGND\G NC NC AGND\G NC NC AGND\G NC NC AGND\G AGND\G NC NC AGND\G NC NC AGND\G NC NC AGND\G NC NC AGND\G AGND\G D2S1

7 OUTPUT2 OUTPUT3 OUTPUT1 ENABLE I4 +3.3V_DIGITAL\G 10 12 14 16 18 2 4 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 6 8 U1 U1 28

OUTPUT2 OUTPUT3 AGND\G qmss-016-06-75-l-d-dp-a OUTPUT1

DIFF2SINGLE 53 53 ENABLE +3.3V_DIGITAL\G 12 11131517 12 19 14 16 18 20 34 56 78 910 21232527 22 29 24 31 26 3335 30 37 32 39 34 41 36 43 38 45 40 47 42 49 44 51 46 48 50 52 INPUT1_P INPUT1_N INPUT2_P INPUT2_N INPUT3_P INPUT3_N 3 5 7 9 1 DIFF2SINGLEB 39 13 15 17 19 23 25 27 29 33 35 37 43 45 47 49 11 21 31 41 51 INPUT1_P INPUT1_N INPUT2_P INPUT2_N INPUT3_P INPUT3_N L1_IN0_P L1_IN1_N L1_IN2_N L1_IN2_P L1_IN0_N L1_IN1_P 2 2 2 2 2 2 AN_L1_IN4_P AN_L1_IN4_N AGND\G AGND\G NC NC AGND\G AN_L1_IN0_P AN_L1_IN0_N AGND\G AN_L1_IN1_P AN_L1_IN1_N AN_L1_IN2_P AN_L1_IN2_N AGND\G AGND\G AN_L1_IN3_P AN_L1_IN3_N AGND\G AGND\G AGND\G AN_L1_IN5_P AN_L1_IN5_N AGND\G L1_IN3_N L1_IN3_P L1_IN5_N L1_IN5_P L1_IN4_N L1_IN4_P 2 2 2 2 2 2 C85 C92 C93 C94 C95 C96 10U 10U 10U 10U 10U 10U C2 C15 C82 C83 C84 C7

10U 10U 10U 10U 10U 10U

1 1 1 1 1 1

100

1 8 2 1 1 1 1 1 1 R1 AN_L1_IN0_N AN_L1_IN0_P AN_L1_IN1_N AN_L1_IN1_P AN_L1_IN2_N AN_L1_IN2_P AN_L1_IN3_N AN_L1_IN3_P AN_L1_IN4_N AN_L1_IN4_P AN_L1_IN5_N AN_L1_IN5_P F E D C B A

Figure A.2: L1: General Schematic 212 A. Schematics

4 3 2 1 IN OUT OUT OUT

D D ENABLE OUTPUT2 OUTPUT3 OUTPUT1 10 12 14 5 23 8 PD2 PD3

PD1

I25 OUT2 OUT3 OUT1 U16

2 CC V 3 DD V 2 1 2 1 9 1 3 1 100P 100P

1 CC V 2 DD V

1 4 C26 2 C27

3 CC V 1 DD V 8 1 6

ad8003

2 1 2 1 10U 10U C24 C25

AGND\G

-IN1 +IN1 -IN2 +IN2 -IN3 +IN3 FB1 FB2 FB3 2 2 1 1

100N C 100N C C22 C23 AGND\G 3 4 2 22 15 20 17 16 21 +3.3V_DIGITAL\G -3.3V_ANALOG\G

B B AGND\G AGND\G AGND\G 2 2 2 2 2 2 R26 R25 R28 R30 R27 R29 300 300 300 300 300 300 1 1 1 1 1 1 AGND\G AGND\G AGND\G AGND\G AGND\G AGND\G 2 2 2 2 2 2 2 2 2 2 2 2 R13 R14 R15 R16 R17 R18 R19 R20 R22 R23 R24 R21 65 65 65 65 62 62 200 200 200 200 261 261 1 1 1 1 1 1 1 1 1 1 1 1

A INPUT1_N INPUT1_P INPUT2_N INPUT2_P INPUT3_N INPUT3_P A IN IN IN IN IN IN INPUT3_N\I INPUT3_P\I INPUT2_N\I INPUT2_P\I INPUT1_N\I INPUT1_P\I ENABLE\I OUTPUT1\I OUTPUT2\I OUTPUT3\I

TITLE: DATE: PIN NAMES DIFF2SINGLE 7/03/2013 ENGINEER: PAGE: LUIS A. TEJEDOR 3 4 3 2 1

Figure A.3: L1: Differential to Single-Ended (channels 0,1,and 2) A. Schematics 213

4 3 2 1 OUT OUT OUT D D

OUTPUT1

G 1P \ D N

OUTPUT3 OUTPUT2

G

49.9 A

49.9

49.9 C 2PF C

AGND\G

2PF 2PF AGND\G AGND\G L L L 20N 20N 20N G \

D B 5.6PF N B G A 49.9 INPUT

A A IN

TITLE: DATE: INPUT\I OUTPUT1\I OUTPUT2\I OUTPUT3\I DIVIDER3 25/05/2012 PIN NAMES ENGINEER: PAGE: LUIS A. TEJEDOR 4, 5 4 3 2 1

Figure A.4: L1: 3 branches splitter 214 A. Schematics

4 3 2 1 IN OUT OUT OUT D D ENABLE_3\G ENABLE OUTPUT1 OUTPUT2 OUTPUT3 10 12 14 8 23 5

PD2 PD3

PD1

1 2 I41 100P OUT2 OUT3 U17 OUT1

C49

2 CC V 3 DD V 9 1 3 1 2 1 10U

1 CC V 2 DD V

1 4 C48 2

3 CC V 1 DD V 6 8

AGND\G 1

ad8003

2 2 1 1 100N 10U C46 C C C47

FB1 FB2 FB3 -IN1 +IN1 -IN2 +IN2 -IN3 +IN3 2 1 100N AGND\G

2 2 2 3 2 4 C45

22 15 16 20 17 21

2 1 100P 275 275 275 R59 R60 R58 AGND\G C44 AGND\G AGND\G 1 1 1 +3.3V_DIGITAL\G -3.3V_ANALOG\G 2 2 2 2 2 2 2 2 2 2 2 2

B B 100 100 100 100 100 100 100 100 100 100 100 100 AGND\G

R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54

1 1 1 1 1 1 1 1 1 1 1 1 100 7 8 R

2 1 100 6 8 R

2 1 100 5 8 R

1 2 100 4 8 R

1 2 100 3 8 R

1 2 100 7 5 R

2 1 100 6 5 R

2 1 100 5 5 R

2 1

100 4 3 R

INPUT11 INPUT12

2 1 100 1 1 R

2 1 100 R7

2 1 100 R6

2 1

A INPUT13 INPUT14 INPUT21 INPUT22 INPUT23 INPUT24 INPUT31 INPUT32 INPUT33 INPUT34 A IN IN IN IN IN IN IN IN IN IN IN IN

TITLE: DATE: INPUT14\I INPUT13\I INPUT12\I INPUT11\I INPUT31\I INPUT32\I INPUT33\I INPUT34\I INPUT21\I INPUT22\I INPUT23\I INPUT24\I ENABLE\I OUTPUT3\I OUTPUT2\I OUTPUT1\I ADDER4 07/03/2013 PIN NAMES ENGINEER: PAGE: LUIS A. TEJEDOR 6 4 3 2 1

Figure A.5: L1: 4 inputs adders A. Schematics 215

4 3 2 1 IN OUT OUT OUT

D D ENABLE ENABLE_3\G A0YA1\G OUTPUT1 OUTPUT2 OUTPUT3

10 12 14 8 23 5 C55

1 2 2 1 100P 100P PD2 PD3 PD1 I21 OUT2 OUT3 OUT1 U18

C54

2 CC V 3 DD V

2 9 1 1 1 3 1 2 10U 10U C53

1 CC V

2 DD V 1 4

2 AGND\G

1 DD V 3 CC V 1 6

C52 8

AGND\G

ad8003

2 1 2 1 100N 100N

C C -IN1 +IN1 -IN2 +IN2 -IN3 +IN3 FB1 FB2 FB3 C50 C51 2 3 4 20 22 17 16 15 21 -3.3V_ANALOG\G +3.3V_DIGITAL\G

B B AGND\G AGND\G AGND\G 2 2 2 2 2 2 R73 R74 300 300 300 300 300 300 R76 R75 R77 R78 1 1 1 1 1 1 AGND\G AGND\G AGND\G AGND\G AGND\G AGND\G 2 2 2 2 2 2 2 2 2 2 2 2 R64 R68 60 60 60 62 62 60 300 300 300 300 261 261 R62 R66 R67 R72 R70 R71 R61 R63

A A 1 1 1 1 1 1 1 1 1 1 1 1 R65 R69 INPUT1_N INPUT1_P INPUT2_N INPUT2_P INPUT3_N INPUT3_P IN IN IN IN IN IN

TITLE: DATE: DIFF2SINGLEB 07/03/2013 ENGINEER: PAGE: LUIS A. TEJEDOR 7

4 3 2 1

Figure A.6: L1: Differential to Single-Ended (channels 3, 4 and 5) 216 A. Schematics

4 3 2 1

D D OUT OUT

OUTPUT1 OUTPUT2

AGND\G 191

2P 2PF AGND\G C C L L

15NH 15NH 4PF

B B 49.9 AGND\G INPUT

A A IN INPUT\I OUTPUT2\I OUTPUT1\I TITLE: DATE: PIN NAMES DIV2 ENGINEER: PAGE: LUIS A. TEJEDOR 8, 9 4 3 2 1

Figure A.7: L1: 2 branches splitter A. Schematics 217

4 3 2 1

D D OUT

OUTPUT 500 AGND\G

C C 56 INPUT

B B IN

A A INPUT\I OUTPUT\I PIN NAMES

TITLE: DATE: ATENUATOR 07/03/2013 ENGINEER: PAGE: LUIS A. TEJEDOR 10, 11 4 3 2 1

Figure A.8: L1: Attenuator 218 A. Schematics

4 3 2 1

10U 100P

D 100N D OUT OUT OUTP OUTN I12 AGND\G

Q Q* adcmp604

C C V E VE +3.3V_DIGITAL\G VP VN

C C

5 285 sms h 10M

IN2N

N I

A D2 C D2

N I

A D1 C D1

I9

10M

5 285 sms

B h B IN3N 10M

IN1N

N I

A D2 C D2

IN3P

N I

A D1 C D1

I8

10M

5 285 sms h 10M

IN2P

N I

A D2 C D2

N I

A D1 C D1

A I7 A 10M IN1P IN3N\I IN3P\I IN2N\I IN2P\I IN1N\I IN1P\I OUTN\I OUTP\I

TITLE: DATE: PIN NAMES LVDS_OR 19/03/2013 ENGINEER: PAGE: LUIS A. TEJEDO 12, 13 4 3 2 1

Figure A.9: L1: LVDS OR gate A. Schematics 219

4 3 2 1

D D OUT OUT OUT OUT OUT OUT OUT3P OUT1P OUT1N OUT2P OUT2N OUT3N I1 I2 I3

Q Q Q Q* Q* Q* adcmp604 adcmp604 adcmp604

C C V C C V C C V E VE E VE E C VE C VP VN VP VN VP VN INAD1 INAD2 INAD3 VTH +3.3V_DIGITAL\G VTH VTH VTH AGND\G AGND\G AGND\G IN IN IN IN +3.3V_DIGITAL\G +3.3V_DIGITAL\G

B B

100P 100P 100P

100N 100N 100N

10U 10U 10U

A A INAD3\I INAD2\I INAD1\I OUT1P\I OUT1N\I OUT2P\I OUT2N\I OUT3P\I OUT3N\I VTH\I TITLE: DATE: 3COMPARATOR PIN NAMES ENGINEER: PAGE: LUIS A. TEJEDOR 14, 15 4 3 2 1

Figure A.10: L1: comparators 220 A. Schematics

4 3 2 1

D OUT OUT D C125 DGND\G 2 2 2 I9 U27 OUTP OUTN 1 6 C124

Q Q*

10UF C126 adcmp604

100NF 100PF

C C V E VE 5 +3.3V_CALIB\G 2 DGND\G 1 1 1 VP VN C C 3 4 1 4 2 3 2 2 2 2 I8 I5 D7 D2A D1A D8 D1C D2C 1K 1K 1K 1K R111 R112 R114 R113

B hsms 2855 B D1A D2 A D1 C D2C hsms 2855 1 1 1 1 4 3 2 1 IN1P IN2P IN1N IN2N IN IN IN IN

A A IN2N\I IN2P\I IN1N\I IN1P\I OUTN\I OUTP\I TITLE: DATE:

PIN NAMES LVDS AND 19/03/2013 ENGINEER: PAGE: LUIS A. TEJEDOR 16 4 3 2 1

Figure A.11: L1: LVDS AND gate A. Schematics 221

4 3 2 1 OUT

D OUT D 1 390K R122 2 AGND\G 1 5 6 7 R119 10K I22 U28 IN2- IN2+

2 2 OUT2

+3.3V_CALIB\G -3.3V_ANALOG\G

C C V + C C -V 8 4 C13 3 10UF IN1- IN1+ OUT1

C opa2830_msop8 C 1 2 3 1

R118 1M

1 2 AGND\G

R117 1M

2 1 2 1 100P

C131

2 1 100N 2 2

C130

1 B 2 B 10U 1M 1M R116 R115 +3.3V_CALIB\G C129 -3.3V_ANALOG\G

1 1

5 285 sms h I4

C128 D9

C D2 A D2 2 1 2 3 120P

C D1 A D1 1 2 1 4 120P AGND\G C127 AGND\G

A INP INN A IN IN INP\I INN\I OUT\I PIN NAMES TITLE: DATE: WIDTH2AMP 6/9/2012 ENGINEER: PAGE: LUIS A. TEJEDOR 17 4 3 2 1

Figure A.12: L1: Width to Amplitude converter 222 A. Schematics

4 3 2 1 IN IN OUT

D D SDATA_OUT SCLK CS* DGND\G 1 1 3 2 6 2 C145 C146 C147 CS* 10U I16 100N 100P

SCLK U31

DGND\G

SDATA

DD V D N 2 G 7 +3.3V_CALIB\G 1 2 2 1 adc7478a C144 1UF VIN NC NC2 8 5 4 1

DGND\G

1 2

C 10N AGND\G C 1 2 100P

1 2 C143 100N C142

+3.3V_CALIB\G DGND\G DGND\G

2 1 C141 10U 1 1 2 2 C140 C137 C138 C139

10U

S NC 100N 100P 5

C136

+3.3V_CALIB\G

DD V 2 1 6 I10 47P

U30

DGND\G

ND G 2 3 2 1 adg801 IN D 4 1 1 AGND\G I5 U29 2

B Q B

DGND\G

adcmp600 ND G CCI V 5 2 R126

1 VP VN

1.5K

+3.3V_CALIB\G

2 1 68P 2 3 4 1 C134 2 100N PULSE_IN 10K 2 C135 R125 10K R124 IN 1 1 AGND\G

A A +3.3V_CALIB\G

TITLE: DATE: SDATA_OUT\I CS*\I SCLK\I PULSE_IN\I READ PULSE AMP 5/9/2012

PIN NAMES ENGINEER: PAGE: LUIS A. TEJEDOR 18 4 3 2 1

Figure A.13: L1: Read Pulse Amplitude circuit A. Schematics 223

A.2 Trigger interface board schematics 224 A. Schematics B C A D r o d e j e 1 T n

o . i s A i

v s i e u R L 2 2 1 1 : f y o

B

n

t P N e w _ _ e a r F F h I I S D D D _ _ D D P N E E _ _ P N P N P N P N P N P N P N P N Y Y B B ______c A A 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 P N P N C C o L L ______P N D 0 0 1 1 E E T T T T T T T T T T T T T T T T O O _ _ h _ _ _ _ D D U U U U U U U U U U U U U U U U c E E B B T T T T P P P P P P P P P P P P P P P P E E I I S R R . r U U U U T T T T T T T T T T T T T T T T L L B B e 1 E E P P P P g U U U U U U U U U U U U U U U U A A O O T T A g N N N N i T T S S I I I I C C O O O O O O O O O O O O O O O O G r P T POTOBEDELAYED0DIF0P POTOBEDELAYED0DIF0N POSTEREO0CB0P POSTEREO0CB0N POINPUT000P POINPUT000N POINPUT010P POINPUT010N POCALIB0P POCALIB0N POOUTPUT000P POOUTPUT000N POOUTPUT010P POOUTPUT010N POOUTPUT020P POOUTPUT020N POOUTPUT030P POOUTPUT030N POOUTPUT040P POOUTPUT040N POOUTPUT050P POOUTPUT050N POOUTPUT060P POOUTPUT060N POOUTPUT070P POOUTPUT070N

F 1 o \ . e . P N A r \ _ _ e e t G F F v I I i S P r F D D D _ _

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u 8 p PIC4801 7 4 a . D D D D COC48 C C 4 N N N N G G G G PIC4802 P N _ _ F F I I D D _ _ D D E E D Y Y N A A G L L E E D D P N P N P N P N P N P N P N P N P N P N D G G ______I I P N P N P N 9 9 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 N R R ______1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 G 3 3 8 8 7 7 ______T T ______A A A A A A A A A A A A A A A A A A A A T T T T T T POTRIGDELAYED0DIF0P POTRIGDELAYED0DIF0N R R R R R R R R R R R R R R R R R R R R 8 8 U U U U U U T T T T T T T T T T T T T T T T T T T T P P P P P P P N X X X X X X X X X X X X X X X X X X X X _ _ N N N N N N E E I I I I I I E E E E E E E E E E E E E E E E E E F F V V V V V I I 5 3 5 5 8 . . . . V . POEXTRA0190P POEXTRA0190N POINPUT030P POINPUT030N POINPUT080P POINPUT080N POINPUT070P POINPUT070N POEXTRA0100P POEXTRA0100N POEXTRA0110P POEXTRA0110N POEXTRA0120P POEXTRA0120N POEXTRA0130P POEXTRA0130N POEXTRA0140P POEXTRA0140N POEXTRA0150P POEXTRA0150N POEXTRA0160P POEXTRA0160N POEXTRA0170P POEXTRA0170N POEXTRA0180P POEXTRA0180N D D V 2 3 2 2 1 1 _ _ 8 + + + + + + . D D 1 E E + P N P N P N P N P N P N P N P N P N P N Y Y ______P N P N P N A A 9 9 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 ______1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 L L 3 3 8 8 7 7 ______E E ______A A A A A A A A A A A A A A A A A A A A 1 2 D D T T T T T T 3 5 2 1 2 4 3 3 8 5 3 9 R R R R R R R R R R R R R R R R R R R R 6 2 2 3 4 A C D 4 5 1 2 3 1 1 1 9 9 G G U U U U U U 1 2 5 1 9 1 1 6 9 1 2 6 T T T T T T T T T T T T T T T T T T T T I I 7 9 P P P P P P A B C D E F U W7 Y A A A K L M8 N P T A C D F G J G M1 N R W1 U J L N R U X X R R X X X X X X X X X X X X X X X X X X N N N N N N NLEXTRA0190P NLEXTRA0190N NLTRIGDELAYED0DIF0P NLTRIGDELAYED0DIF0N NLINPUT030P NLINPUT030N NLINPUT080P NLINPUT080N NLINPUT070P NLINPUT070N NLEXTRA0100P NLEXTRA0100N NLEXTRA0110P NLEXTRA0110N NLEXTRA0120P NLEXTRA0120N NLEXTRA0130P NLEXTRA0130N NLEXTRA0140P NLEXTRA0140N NLEXTRA0150P NLEXTRA0150N NLEXTRA0160P NLEXTRA0160N NLEXTRA0170P NLEXTRA0170N NLEXTRA0180P NLEXTRA0180N PIU100A21 PIU100B18 PIU100C25 PIU100D22 PIU100E19 PIU100F16 PIU100U3 PIU100W7 PIU100Y4 PIU100AA1 PIU100AC5 PIU100AD2 PIU100K4 PIU100L1 PIU100M8 PIU100N5 PIU100P2 PIU100T6 PIU100A1 PIU100C5 PIU100D2 PIU100F6 PIU100G3 PIU100J7 PIU100G14 PIU100M12 PIU100N13 PIU100R13 PIU100W13 PIU100U13 PIU100J9 PIU100L9 PIU100N9 PIU100R9 PIU100U9 E E T T I I I I I I E E E E E E E E E E E E E E E E E E 0 0 6 6 6 6 6 6 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 X X X X X M M M M _ _ 1 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 U U U U U ______A A A A T C A A A A A T O O O O O O O O O O O O O O O O O O O O O O O O R R R R D C C C C C C C C C C C C C C C C C C C C C C C C C C C C C B B B B A A C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C B E E 7 4 5 7 5 9 6 6 6 7 8 9 8 9 0 0 2 1 5 3 4 3 4 C 7 7 9 8 9 0 1 1 2 2 3 5 6 6 4 4 6 7 8 0 1 2 7 8 9 5 0 6 6 V V V V V 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 C C C C C V V V V V V V V V V V V V V V V V V V V V V V V 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 1 1 1 2 2 2 1 1 1 1 2 C 7 7 C H H H G F F F G F G F H G C B E D A A B A E E D C D C E D B A C B B A E D C C B A A A C B C B D D E V V V V 6 6 V V G G PIU100H17 PIU100H14 PIU100H15 PIU100G17 PIU100F17 PIU100F18 PIU100F19 PIU100G15 PIU100F15 PIU100G19 PIU100F20 PIU100H16 PIU100G16 PIU100C17 PIU100B17 PIU100E16 PIU100D16 PIU100A17 PIU100A18 PIU100B19 PIU100A19 PIU100E17 PIU100E18 PIU100D18 PIU100C18 PIU100D19 PIU100C19 PIU100E20 PIU100D20 PIU100B20 PIU100A20 PIU100C21 PIU100B21 PIU100B22 PIU100A22 PIU100E21 PIU100D21 PIU100C22 PIU100C23 PIU100B25 PIU100A25 PIU100A23 PIU100A24 PIU100C26 PIU100B26 PIU100C24 PIU100B24 PIU100D23 PIU100D24 PIU100E22 G G F F 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 - - 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 1 1 1 1 1 1 1 1 ______0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ______T T T T T T T T T T T T T T T 0 5 0 0 0 0 0 1 1 0 0 0 0 1 1 1 2 2 2 3 3 3 3 3 1 2 2 2 3 3 3 3 S S S S F F S S S S ______0 0 C C C C C C C C _ 2 N N N N N N N N N N N N N T T T T T T T T T T T T T T T T T T T T T T T T T T T T T T E E 0 0 Q Q Q Q Q Q Q Q _ O O O O O O O O O O O O O O O O O O O O O O O O O O I I I I I I I I I I I I I ______C C C C C C C C O 1 1 R R I D D D D D D D D C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C O P P P P P P P P P P P P P P P P R R R R N N N N N N N N N N N N N N A A I ______V V J K 1 2 4 5 6 7 8 0 6 7 8 9 0 2 3 4 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 1 2 4 5 7 8 0 6 7 8 0 2 3 4 S S S S 7 7 0 1 0 1 2 3 2 3 _ _ 0 0 1 1 1 1 1 2 2 2 2 MR MR MR MR L L L L L L L 1 1 1 1 2 2 2 2 _ _ _ _ L L L L L L V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 0 3 1 C 1 C T T T T T T T T ______L L L L L L L L L 1 2 1 2 ______L L L L L L L L ______1 2 1 2 COU10J COU10K T T ______U X U X ______T T T T O O O O O O O O O O O O O P P _ _ P P T T T T I I I I I I I N N N N _ _ _ _ I I I I I I O O O O O O O O O O O O O O O O O 3 9 5 1 _ _ _ _ I I I I I I I I I 3 9 5 1 N N I I I I I I I I P P 1 2 N N 6 6 1 1 3 0 2 2 6 0 9 4 3 0 4 4 5 5 3 0 4 0 2 1 0 2 9 8 5 6 1 2 7 1 3 1 7 8 0 L L 1 2 P P 6 9 L L 1 4 N N 1 4 1 2 2 1 1 1 1 2 2 1 1 1 2 2 2 2 1 2 2 2 1 1 1 1 1 1 1 1 2 2 2 2 1 1 1 _ _ L L 2 3 1 _ _ L L 1 1 2 3 L E J J J 1 1 P F P F _ _ 1 1 T T L L L T T E R B C Y U V Y K N N G H K K K U V V A D _ _ 1 1 O O _ L 6 L L M1 M1 O O W1 W1 L L I I L L I I _ 7 A O O A _ _ L L A A A A O O PIU100Y14 PIU100W11 PIU100W17 PIU100AA21 PIU100AB18 PIU100AD22 PIU100AE19 PIU100AF26 PIU100T16 PIU100T26 PIU100U23 PIU100V20 PIU100Y24 PIU100AC25 PIU100K24 PIU100L21 PIU100N15 PIU100N25 PIU100P22 PIU100R19 PIU100F26 PIU100G23 PIU100H20 PIU100J17 PIU100K14 PIU100M18 PIU100J11 PIU100J13 PIU100K10 PIU100K12 PIU100L11 PIU100L13 PIU100M10 PIU100P10 PIU100T10 PIU100T12 PIU100U11 PIU100V10 PIU100V12 O _ _ I I _ _ 6 I I I _ _ O O O O O I I I O O G I I O O I I I I G 7 7 F 3 - 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PIU100AE24 PIU100AF1 PIU100AF6 PIU100AF8 PIU100AF10 PIU100AF12 PIU100AF14 PIU100AF16 PIU100AF21 PIU100M11 E 6 L _ _ L 7 D P E E 0 6 D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D 1 A F E _ L D B 1 G N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N I S P C 7 C B _ G _ _ _ _ L G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G I P 2 D A E E E E F 2 A _ R F S A 3 _ L L L L I L - T C S L L D D 2 3 4 5 6 7 8 9 D D D B B B B _ _ _ L D T ______L E A E E E E E S S S _ 0 N E A A A A L L L L L L L L L E T D D Y Y 0 S S S S Y Y O O O X G D _ S _ E E E E E E E E E 1 D I I I I A A _ D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D L L L T A A _ T E T D D D D D D D D D A D D D D L L L T K N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N ______L L T 7 X D X _ _ _ _ 0 E E POLOS0TRIGDELAYED POLOS0CALIB POLOS0SFP011 POTX0DISABLE0TOBEDELAYED A L X T T T T T T T T T E E G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G X E E E 1 C X X X X D D E _ C D _ P 7 0 1 2 3 4 5 6 6 6 X X X X X X X X X D D E D T T T T U X I COU10L _ E E S S ______O E E E E E E E E E E G G S _ _ S B B S S S S S S S S K I I F ______S POTX0DISABLE0SFP011 POTX0DISABLE0PEDESTAL POTX0DISABLE0CALIB POTX0DISABLE07 Y 4 7 8 9 6 3 6 6 9 1 9 7 6 8 7 5 9 2 C C 2 2 0 2 4 5 4 0 2 6 6 4 1 5 6 3 1 3 6 0 0 2 4 6 6 5 7 0 1 2 3 8 5 1 3 9 0 0 3 3 L E O R R O O O E E E E E E E E E O O O O O O O J 2 2 1 2 1 1 1 1 2 1 1 1 2 1 2 1 1 2 1 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 2 1 1 1 1 2 F F P E E E E L A B B C C A A D H K L L MI MO C I I T T T T R L L L L L L L L L L L L L L L L L J J M3 M9 F F E E E E E L L L L B B B C C C C A A A A A D D G G G G G H K K K N N L M1 M2 A POLOS0PEDESTAL POMISO0EXT0DEL POMOSI0EXT0DEL POCLK0EXT0DEL POI2C0SCLK POI2C0SDA POTRIGDELAYED POTRIGDELAYED02 POTOBEDELAYED POTOBEDELAYED02 POREF0EXT0DEL POLOS07 POLE0EXT0DEL POLE0EXT0DEL02 POLE0EXT0DEL03 POLE0EXT0DEL04 POLE0EXT0DEL05 POLE0EXT0DEL06 POLE0EXT0DEL07 POLE0EXT0DEL08 POLE0EXT0DEL09 POLOS00 POLOS01 POLOS02 POLOS03 POLOS04 POLOS05 POLOS06 E T PIU100A6 PIU100A8 PIU100A10 PIU100A12 PIU100A14 PIU100A16 PIU100A26 PIU100B3 PIU100B6 PIU100B15 PIU100B16 PIU100B23 PIU100C6 PIU100C9 PIU100C11 PIU100C13 PIU100C16 PIU100C20 PIU100D7 PIU100D15 PIU100D17 PIU100E4 PIU100E7 PIU100E8 PIU100E9 PIU100E10 PIU100E12 PIU100E14 PIU100E15 PIU100E24 PIU100F1 PIU100F9 PIU100F14 PIU100F21 PIU100G10 PIU100G11 PIU100G12 PIU100G13 PIU100G18 PIU100H5 PIU100H25 PIU100J2 PIU100J12 PIU100J22 PIU100K9 PIU100K11 PIU100K13 PIU100K19 PIU100L6 PIU100L10 PIU100L12 PIU100L16 PIU100L26 PIU100M3 PIU100M9 PIU100M13 PIU100M23 PIU100N10 PIU100N20 PIU100P7 D 1 S B D 1 E I E _ E D L B D P Y N A O F E L A G T S P C 7 A L _ _ _ _ _ T E E E E E E 1 S L L L L L D B 1 I E B B B B B _ G L I D P A A A A A A R E F S S S S S I I I I I P T C S 7 0 1 2 3 4 5 6 ______D D D D D S S S S _ _ _ _ _ S S S S S S S S O O O O X X X X X O O O O O O O O L L L L T T T T T L L L L L L L L NLLOS0PEDESTAL NLLOS0TRIGDELAYED NLLOS0CALIB NLLOS0SFP011 NLTX0DISABLE0TOBEDELAYED NLTX0DISABLE0SFP011 NLTX0DISABLE0PEDESTAL NLTX0DISABLE0CALIB NLTX0DISABLE07 NLLOS07 NLLOS00 NLLOS01 NLLOS02 NLLOS03 NLLOS04 NLLOS05 NLLOS06 4 5 6 7 8 5 6 7 9 0 8 0 1 1 1 2 3 2 4 2 3 4 5 6 6 6 5 4 5 7 8 3 5 6 9 2 3 4 5 6 4 5 9 0 8 1 3 4 5 6 1 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 K K J J J K K M1 L M1 L M1 M1 J H L L K J J H G G K J H H J H G F J H F E K K G F E D E D H G G F J J L PIU100K18 PIU100K15 PIU100J16 PIU100J14 PIU100J15 PIU100K16 PIU100K17 PIU100M14 PIU100L14 PIU100M15 PIU100L15 PIU100M16 PIU100M17 PIU100J19 PIU100H19 PIU100L17 PIU100L18 PIU100K20 PIU100J20 PIU100J18 PIU100H18 PIU100G20 PIU100G21 PIU100K21 PIU100J21 PIU100H21 PIU100H22 PIU100J23 PIU100H23 PIU100G22 PIU100F22 PIU100J24 PIU100H24 PIU100F23 PIU100E23 PIU100K22 PIU100K23 PIU100G24 PIU100F24 PIU100E25 PIU100D25 PIU100E26 PIU100D26 PIU100H26 PIU100G26 PIU100G25 PIU100F25 PIU100J25 PIU100J26 PIU100L19 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ______0 0 0 5 0 1 0 8 6 4 2 0 7 7 5 3 9 6 F 8 P P P P P P S S P P F B B B N N N N N N N N C C _ C C C C C C 2 2 2 2 2 2 1 2 2 2 1 1 1 1 3 T T S S 0 8 9 2 0 T 1 E _ _ _ 0 8 9 2 0 1 3 1 E Q Q _ _ _ 1 C C _ C C 1 C C C C O 1 A A A A A A R A A A A A R 1 A D D D D D D E R V I D D D D R D D D D P P O ______R R _ D R R N D D I D A A A A A A _ _ O 4 6 V D 2 2 2 3 3 3 3 2 2 2 3 3 3 A A A A V A A WE 4 S S S S S ______2 3 A _ A F _ _ _ _ A MR MR MR MR _ _ _ L L A _ _ T T T T T T T T T T T T T _ _ F A L 0 0 0 1 _ 0 _ Q S S _ T T 0 0 0 1 _ _ _ _ _ 1 _ _ _ 1 2 S S ______1 2 _ _ _ 1 1 3 T T T T _ _ 1 1 2 1 2 2 T 1 T T T T 3 D Q Q P P P P P P P T T O O T T S Q Q N N N N N N _ _ _ _ T O _ T P P T I I _ _ _ _ T T T T T _ T 6 7 8 9 0 2 4 _ _ A _ _ T I 6 7 8 0 2 4 D D _ _ P P P P 5 1 _ Q _ _ _ _ _ 3 D D _ 1 1 1 1 2 2 2 _ N _ P P 1 1 1 2 2 2 N N N N _ _ 1 2 5 7 1 2 P N N P _ _ P P P 3 6 T 0 9 8 7 5 1 4 D L L L L L L L 1 0 9 7 6 1 2 5 7 N N N 0 1 N L L L L L L 8 1 4 N 0 0 1 3 L L L L L L 2 3 _ 2 1 1 1 1 8 7 5 4 3 2 1 1 ______6 5 4 2 2 1 1 1 6 5 4 2 1 8 2 3 T L 0 E E ______L L L L 1 1 3 T T 8 7 6 5 1 2 ______L 1 1 T T 2 1 1 _ _ 1 6 6 L L _ _ _ _ L 2 N _ _ B B B B B B B B B B A A A A A A A A A A A 1 1 1 1 8 7 5 6 3 2 1 9 8 7 6 4 3 2 1 7 O O O O O O O _ L L L _ _ O O O O O O L L L 7 7 I I I I I I I O O O O O O _ _ T _ L L 1 L I I I I I I P P N O _ _ L _ I I I I I I O O O O _ A A A A A A A A A A A A A A A A A A A A A Y Y Y Y Y Y Y Y Y Y Y W1 W1 W1 W8 W6 W5 W4 W3 W1 V V V V V V V V U _ _ 6 6 O _ I _ _ 2 N N _ I I I I 3 9 9 _ O O I O O O O 3 9 I I O I O O 1 L G G N I I O O L L I O 5 I 5 I I O PIU100AB21 PIU100AB20 PIU100AB19 PIU100AB17 PIU100AB16 PIU100AB6 PIU100AB5 PIU100AB4 PIU100AB2 PIU100AB1 PIU100AA20 PIU100AA19 PIU100AA18 PIU100AA17 PIU100AA15 PIU100AA8 PIU100AA7 PIU100AA5 PIU100AA4 PIU100AA3 PIU100AA2 PIU100Y18 PIU100Y17 PIU100Y16 PIU100Y15 PIU100Y8 PIU100Y7 PIU100Y5 PIU100Y6 PIU100Y3 PIU100Y2 PIU100Y1 PIU100W16 PIU100W15 PIU100W14 PIU100W8 PIU100W6 PIU100W5 PIU100W4 PIU100W3 PIU100W1 PIU100V9 PIU100V8 PIU100V7 PIU100V6 PIU100V4 PIU100V3 PIU100V2 PIU100V1 PIU100U7 I I I _ L L 5 I _ _ L G G _ _ 1 _ O O O F F I C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C I I L O O O 3 3 I I I _ - - N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N T T O I 0 0

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5 1 K N A B A A C M C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 7 7 0 0 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N 1 C 1 C U X U X COU10C COU10M 5 3 2 1 5 4 3 2 6 4 3 2 1 5 4 3 1 6 5 3 2 1 0 8 7 5 4 3 2 0 9 8 7 3 2 1 9 8 7 6 2 6 5 4 3 1 0 9 8 7 2 2 2 2 2 2 1 1 2 2 2 2 2 1 1 1 2 2 2 1 1 1 1 2 2 2 2 2 2 2 1 1 1 F F F F E E E E C C C C C D D D D F F F F F F F F E E E E E E E E C C C C C C C B D D D D D D D D D A A A A A A A A A A A A A A A A A D A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A E PIU100AF25 PIU100AF24 PIU100AF23 PIU100AF22 PIU100AF20 PIU100AF19 PIU100AF18 PIU100AF17 PIU100AF5 PIU100AF4 PIU100AF3 PIU100AF2 PIU100AE26 PIU100AE25 PIU100AE23 PIU100AE22 PIU100AE21 PIU100AE20 PIU100AE18 PIU100AE17 PIU100AE5 PIU100AE3 PIU100AE2 PIU100AE1 PIU100AD26 PIU100AD25 PIU100AD24 PIU100AD23 PIU100AD21 PIU100AD20 PIU100AD19 PIU100AD18 PIU100AD17 PIU100AD5 PIU100AD4 PIU100AD3 PIU100AD1 PIU100AC23 PIU100AC22 PIU100AC21 PIU100AC19 PIU100AC18 PIU100AC17 PIU100AC16 PIU100AC6 PIU100AC4 PIU100AC3 PIU100AC2 PIU100AC1 PIU100AB22 Y A L L A E T D D 1 S B 1 I E N E _ T L B G D P 0 1 2 3 4 C A O E F _ _ _ _ _ E 7 C P S T E E E E E T _ _ _ _ _ L L L L L E T T T T T B B B B B L L L L L D A A A A A _ 5 6 U U U U U S S S S S _ _ E I I I I I A A A A A E E L F F F F F D D D D D L L N B ______I 0 1 2 3 4 5 6 B B A ______X X X X X X X X X X D D A A T T T T T T T E T T T T T C T T T T T _ I 6 E S S X K X L L L L L L L O I I 0 1 S 7 L Y T R _ _ H U U U U U U U S 6 POTX0FAULT07 POTX0FAULT0CALIB POTX0FAULT0PEDESTAL POTX0FAULT0SFP011 POTX0FAULT0TOBEDELAYED POCABLE0DETECT POTX0DISABLE00 POTX0DISABLE01 POTX0DISABLE02 POTX0DISABLE03 POTX0DISABLE04 0 D D _ _ C S S _ A T T _ _ A A A A A A A L H G H T T _ 5 3 1 MO C MI C C L E B F F F F F F F X X T A G T 1 1 1 7 R R ______S K E _ I I I I I T T _ _ _ _ _ F T 0 A A E L S X X X X X X X P 1 1 1 1 P P P P 3 D 1 M_ S _ O - B 0 1 0 S P P P P R C U U S S S S I C T T T T T T T 0 POTX0DISABLE05 POTX0DISABLE06 I E E 0 A S _ 0 T _ _ _ _ L B _ 0 0 R D V 0 P P N 0 0 0 5 6 0 1 2 3 4 B 0 POSPI0MOSI0DIN POP1015 POP1013 POP1011 POP107 PORESET POCLK0TH POUART0TX POUART0RX POSPI0CCLK POSPI0MISO POSPI0CS00 POSPI0CS01 POIO0TH POCS0TH POTX0FAULT00 POTX0FAULT01 POTX0FAULT02 POTX0FAULT03 POTX0FAULT04 POTX0FAULT05 POTX0FAULT06 _ K E _ A 0 O _ _ E F F F ______G B 0 0 0 0 1 0 _ L K 0 1 2 3 4 5 6 7 C P S T N _ P N E E E E E E E E E I O T _ _ _ _ O G A 4 4 I ______C G C L L L L L L L O P N R R X X F D D MS 7 R 0 T T T T T T T T T T T T N T C B B B B B B B T T T M0 M1 M2 D I P C V V V V D D 1 C L L L L L L L L L L L L A A A A A A A U X COU10G U U U U U U U U U U U U S S S S S S S I I I I I I I A A A A A A A A A A A A 9 7 6 5 0 1 2 2 1 0 2 1 3 1 2 1 0 D D F F F F F F F F F F F F D D D D D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ______B Y J W9 P P E B R R H H H H V N N X X X X X X X X X X X X X X X X X X X A W1

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Figure A.14: TIB: FPGA pins A. Schematics 225 B C A D i i i i i COC133 C133 Cap Sem 470nF 1 edor COC97 COC115 COC151 COC160 C97 Cap Sem 470nF C115 Cap Sem 470nF C151 Cap Sem 470nF C160 Cap Sem 470nF PIC13302 PIC13301 i GND PIC9702 PIC9701 PIC11502 PIC11501 PIC15102 PIC15101 PIC16002 PIC16001 i i i i i GND GND GND GND on s A. Tej Bank 0 si Lui COC132 C132 Cap Sem 470nF Revi COC64 COC96 COC114 COC150 COC159 C64 Cap Sem 47uF C96 Cap Sem 470nF C114 Cap Sem 470nF C150 Cap Sem 470nF C159 Cap Sem 470nF PIC13202 PIC13201 i GND PIC6402 PIC6401 PIC9602 PIC9601 PIC11402 PIC11401 PIC15002 PIC15001 PIC15902 PIC15901 3.3V i i i i GND GND GND GND GND + of 4 4 i COC131 C131 Cap Sem 470nF Sheet Drawn By: COC95 COC113 COC149 COC158 C95 Cap Sem 470nF C113 Cap Sem 470nF C149 Cap Sem 470nF C158 Cap Sem 470nF PIC13102 PIC13101 i GND PIC9502 PIC9501 PIC11302 PIC11301 PIC14902 PIC14901 PIC15802 PIC15801 i i i i GND GND GND GND COC81 C81 Cap Sem 470nF PIC8102 PIC8101 i GND COC130 C130 Cap Sem 470nF gger COC94 COC112 COC148 COC157 C94 Cap Sem 470nF C112 Cap Sem 470nF C148 Cap Sem 470nF C157 Cap Sem 470nF PIC13002 PIC13001 i GND PIC9402 PIC9401 PIC11202 PIC11201 PIC14802 PIC14801 PIC15702 PIC15701 i i i i GND GND GND GND COC80 C80 Cap Sem 470nF ereo Tri FPGA_Power.SchDoc PIC8002 PIC8001 St ..\ i GND COC129 C129 Cap Sem 470nF ve\ COC93 COC111 COC147 COC156 C93 Cap Sem 470nF C111 Cap Sem 470nF C147 Cap Sem 470nF C156 Cap Sem 470nF PIC12902 PIC12901 i GND PIC9302 PIC9301 PIC11102 PIC11101 PIC14702 PIC14701 PIC15602 PIC15601 e Dri i i i i GND GND GND GND COC79 C79 Cap Sem 470nF ber 2013 PIC7902 PIC7901 i 12/ Googl GND COC128 C128 Cap Sem 4.7uF \ Num 30/ C: COC92 COC110 COC146 COC155 C92 Cap Sem 4.7uF C110 Cap Sem 4.7uF C146 Cap Sem 4.7uF C155 Cap Sem 4.7uF PIC12802 PIC12801 i GND PIC9202 PIC9201 PIC11002 PIC11001 PIC14602 PIC14601 PIC15502 PIC15501 i i i i GND GND GND GND COC78 C78 Cap Sem 470nF e e: PIC7802 PIC7801 l e: t ze l i GND A4 COC127 C127 Cap Sem 4.7uF Ti Si Dat Fi COC91 COC109 COC145 COC154 C91 Cap Sem 4.7uF C109 Cap Sem 4.7uF C145 Cap Sem 4.7uF C154 Cap Sem 4.7uF PIC12702 PIC12701 i GND PIC9102 PIC9101 PIC10902 PIC10901 PIC14502 PIC14501 PIC15402 PIC15401 i i i i GND GND GND GND COC77 C77 Cap Sem 470nF i PIC7702 PIC7701 i GND COC126 C126 Cap Sem 4.7uF COC90 COC108 COC144 COC153 C90 Cap Sem 4.7uF C108 Cap Sem 4.7uF C144 Cap Sem 4.7uF C153 Cap Sem 4.7uF PIC12602 PIC12601 i GND COC63 C63 Cap Sem 4.7uF PIC9002 PIC9001 PIC10802 PIC10801 PIC14402 PIC14401 PIC15302 PIC15301 3 3 i i i i GND GND GND GND COC76 C76 Cap Sem 470nF PIC6302 PIC6301 i GND PIC7602 PIC7601 i GND COC125 C125 Cap Sem 100uF C89 Cap Sem 47uF C107 Cap Sem 100uF C143 Cap Sem 100uF C152 Cap Sem 100uF COC89 COC107 COC143 COC152 PIC12502 PIC12501 GND C62 Cap Sem 4.7uF COC62 PIC8902 PIC8901 PIC10702 PIC10701 PIC14302 PIC14301 PIC15202 PIC15201 3.3V GND GND GND GND C75 Cap Sem 470nF COC75 + PIC6202 PIC6201 2.5V 2.5V 2.5V i i GND + + + PIC7502 PIC7501 i GND C61 Cap Sem 4.7uF C88 Cap Sem 47uF COC61 COC88 C74 Cap Sem 470nF COC74 PIC6102 PIC6101 PIC8802 PIC8801 Bank 15 1.8V i GND GND + PIC7402 PIC7401 Bank 13 Bank 33 Bank 35 i GND i i i C60 Cap Sem 4.7uF COC60 C73 Cap Sem 470nF COC73 PIC6002 PIC6001 i GND PIC7302 PIC7301 i i GND C106 Cap Sem 470nF C124 Cap Sem 470nF C142 Cap Sem 470nF COC106 COC124 COC142 VCCAUX PIC10602 PIC10601 PIC12402 PIC12401 PIC14202 PIC14201 i i i GND GND GND C59 Cap Sem 4.7uF COC59 C72 Cap Sem 470nF C169 Cap Sem 470nF COC72 COC169 PIC5902 PIC5901 i GND PIC7202 PIC7201 PIC16902 PIC16901 i i GND GND C105 Cap Sem 470nF C123 Cap Sem 470nF C141 Cap Sem 470nF COC105 COC123 COC141 PIC10502 PIC10501 PIC12302 PIC12301 PIC14102 PIC14101 i i i GND GND GND C58 Cap Sem 4.7uF COC58 i C71 Cap Sem 470nF C168 Cap Sem 470nF COC71 COC168 PIC5802 PIC5801 i GND PIC7102 PIC7101 PIC16802 PIC16801 i i GND GND C104 Cap Sem 470nF C122 Cap Sem 470nF C140 Cap Sem 470nF COC104 COC122 COC140 2 C87 Cap Sem 470nF 2 COC87 PIC10402 PIC10401 PIC12202 PIC12201 PIC14002 PIC14001 i i i GND GND GND C57 Cap Sem 4.7uF COC57 PIC8702 PIC8701 i GND C70 Cap Sem 470nF C167 Cap Sem 470nF COC70 COC167 PIC5702 PIC5701 i GND PIC7002 PIC7001 PIC16702 PIC16701 i i GND GND C103 Cap Sem 470nF C121 Cap Sem 470nF C139 Cap Sem 470nF COC103 COC121 COC139 C86 Cap Sem 470nF COC86 PIC10302 PIC10301 PIC12102 PIC12101 PIC13902 PIC13901 i i i GND GND GND C56 Cap Sem 4.7uF COC56 PIC8602 PIC8601 i GND C69 Cap Sem 470nF C166 Cap Sem 470nF COC69 COC166 PIC5602 PIC5601 i GND PIC6902 PIC6901 PIC16602 PIC16601 i i GND GND C102 Cap Sem 470nF C120 Cap Sem 470nF C138 Cap Sem 470nF COC102 COC120 COC138 COC85 C85 Cap Sem 470nF PIC10202 PIC10201 PIC12002 PIC12001 PIC13802 PIC13801 i i i GND GND GND C55 Cap Sem 4.7uF COC55 PIC8502 PIC8501 i GND COC68 COC165 C68 Cap Sem 470nF C165 Cap Sem 470nF PIC5502 PIC5501 i GND PIC6802 PIC6801 PIC16502 PIC16501 i i GND GND COC101 COC119 COC137 C101 Cap Sem 4.7uF C119 Cap Sem 4.7uF C137 Cap Sem 4.7uF COC84 C84 Cap Sem 4.7uF PIC10102 PIC10101 PIC11902 PIC11901 PIC13702 PIC13701 i i i GND GND GND COC54 C54 Cap Sem 4.7uF PIC8402 PIC8401 i GND COC67 COC164 C67 Cap Sem 470nF C164 Cap Sem 4.7uF PIC5402 PIC5401 i GND PIC6702 PIC6701 PIC16402 PIC16401 i i GND GND COC100 COC118 COC136 C100 Cap Sem 4.7uF C118 Cap Sem 4.7uF C136 Cap Sem 4.7uF COC83 C83 Cap Sem 4.7uF PIC10002 PIC10001 PIC11802 PIC11801 PIC13602 PIC13601 i i i GND GND GND COC53 C53 Cap Sem 4.7uF PIC8302 PIC8301 i GND COC66 COC163 C66 Cap Sem 470nF C163 Cap Sem 4.7uF PIC5302 PIC5301 GND 3 PIC6602 PIC6601 PIC16302 PIC16301 i i GND GND C99 Cap Sem 4.7uF C117 Cap Sem 4.7uF C135 Cap Sem 4.7uF COC99 COC117 COC135 C82 Cap Sem 100uF COC82 PIC9902 PIC9901 PIC11702 PIC11701 PIC13502 PIC13501 i i i GND GND GND C52 Cap Pol 330uF COC52 1V PIC8202 PIC8201 + GND C65 Cap Sem 470nF C162 Cap Sem 4.7uF COC65 COC162 1V PIC5201 PIC5202 + GND PIC6502 PIC6501 PIC16202 PIC16201 1 1 i GND GND C98 Cap Sem 100uF C116 Cap Sem 100uF C134 Cap Sem 100uF COC98 COC116 COC134 1V PIC9802 PIC9801 PIC11602 PIC11601 PIC13402 PIC13401 Bank 34 + GND GND GND 2.5V 3.3V 2.5V C161 Cap Sem 100uF COC161 + + + PIC16102 PIC16101 VCCBRAM GND VCCINT 2.5V + VCCINT Bank 12 Bank 14 Bank 16 B C A D

Figure A.15: TIB: FPGA power filtering 226 A. Schematics B C A D 1 edor on s A. Tej si Lui Revi of 4 4 Sheet Drawn By: gger ereo Tri St JTAG JTAG.SchDoc ..\ ve\ e Dri ber 2013 12/ Googl \ Num 30/ C: e e: l e: t ze l A4 Ti Si Dat Fi 3 3 J29 Socket J30 Socket J32 Socket J33 Socket COJ29 COJ30 COJ32 COJ33 S TM TCK TDO TDI PIJ2901 PIJ3001 PIJ3201 PIJ3301 POTMS POTCK POTDO POTDI 3.3V S + NLTMS NLTCK NLTDO NLTDI TM TCK TDO TDI 2 4 6 8 10 12 14 PIJ3102 PIJ3104 PIJ3106 PIJ3108 PIJ31010 PIJ31012 PIJ31014 2 4 6 8 10 12 14 ex 87833-1420 ol 1 3 5 7 9 11 13 J31 M COJ31 1 3 5 7 9 11 13 PIJ3101 PIJ3103 PIJ3105 PIJ3107 PIJ3109 PIJ31011 PIJ31013 GND 2 2 1 1 B C A D

Figure A.16: TIB: JTAG connector A. Schematics 227 B C A D 1 edor on s A. Tej si Lui Revi of 4 4 Sheet Drawn By: gger .SchDoc ereo Tri St Raspberry Pi Raspberry_Pi ..\ ve\ e Dri ber 2013 J70 Socket J73 Socket COJ70 COJ73 12/ Googl \ Num PIJ7001 PIJ7301 30/ C: INIT_B DONE POINIT0B PODONE e e: l e: t ze l A4 _B Ti Si Dat Fi J62 Socket J65 Socket J68 Socket COJ62 COJ65 COJ68 3.3V UART_RX UART_TX PROGRAM + i PIJ6201 PIJ6501 PIJ6801 POUART0RX POUART0TX POPROGRAM0B 3 3 J72 Socket J75 Socket J76 Socket COJ72 COJ75 COJ76 COC306 C306 Cap Sem 10uF PIC30602 PIC30601 RESET SPI_CS_0 SPI_CS_1 PIJ7201 PIJ7501 PIJ7601 GND _B PORESET POSPI0CS00 POSPI0CS01 i GND GND GND NLINIT0B NLDONE INIT_B DONE C305 Cap Sem 100nF COC305 NLUART0RX NLUART0TX NLPROGRAM0B UART_RX UART_TX PROGRAM PIC30502 PIC30501 NLRESET NLSPI0CS00 NLSPI0CS01 RESET SPI_CS_0 SPI_CS_1 i GND 5V + 2 4 6 8 10 12 14 16 18 20 22 24 26 PIJ8502 PIJ8504 PIJ8506 PIJ8508 PIJ85010 PIJ85012 PIJ85014 PIJ85016 PIJ85018 PIJ85020 PIJ85022 PIJ85024 PIJ85026 C304 Cap Sem 100pF COC304 COR80 R80 Res3 100 NLSPI0CLK0COPY1 SPI_CLK_COPY1 PIR8002 PIR8001 PIC30402 PIC30401 GND GND 5V0 5V0 GND GND GND SPI_CS0 SPI_CS1 GPIO_18 GPIO_23 GPIO_24 GPIO_25

UART_TX

UART_RX

D N G 0 PIJ8500 GND J77 Socket COJ77 J79 Socket COJ79 OSI ISO PIJ7701 SPI_CCLK CONFIG_CCLK PIJ7901 3.3V I2C_SDA I2C_CLK GPIO_4 GND GPIO_17 GPIO_27 GPIO_22 3.3V SPI_M SPI_M SPI_CLK GND POSPI0CCLK POCONFIG0CCLK J85 Raspberry_Pi COJ85 1 3 5 7 9 11 13 15 17 19 21 23 25 PIJ8501 PIJ8503 PIJ8505 PIJ8507 PIJ8509 PIJ85011 PIJ85013 PIJ85015 PIJ85017 PIJ85019 PIJ85021 PIJ85023 PIJ85025 ed he cat i ow 3.3V 8 7 6 5 GND + on and t 2 2 PIU4008 PIU4007 PIU4006 PIU4005 i be repl k pad used NLI2C0SDA NLI2C0SCLK NLP107 I2C_SDA I2C_SCLK P1_7 gurat ust 1Y3 1Y2 1Y1 VDD he cl . ock m k pad used for sl rol GND ng confi cl o feed t CLKIN OE 1Y0 GND SPI cl t duri spi cont U40 CDCV304 COU40 OSI_DIN ISO 1 2 3 4 PIJ6101 PIJ6401 PIJ6701 NLSPI0MOSI0DIN NLSPI0MISO SPI_M SPI_M _CCLK PIU4001 PIU4002 PIU4003 PIU4004 COJ61 COJ64 COJ67 J61 Socket J64 Socket J67 Socket RPi NLRPi0CCLK 3.3V GND + I2C_SDA I2C_SCLK P1_7 _CCLK POI2C0SDA POI2C0SCLK POP107 RPi R81 Res3 100 COR81 SPI_CLK_COPY0 NLSPI0CLK0COPY0 PIR8102 PIR8101 P1_11 P1_13 P1_15 NLP1011 NLP1013 NLP1015 GND PIJ7101 PIJ7401 J71 Socket J74 Socket COJ71 COJ74 3.3V OSI_DIN ISO + PIJ6301 PIJ6601 PIJ6901 SPI_M SPI_M J63 Socket J66 Socket J69 Socket COJ63 COJ66 COJ69 PIJ7801 POSPI0MOSI0DIN POSPI0MISO J78 Socket COJ78 P1_11 P1_13 P1_15 POP1011 POP1013 POP1015 1 1 al duci FD3 Fi COFD3 B C A D

Figure A.17: TIB: Raspberry Pi pins 228 A. Schematics B C A D i i i i i Sem Sem Sem Sem Sem 1 COC199 C199 Cap 100nF edor COC175 COC181 COC187 COC193 C175 Cap 100nF C181 Cap 100nF C187 Cap 100nF C193 Cap 100nF PIC19902 PIC19901 Tej i

PIC17502 PIC17501 PIC18102 PIC18101 PIC18702 PIC18701 PIC19302 PIC19301 . i i i i A on Sem s si 8 8 Sem Sem Sem Sem Lui COC198 C198 Cap 100pF Revi D COC174 COC180 COC186 COC192 3V C174 Cap 100pF C180 Cap 100pF C186 Cap 100pF C192 Cap 100pF PIC19802 PIC19801 N 3. D D D D i 3V 3V 3V 3V G + PIC17402 PIC17401 PIC18002 PIC18001 PIC18602 PIC18601 PIC19202 PIC19201 N N N N of 3. 3. 3. 3.

By: i i i i G G G G

+ + + +

Sem n

_SFP_11_FB_P _SFP_11_FB_N Sem Sem Sem Sem raw COC197 C197 Cap 10uF oc Sheet D TRA TRA COC173 COC179 COC185 COC191 C173 Cap 10uF C179 Cap 10uF C185 Cap 10uF C191 Cap 10uF PIC19702 PIC19701 PIC17302 PIC17301 PIC17902 PIC17901 PIC18502 PIC18501 PIC19102 PIC19101 SchD PECL PECL. PECL_EX PECL_EX LV LV LV o t oLV gger POLVPECL0EXTRA0SFP0110FB0P POLVPECL0EXTRA0SFP0110FB0N S St T_4_P T_4_N T_5_P T_5_N T_6_P T_6_N T_7_P T_7_N Tri D D TPU TPU TPU TPU TPU TPU TPU TPU LV LIB_FB_P LIB_FB_N LV \ . ereo U U U U U U U U . St ve\ ri D e PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O PECL_CA PECL_CA 7 7 ber 2013 LV LV LV LV LV LV LV LV LV LV _SFP_11_FB_P _SFP_11_FB_N oogl um POLVPECL0OUTPUT040P POLVPECL0OUTPUT040N POLVPECL0OUTPUT050P POLVPECL0OUTPUT050N POLVPECL0OUTPUT060P POLVPECL0OUTPUT060N POLVPECL0OUTPUT070P POLVPECL0OUTPUT070N POLVPECL0CALIB0FB0P POLVPECL0CALIB0FB0N 12/ G \ N TRA TRA 30/ C: T_4_P T_4_N T_5_P T_5_N T_6_P T_6_N T_7_P T_7_N e e: 3 l e: t ze l PECL_EX PECL_EX at TPU TPU TPU TPU TPU TPU TPU TPU LIB_FB_P LIB_FB_N A Ti Si D Fi U U U U U U U U NLLVPECL0EXTRA0SFP0110FB0P NLLVPECL0EXTRA0SFP0110FB0N LV LV i Sem D PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O PECL_CA PECL_CA 3V N 3. NLLVPECL0OUTPUT040P NLLVPECL0OUTPUT040N NLLVPECL0OUTPUT050P NLLVPECL0OUTPUT050N NLLVPECL0OUTPUT060P NLLVPECL0OUTPUT060N NLLVPECL0OUTPUT070P NLLVPECL0OUTPUT070N NLLVPECL0CALIB0FB0P NLLVPECL0CALIB0FB0N G LV LV LV LV LV LV LV LV LV LV COC205 C205 Cap 100nF + 8 7 6 5 PIC20502 PIC20501 i PIU2208 PIU2207 PIU2206 PIU2205 D D D D D 3V 3V 3V 3V 3V Z N N N N N Y D Sem cc 3. 3. 3. 3. 3. G G G G G N S101 + + + + + V G D COC204 C204 Cap 100pF 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 D 3V PIU1208 PIU1207 PIU1206 PIU1205 PIU1408 PIU1407 PIU1406 PIU1405 PIU1608 PIU1607 PIU1606 PIU1605 PIU1808 PIU1807 PIU1806 PIU1805 PIU1908 PIU1907 PIU1906 PIU1905 PIC20402 PIC20401 N 3. C bb i 65LV G + Z Z Z Z Z N A B V D D D D D Y Y Y Y Y 22 cc cc cc cc cc 6 6 N N N N N COU22 U SN S101 S101 S101 S101 S101 V V V V V Sem G G G G G D D D D D 1 2 3 4 COC203 C203 Cap 10uF C bb C bb C bb C bb C bb 65LV 65LV 65LV 65LV 65LV PIU2201 PIU2202 PIU2203 PIU2204 N A B V N A B V N A B V N A B V N A B V 12 14 16 18 19 PIC20302 PIC20301 COU12 COU14 COU16 COU18 COU19 U SN U SN U SN U SN U SN 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 COR38 R38 Res3 100 PIU1201 PIU1202 PIU1203 PIU1204 PIU1401 PIU1402 PIU1403 PIU1404 PIU1601 PIU1602 PIU1603 PIU1604 PIU1801 PIU1802 PIU1803 PIU1804 PIU1901 PIU1902 PIU1903 PIU1904 PIR3802 PIR3801 2 R28 Res3 100 R30 Res3 100 R32 Res3 100 R34 Res3 100 R35 Res3 100 COR28 COR30 COR32 COR34 COR35 2 PIR2801 PIR2802 PIR3001 PIR3002 PIR3201 PIR3202 PIR3401 PIR3402 PIR3502 PIR3501 eader P20 H COP20 2 2 2 2 eader T_4_P T_4_N T_5_P T_5_N T_6_P T_6_N T_7_P T_7_N P10 H COP10 1 2 eader eader eader eader COP12 COP14 COP16 COP17 P12 H P14 H P16 H P17 H _SFP_11_FB_P _SFP_11_FB_N TPU TPU TPU TPU TPU TPU TPU TPU 1 2 U U U U U U U U TRA TRA NLOUTPUT040P NLOUTPUT040N NLOUTPUT050P NLOUTPUT050N NLOUTPUT060P NLOUTPUT060N NLOUTPUT070P NLOUTPUT070N O O O O O O O O PIP2001 PIP2002 1 2 1 2 1 2 1 2 LIB_FB_P LIB_FB_N NLEXTRA0SFP0110FB0P NLEXTRA0SFP0110FB0N EX EX NLCALIB0FB0P NLCALIB0FB0N CA CA PIP1001 PIP1002 5 5 PIP1201 PIP1202 PIP1401 PIP1402 PIP1601 PIP1602 PIP1701 PIP1702 T_4_P T_4_N T_5_P T_5_N T_6_P T_6_N T_7_P T_7_N TPU TPU U U TPU TPU TPU TPU TPU TPU O O _SFP_11_FB_N U U U U U U _SFP_11_FB_P LIB_FB_P LIB_FB_N O O O O O O POOUTPUT040P POOUTPUT040N TRA i i i i POOUTPUT050P POOUTPUT050N POOUTPUT060P POOUTPUT060N POOUTPUT070P POOUTPUT070N CA CA TRA i POCALIB0FB0P POCALIB0FB0N EX Sem Sem Sem Sem EX POEXTRA0SFP0110FB0N Sem POEXTRA0SFP0110FB0P C172 Cap 100nF C178 Cap 100nF C184 Cap 100nF C190 Cap 100nF COC172 COC178 COC184 COC190 C196 Cap 100nF COC196 PIC17202 PIC17201 PIC17802 PIC17801 PIC18402 PIC18401 PIC19002 PIC19001 i i i i PIC19602 PIC19601 i Sem Sem Sem Sem Sem COC171 COC177 COC183 COC189 C171 Cap 100pF C177 Cap 100pF C183 Cap 100pF C189 Cap 100pF IF_P IF_N D D D D 3V 3V 3V 3V COC195 C195 Cap 100pF PIC17102 PIC17101 PIC17702 PIC17701 PIC18302 PIC18301 PIC18902 PIC18901 N N N N _D _D 3. 3. 3. 3. D i i i i 3V G G G G + + + + PIC19502 PIC19501 N 3. ED ED i G + Y 4 4 Sem Sem Sem Sem Y Sem ELA C170 Cap 10uF C176 Cap 10uF C182 Cap 10uF C188 Cap 10uF COC170 COC176 COC182 COC188 ELA C194 Cap 10uF COC194 PIC17002 PIC17001 PIC17602 PIC17601 PIC18202 PIC18201 PIC18802 PIC18801 al BED BED PIC19402 PIC19401 2 duci COFD2 FD Fi PECL_TO PECL_TO T_0_P T_0_N T_1_P T_1_N T_2_P T_2_N T_3_P T_3_N LV LV L_FB_P L_FB_N TPU TPU TPU TPU TPU TPU TPU TPU POLVPECL0TOBEDELAYED0DIF0P POLVPECL0TOBEDELAYED0DIF0N U U U U U U U U ESTA ESTA IF_P IF_N _D _D PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O ED ED LV LV LV LV LV LV LV LV Y Y PECL_PED PECL_PED POLVPECL0OUTPUT000P POLVPECL0OUTPUT000N POLVPECL0OUTPUT010P POLVPECL0OUTPUT010N POLVPECL0OUTPUT020P POLVPECL0OUTPUT020N POLVPECL0OUTPUT030P POLVPECL0OUTPUT030N LV LV ELA ELA POLVPECL0PEDESTAL0FB0P POLVPECL0PEDESTAL0FB0N BED BED T_0_P T_0_N T_1_P T_1_N T_2_P T_2_N T_3_P T_3_N 3 3 TPU TPU TPU TPU TPU TPU TPU TPU L_FB_P L_FB_N U U U U U U U U PECL_TO PECL_TO ESTA ESTA LV LV NLLVPECL0TOBEDELAYED0DIF0P NLLVPECL0TOBEDELAYED0DIF0N PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O PECL_O i LV LV LV LV LV LV LV LV NLLVPECL0OUTPUT000P NLLVPECL0OUTPUT000N NLLVPECL0OUTPUT010P NLLVPECL0OUTPUT010N NLLVPECL0OUTPUT020P NLLVPECL0OUTPUT020N NLLVPECL0OUTPUT030P NLLVPECL0OUTPUT030N Sem D 3V N 3. PECL_PED PECL_PED G C202 Cap 100nF + COC202 LV LV NLLVPECL0PEDESTAL0FB0P NLLVPECL0PEDESTAL0FB0N 8 7 6 5 PIC20202 PIC20201 D D D D i 3V 3V 3V 3V PIU2108 PIU2107 PIU2106 PIU2105 N N N N 3. 3. 3. 3. G G G G + + + + Z D Y Sem cc D 3V N S101 V 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 N 3. G D G C201 Cap 100pF + PIU1108 PIU1107 PIU1106 PIU1105 PIU1308 PIU1307 PIU1306 PIU1305 PIU1508 PIU1507 PIU1506 PIU1505 PIU1708 PIU1707 PIU1706 PIU1705 COC201 D 3V 8 7 6 5 Z Z Z Z N D D D D Y Y Y Y PIC20102 PIC20101 cc cc cc cc 3. C bb i 65LV G N N N N S101 S101 S101 S101 V V V V + N A B V PIU2008 PIU2007 PIU2006 PIU2005 21 G G G G D D D D U SN COU21 Z D Y Sem cc N S101 V 1 2 3 4 C bb C bb C bb C bb G D 65LV 65LV 65LV 65LV COC200 C200 Cap 10uF N A B V N A B V N A B V N A B V 11 13 15 17 U SN U SN U SN U SN COU11 COU13 COU15 COU17 2 2 PIU2101 PIU2102 PIU2103 PIU2104 PIC20002 PIC20001 C bb 65LV 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 N A B V 20 U SN COU20 PIU1101 PIU1102 PIU1103 PIU1104 PIU1301 PIU1302 PIU1303 PIU1304 PIU1501 PIU1502 PIU1503 PIU1504 PIU1701 PIU1702 PIU1703 PIU1704 1 2 3 4 R37 Res3 100 COR37 PIR3702 PIR3701 2 PIU2001 PIU2002 PIU2003 PIU2004 IF_P IF_N eader _D _D R27 Res3 100 R29 Res3 100 R31 Res3 100 R33 Res3 100 R36 Res3 100 COR27 COR29 COR31 COR33 COR36 P19 H COP19 PIR2701 PIR2702 PIR2901 PIR2902 PIR3101 PIR3102 PIR3301 PIR3302 PIR3602 PIR3601 ED ED 2 2 2 2 2 Y Y 1 2 T_3_P T_3_N ELA ELA eader eader eader eader eader T_1_N P9 H P11 H P13 H P15 H P18 H L_FB_P L_FB_N COP9 COP11 COP13 COP15 COP18 TPU TPU BED BED T_0_P T_0_N T_2_P T_2_N PIP1901 PIP1902 U U TPU T_1_P O O TO TO NLOUTPUT030P NLOUTPUT030N NLTOBEDELAYED0DIF0P NLTOBEDELAYED0DIF0N 1 2 1 2 1 2 1 2 1 2 ESTA ESTA U TPU TPU TPU TPU O NLOUTPUT010N U U U U TPU O O O O PED PED NLOUTPUT000P NLOUTPUT000N NLOUTPUT020P NLOUTPUT020N NLPEDESTAL0FB0P NLPEDESTAL0FB0N U O NLOUTPUT010P PIP901 PIP902 PIP1101 PIP1102 PIP1301 PIP1302 PIP1501 PIP1502 PIP1801 PIP1802 IF_N IF_P _D _D 1 1 ED ED Y Y T_0_P T_0_N T_1_P T_1_N T_2_P T_2_N T_3_P T_3_N L_FB_P L_FB_N ELA ELA TPU TPU TPU TPU TPU TPU TPU TPU ESTA ESTA U U U U U U U U BED O O O O O O O O BED PED PED TO POOUTPUT000P POOUTPUT000N POOUTPUT010P POOUTPUT010N POOUTPUT020P POOUTPUT020N POOUTPUT030P POOUTPUT030N TO POPEDESTAL0FB0P POPEDESTAL0FB0N POTOBEDELAYED0DIF0N POTOBEDELAYED0DIF0P B C A D

Figure A.18: TIB: LVDS to LVPECL translators A. Schematics 229 B C A D i i i i i Sem Sem Sem Sem Sem 1 COC211 COC217 COC223 COC229 COC235 C211 Cap 100nF C217 Cap 100nF C223 Cap 100nF C229 Cap 100nF C235 Cap 100nF PIC21102 PIC21101 PIC21702 PIC21701 PIC22302 PIC22301 PIC22902 PIC22901 PIC23502 PIC23501 edor i i i i i Tej

on . Sem Sem Sem Sem Sem si A 8 8 s COC210 COC216 COC222 COC228 COC234 C210 Cap 100pF C216 Cap 100pF C222 Cap 100pF C228 Cap 100pF C234 Cap 100pF Revi D D D D D Lui 3V 3V 3V 3V 3V PIC21002 PIC21001 PIC21602 PIC21601 PIC22202 PIC22201 PIC22802 PIC22801 PIC23402 PIC23401 N N N N N 3. 3. 3. 3. 3. i i i i i G G G G G + + + + + of

By:

Sem Sem Sem Sem Sem n

2 raw COC209 COC215 COC221 COC227 COC233 C209 Cap 10uF C215 Cap 10uF C221 Cap 10uF C227 Cap 10uF C233 Cap 10uF oc Sheet D _SFP_11_P _SFP_11_N PIC20902 PIC20901 PIC21502 PIC21501 PIC22102 PIC22101 PIC22702 PIC22701 PIC23302 PIC23301 eader COP31 P31 H SchD TRA TRA S. D EX EX 1 2 S POEXTRA0SFP0110P POEXTRA0SFP0110N 2 2 2 2 2 D oLV LV gger o PIP3101 PIP3102 t eader eader eader eader eader Tri PECLt T_5_P T_5_N T_6_P T_6_N T_7_P T_7_N T_8_P T_8_N COP21 COP23 COP25 COP27 COP30 P21 H P23 H P25 H P27 H P30 H LIB_P LIB_N LV PU PU PU PU PU PU PU PU \ . ereo . PECL IN IN IN IN IN IN IN IN CA CA _SFP_11_P _SFP_11_N _SFP_11_P _SFP_11_N St 1 2 1 2 1 2 1 2 1 2 ve\ POINPUT050P POINPUT050N POINPUT060P POINPUT060N POINPUT070P POINPUT070N POINPUT080P POINPUT080N POCALIB0P POCALIB0N LV ri TRA TRA TRA TRA D e NLEXTRA0SFP0110P NLEXTRA0SFP0110N EX EX EX EX PIP2101 PIP2102 PIP2301 PIP2302 PIP2501 PIP2502 PIP2701 PIP2702 PIP3001 PIP3002 7 7 ber 2013 oogl um 12/ T_5_P T_5_N T_5_P T_5_N T_6_P T_6_N T_6_P T_6_N T_7_P T_7_N T_7_P T_7_N T_8_P T_8_N T_8_P T_8_N G \ N D LIB_P LIB_N LIB_P LIB_N 3V 30/ C: PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU N 3. G IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN CA CA CA CA NLINPUT050P NLINPUT050N NLINPUT060P NLINPUT060N NLINPUT070P NLINPUT070N NLINPUT080P NLINPUT080N NLCALIB0P NLCALIB0N + 8 7 6 5 e e: PIU3308 PIU3307 PIU3306 PIU3305 3 l e: D D D D t ze l at 3V 3V 3V 3V A Z N N N N D Y Ti Si D Fi cc 3. 3. 3. 3. D 3V G G G G N S100 + + + + V N 3. G D G + 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 PIU2308 PIU2307 PIU2306 PIU2305 PIU2508 PIU2507 PIU2506 PIU2505 PIU2708 PIU2707 PIU2706 PIU2705 PIU2908 PIU2907 PIU2906 PIU2905 8 7 6 5 C bb 65LV PIU3208 PIU3207 PIU3206 PIU3205 Z Z Z Z N A B V 33 D D D D Y Y Y Y cc cc cc cc COU33 U SN N N N N S100 S100 S100 S100 V V V V Z Y D cc G G G G D D D D N S100 V 1 2 3 4 G D C bb C bb C bb C bb i 65LV 65LV 65LV 65LV PIU3301 PIU3302 PIU3303 PIU3304 N A B V N A B V N A B V N A B V 23 25 27 29 C bb 65LV COU23 COU25 COU27 COU29 U SN U SN U SN U SN N A B V 32 Sem U SN COU32 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 COC238 C238 Cap 100nF 1 2 3 4 PIU2301 PIU2302 PIU2303 PIU2304 PIU2501 PIU2502 PIU2503 PIU2504 PIU2701 PIU2702 PIU2703 PIU2704 PIU2901 PIU2902 PIU2903 PIU2904 PIC23802 PIC23801 6 6 i PIU3201 PIU3202 PIU3203 PIU3204 Sem C237 Cap 100pF COC237 _SFP_11_P _SFP_11_N D 3V T_5_P T_5_N T_6_P T_6_N T_7_P T_7_N N PIC23702 PIC23701 3. i G TRA TRA T_8_P T_8_N + PU PU PU PU PU PU LIB_P LIB_N PU PU Sem COC236 C236 Cap 10uF PECL_IN PECL_IN PECL_IN PECL_IN PECL_IN PECL_IN PECL_EX PECL_EX PIC23602 PIC23601 PECL_IN PECL_IN PECL_CA PECL_CA LV LV LV LV LV LV LV LV NLLVPECL0INPUT050P NLLVPECL0INPUT050N NLLVPECL0INPUT060P NLLVPECL0INPUT060N NLLVPECL0INPUT070P NLLVPECL0INPUT070N NLLVPECL0EXTRA0SFP0110P NLLVPECL0EXTRA0SFP0110N LV LV LV LV NLLVPECL0INPUT080P NLLVPECL0INPUT080N NLLVPECL0CALIB0P NLLVPECL0CALIB0N T_5_P T_6_P T_7_P T_5_N T_6_N T_7_N T_8_P PU PU PU LIB_P LIB_N T_8_N PU PU PU PU _SFP_11_P _SFP_11_N PU PECL_IN PECL_IN PECL_IN TRA TRA 5 5 PECL_IN PECL_IN PECL_IN PECL_IN PECL_CA PECL_CA LV LV LV PECL_IN LV LV LV LV LV LV POLVPECL0INPUT050P POLVPECL0INPUT060P POLVPECL0INPUT070P LV POLVPECL0INPUT050N POLVPECL0INPUT060N POLVPECL0INPUT070N POLVPECL0INPUT080P POLVPECL0CALIB0P POLVPECL0CALIB0N PECL_EX PECL_EX POLVPECL0INPUT080N LV LV POLVPECL0EXTRA0SFP0110P POLVPECL0EXTRA0SFP0110N i i i i i Sem Sem Sem Sem Sem C214 Cap 100nF C220 Cap 100nF C226 Cap 100nF C232 Cap 100nF COC214 COC220 COC226 COC232 C208 Cap 100nF COC208 PIC21402 PIC21401 PIC22002 PIC22001 PIC22602 PIC22601 PIC23202 PIC23201 i i i i PIC20802 PIC20801 i Sem Sem Sem Sem Sem IF_P IF_N COC213 COC219 COC225 COC231 C213 Cap 100pF C219 Cap 100pF C225 Cap 100pF C231 Cap 100pF _D _D D D D D 3V 3V 3V 3V COC207 C207 Cap 100pF PIC21302 PIC21301 PIC21902 PIC21901 PIC22502 PIC22501 PIC23102 PIC23101 N N N N 4 4 3. 3. 3. 3. D i i i i ED ED 3V G G G G + + + + 2 PIC20702 PIC20701 N Y Y 3. i G + Sem Sem Sem Sem ELA ELA eader Sem D D COP32 P32 H C212 Cap 10uF C218 Cap 10uF C224 Cap 10uF C230 Cap 10uF COC212 COC218 COC224 COC230 C206 Cap 10uF COC206 PIC21202 PIC21201 PIC21802 PIC21801 PIC22402 PIC22401 PIC23002 PIC23001 TRIG TRIG 1 2 PIC20602 PIC20601 POTRIGDELAYED0DIF0P POTRIGDELAYED0DIF0N 2 2 2 PIP3201 PIP3202 IF_P IF_N IF_P IF_N 2 2 _D _D _D _D L_P L_N eader eader eader ED ED ED ED P22 H P24 H P26 H COP22 COP24 COP26 eader eader Y Y Y Y T_1_P T_1_N T_2_P T_2_N T_3_P T_3_N T_4_P T_4_N P28 H P29 H COP28 COP29 ESTA ESTA PU PU PU PU PU PU PU PU ELA ELA ELA ELA 1 2 1 2 1 2 D D D D IN IN IN IN IN IN IN IN PED PED 1 2 1 2 POINPUT010P POINPUT010N POINPUT020P POINPUT020N POINPUT030P POINPUT030N POINPUT040P POINPUT040N POPEDESTAL0P POPEDESTAL0N TRIG TRIG TRIG TRIG NLTRIGDELAYED0DIF0P NLTRIGDELAYED0DIF0N PIP2201 PIP2202 PIP2401 PIP2402 PIP2601 PIP2602 i PIP2801 PIP2802 PIP2901 PIP2902 T_1_P T_1_N T_2_P T_2_N T_3_P T_3_N L_P L_N L_P L_N Sem D 3 3 T_1_P T_1_N T_2_P T_2_N T_3_P T_3_N T_4_P T_4_N T_4_P T_4_N 3V PU PU PU PU PU PU N 3. NLINPUT010P NLINPUT010N NLINPUT020P NLINPUT020N NLINPUT030P NLINPUT030N G IN IN IN IN IN IN PU PU PU PU PU PU PU PU PU PU C241 Cap 100nF COC241 + ESTA ESTA ESTA ESTA IN IN IN IN IN IN IN IN IN IN NLINPUT040P NLINPUT040N 8 7 6 5 PIC24102 PIC24101 i PED PED PED PED NLPEDESTAL0P NLPEDESTAL0N PIU3408 PIU3407 PIU3406 PIU3405 Z D Y Sem cc D D D D 3V 3V 3V 3V N S100 V N N N N 3. 3. 3. 3. G D D 3V G G G G COC240 C240 Cap 100pF + + + + N 3. D 3V G + 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 PIC24002 PIC24001 N 3. C bb i 65LV G + 8 7 6 5 PIU2408 PIU2407 PIU2406 PIU2405 PIU2608 PIU2607 PIU2606 PIU2605 PIU2808 PIU2807 PIU2806 PIU2805 PIU3008 PIU3007 PIU3006 PIU3005 N A B V 34 U SN COU34 PIU3108 PIU3107 PIU3106 PIU3105 Z Z Z Z D D D D Y Y Y Y Sem cc cc cc cc N N N N S100 S100 S100 S100 V V V V Z 1 2 3 4 Y D cc G G G G D D D D N S100 C239 Cap 10uF V COC239 G D PIU3401 PIU3402 PIU3403 PIU3404 PIC23902 PIC23901 C bb C bb C bb C bb 65LV 65LV 65LV 65LV N A B V N A B V N A B V N A B V 24 26 28 30 C bb 65LV U SN U SN U SN U SN COU24 COU26 COU28 COU30 N A B V 31 U SN COU31 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 IF_P IF_N 1 2 3 4 _D _D PIU2401 PIU2402 PIU2403 PIU2404 PIU2601 PIU2602 PIU2603 PIU2604 PIU2801 PIU2802 PIU2803 PIU2804 PIU3001 PIU3002 PIU3003 PIU3004 ED ED PIU3101 PIU3102 PIU3103 PIU3104 Y Y 2 2 ELA ELA D D L_P L_N T_1_P T_1_N T_2_P T_2_N T_3_P T_3_N T_4_P T_4_N PU PU PU PU PU PU PU PU ESTA ESTA PECL_TRIG PECL_TRIG LV LV NLLVPECL0TRIGDELAYED0DIF0P NLLVPECL0TRIGDELAYED0DIF0N PECL_IN PECL_IN PECL_IN PECL_IN PECL_IN PECL_IN PECL_IN PECL_IN PECL_PED PECL_PED LV LV LV LV LV LV LV LV NLLVPECL0INPUT010P NLLVPECL0INPUT010N NLLVPECL0INPUT020P NLLVPECL0INPUT020N NLLVPECL0INPUT030P NLLVPECL0INPUT030N NLLVPECL0INPUT040P NLLVPECL0INPUT040N LV LV NLLVPECL0PEDESTAL0P NLLVPECL0PEDESTAL0N IF_P IF_N _D _D ED ED T_1_P T_2_P T_3_P T_4_P Y Y T_1_N T_2_N T_3_N T_4_N PU PU PU PU L_P L_N PU PU PU PU ELA ELA D D ESTA ESTA PECL_IN PECL_IN PECL_IN PECL_IN 1 1 PECL_IN PECL_IN PECL_IN PECL_IN LV LV LV LV LV LV LV LV POLVPECL0INPUT010P POLVPECL0INPUT020P POLVPECL0INPUT030P POLVPECL0INPUT040P PECL_PED PECL_PED PECL_TRIG PECL_TRIG POLVPECL0INPUT010N POLVPECL0INPUT020N POLVPECL0INPUT030N POLVPECL0INPUT040N LV LV LV LV POLVPECL0PEDESTAL0P POLVPECL0PEDESTAL0N POLVPECL0TRIGDELAYED0DIF0P POLVPECL0TRIGDELAYED0DIF0N B C A D

Figure A.19: TIB: LVPECL to LVDS translators 230 A. Schematics B C A D 1 r 1 7 7 Semi Semi F F o 5 6 7 u u Semi 0 0 F ed COC251 COC267 COC277 C2 C2 Cap 1 C2 Cap 1 u ej 0 1 Semi D D D F Cap 1 6 u PIC25102 PIC25101 PIC26702 PIC26701 PIC27702 PIC27701 N N N . T 0 n G G G COC261 C2 Cap 1 A o i s V D i s i PIC26102 PIC26101 u .3 N V V V L G +3 .3 .3 .3 F F F Rev 0 6 6 Semi Semi Semi n n n 5 6 7 +3 +3 +3 0 0 0 0 0 0 : COC250 COC266 COC276 C2 Cap 1 C2 Cap 1 C2 Cap 1 8 8 f F 0 Semi D D D n 6 By PIC25002 PIC25001 PIC26602 PIC26601 PIC27602 PIC27601 0 N N N n o 0 COC260 G G G C2 Cap 1 eet D raw PIC26002 PIC26001 N Sh D G r r r r r r o o o o o o PIL1001 PIL1201 PIL1701 PIL1901 PIL2101 PIL2301 H H H ct ct ct ct ct ct c u u u u u u u u u o 1 1 1 H H H d d d d d d r r u u u D o o PIL1501 PIL1601 In 1 In In 1 In In 1 In H ct ct u u u 1 0 2 7 9 1 3 H .Sch d d 1 1 1 1 2 2 u 5 Semi rs rs F er COL10 COL12 COL17 COL19 COL21 COL23 L L In 1 In L L L L 6 u u u g 9 o o 0 Semi g F 5 6 PIL1002 PIL1202 PIL1702 PIL1902 COC265 PIL2102 PIL2302 4 b b C2 Cap 1 ri u 1 1 h h 0 D COC249 COL15 COL16 g g T L L C2 Cap 1 PIC26502 PIC26501 F F N 3 2 ei Semi Semi ei n n D G 4 6 PIL1502 PIL1602 0 0 N N PIC24902 PIC24901 F N ereo 2 0 0 Semi 9 5 Semi Semi n F F COC243 COC262 ..\ G 7 C2 Cap 1 C2 Cap 1 5 7 0 St u u F 3 e\ 0 Semi 0 0 n D D COC259 COC272 COC275 5 v C2 Cap 1 C2 Cap 1 C2 Cap 1 0 PIC24302 PIC24301 PIC26202 PIC26201 N N F ri 0 4 Semi D D D COC253 n G G C2 Cap 1 PIC25902 PIC25901 PIC27202 PIC27201 PIC27502 PIC27501 6 0 N N N F 3 8 0 Semi D e D n COC264 1 G G G l 4 C2 Cap 1 PIC25302 PIC25301 0 er N 0 g 0 D 2 o G COC248 / C2 Cap 1 PIC26402 PIC26401 o N mb 2 D u 1 G G PIC24802 PIC24801 / \ N F F N 0 8 4 Semi Semi n n G 3 C: 5 7 0 0 0 0 COC258 COC274 C2 Cap 1 C2 Cap 1 P N D D _ _ PIC25802 PIC25801 PIC27402 PIC27401 N N 1 1 P N _ _ _ _ G G e: e T T P N 7 7 2 P N P N l e: t ze l _ _ _ _ at _ _ _ _ i A 2 2 T T 3 3 5 5 P N PU PU T Si D Fi ______T T er 2 T T 6 6 T T T T P N PU PU U U _ _ _ _ T T 2 T T 8 8 O O 1 2 PU PU P N ead PU PU PU PU U U ______COP42 T T T T P4 H T T 4 4 IN IN O O PU PU U U U U ______CL CL T T O O O O IN IN PU PU P N ______CL CL CL CL PE PE 7 7 PIP4201 PIP4202 6 6 IN IN PU PU V V _ _ _ _ CL CL CL CL CL CL PE PE PE PE L L T T IN IN V V V V _ _ CL CL POLVPECL0OUTPUT010P POLVPECL0OUTPUT010N PE PE PE PE PE PE L L L L er 2 PU PU V V V V V V CL CL PE PE POLVPECL0INPUT020P POLVPECL0INPUT020N POLVPECL0OUTPUT070P POLVPECL0OUTPUT070N L L L L L L 4 IN IN 1 2 ead V V P N _ _ COP34 POLVPECL0OUTPUT030P POLVPECL0OUTPUT030N POLVPECL0OUTPUT050P POLVPECL0OUTPUT050N POLVPECL0INPUT060P POLVPECL0INPUT060N PE PE _ _ P3 H L L 1 1 P N V V _ _ _ _ CL CL POLVPECL0INPUT080P POLVPECL0INPUT080N L L 2 2 T T P N P N _ _ _ _ PE PE _ _ PIP3401 PIP3402 POLVPECL0INPUT040P POLVPECL0INPUT040N er 2 T T 2 2 7 7 PU PU V V P N P N _ _ _ _ NLLVPECL0INPUT060P NLLVPECL0INPUT060N _ _ _ _ T T L L 0 er 2 T T 1 2 PU PU T T 3 3 P N 5 5 P N P N ead U U ______COP40 P4 H 6 4 4 6 6 8 8 O O IN IN 1 2 PU PU T T T T ead PU PU ______COP46 T T P4 H T T T T T T IN IN P N PU PU PU PU U U _ _ _ _ CL CL CL CL T T T T PIP4001 PIP4002 4 4 O O PU PU PU PU PU PU P N U U U U ______CL CL PE PE PE PE PIP4601 PIP4602 T T 8 8 O O IN IN O O IN IN IN IN V V V V ______1 1 CL CL PE PE NLLVPECL0OUTPUT010P NLLVPECL0OUTPUT010N L L L L er 2 T T _ PU PU V V T R_ CL CL CL CL CL CL CL CL CL CL PE PE NLLVPECL0INPUT020P NLLVPECL0INPUT020N L L 1 IN IN 1 2 PU PU ead V V _ _ 3 5 3 5 COP41 NLLVPECL0OUTPUT070P NLLVPECL0OUTPUT070N PE PE PE PE PE PE PE PE PE PE P4 H L L _ _ IN IN CC_ CC_ V V V V V V V V V V _ _ 7 T R_ T R_ 7 CL CL NLVCC0T01 NLVCC0R01 NLLVPECL0OUTPUT030P NLLVPECL0OUTPUT030N V V L L L L L L L L L L _ P N D D T R_ CL CL PE PE _ _ PIP4101 PIP4102 5 5 N N CC_ CC_ CC_ CC_ V V _ _ PE PE NLVCC0T03 NLVCC0R03 NLLVPECL0INPUT040P NLLVPECL0INPUT040N NLVCC0T05 NLVCC0R05 G G V V L L V V T T CC_ CC_ V V NLVCC0T07 NLVCC0R07 NLLVPECL0INPUT080P NLLVPECL0INPUT080N V V L L er 2 B B B B B B B B B B PU PU D D 0 9 8 7 6 5 4 3 2 1 T T 3 2 1 1 1 1 1 1 1 1 1 1 2 ead N N U U D D D D COP33 P3 H G G O O PIJ38020B PIJ38019B PIJ38018B PIJ38017B PIJ38016B PIJ38015B PIJ38014B PIJ38013B PIJ38012B PIJ38011B N N N N _ _ G G G G - - + + D D D D D D D D D D P N D 0 9 8 7 6 5 4 3 2 1 CL CL D _ _ eeT eeT ccT ccR eeR eeR er 2 2 1 1 1 1 1 1 1 1 1 PIP3301 PIP3302 T RD B B B B B B B B B B D D D D D D D D D D 1 1 T RD V V V V V V 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 _ _ PE PE PIJ38020D PIJ38019D PIJ38018D PIJ38017D PIJ38016D PIJ38015D PIJ38014D PIJ38013D PIJ38012D PIJ38011D 9 er 2 2 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 2 T T ead V V COP39 NLLVPECL0OUTPUT050P NLLVPECL0OUTPUT050N P3 H L L - 5 - PIJ50020B PIJ50019B PIJ50018B PIJ50017B PIJ50016B PIJ50015B PIJ50014B PIJ50013B PIJ50012B PIJ50011B PIJ50020D PIJ50019D PIJ50018D PIJ50017D PIJ50016D PIJ50015D PIJ50014D PIJ50013D PIJ50012D PIJ50011D + + 1 2 ead PU PU D D T T COP45 P4 H - - - - eeT eeT ccT ccR eeR eeR T + + RD + + T RD P N U U n D D V V V V V V D D _ _ o eeT eeT ccT eeT eeT ccT PIP3901 PIP3902 ccR eeR eeR ccR eeR eeR -1 T T O O RD RD i 3 3 T T RD RD P N 8 _ _ V V V V V V V V V V V V F2 F1 F0 _ _ e _ _ 0 l PIP4501 PIP4502 ect E E E T T 7 7 0 t l _ _ CL CL ab 1 6 6 s -D -D -D T T 6 PU PU i n 7 PE PE D D D T T o e Sel S -1 i Fau D PU PU V V 8 U U n n eeT eeR eeR x x O F2 F1 F0 B e T T L L 0 o o l -1 -1 8 O O i i V T T MO MO MO Rat L V V ect E E E 0 t 8 8 U U 3 _ _ l F2 F1 F0 F2 F1 F0 e e COJ38B ab 1 J SFP-1 0 0 l l s -D -D -D O O ect ect E E E E E E 6 i 0 0 t t _ _ 7 l l CL CL D D D ab ab 1 1 e Sel S s s -D -D -D -D -D -D Fau D 6 6 B B B B B B B B B B i i eeT eeR eeR x x O 7 7 D CL CL PE PE 1 2 3 4 5 6 7 8 9 0 D D D D D D e Sel e Sel S S 8 1 V T T MO MO MO Rat L V V Fau D Fau D V V 3 eeT eeR eeR eeT eeR eeR x x O x x O B D PE PE COJ38D J SFP-1 L L PIJ3801B PIJ3802B PIJ3803B PIJ3804B PIJ3805B PIJ3806B PIJ3807B PIJ3808B PIJ3809B PIJ38010B 0 0 V T T MO MO MO Rat L V V V T T MO MO MO Rat L V V V V 5 5 D J SFP-1 J SFP-1 L L COJ50B COJ50D N D D D D D D D D D D D 1 2 3 4 5 6 7 8 9 0 G 3 1 N B B B B B B B B B B D D D D D D D D D D 8 K 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 G 0 PIJ3801D PIJ3802D PIJ3803D PIJ3804D PIJ3805D PIJ3806D PIJ3807D PIJ3808D PIJ3809D PIJ38010D 3 1 1 COR48 0 V R4 Res 1 K D PIJ5001B PIJ5002B PIJ5003B PIJ5004B PIJ5005B PIJ5006B PIJ5007B PIJ5008B PIJ5009B PIJ50010B PIJ5001D PIJ5002D PIJ5003D PIJ5004D PIJ5005D PIJ5006D PIJ5007D PIJ5008D PIJ5009D PIJ50010D 0 .3 N PIR4801 PIR4802 V R4 Res 1 COR40 D D D G +3 PIR4002 PIR4001 .3 N N N D D G G G +3 N N G G 3 3 3 3 3 8 9 7 K K K K 0 0 0 0 3 3 V V V V COR53 COR58 COR59 COR67 9 7 R5 Res 1 R5 Res 1 R5 Res 1 R6 Res 1 K K 0 0 .3 .3 .3 .3 PIR5302 PIR5301 PIR5801 PIR5802 PIR5902 PIR5901 PIR6701 PIR6702 V V R6 Res 1 R7 Res 1 COR69 COR77 +3 +3 +3 +3 .3 .3 PIR6902 PIR6901 PIR7702 PIR7701 PIJ4001 +3 +3 0 4 J COJ40 et 1 _ ck E 1 So 5 7 BL _ _ S_ PIJ3501 PIJ3701 PIJ4601 E E 3 O _ ISA L 1 5 PIJ4301 PIJ4401 PIJ4701 PIJ4901 PIJ5201 E 5 7 6 BL BL D _ _ 3 3 4 _ J J J COJ35 COJ37 POLOS01 COJ46 PIJ5401 PIJ5601 PIJ5801 T T 3 7 3 4 7 9 2 et et et BL X _ _ L L 4 4 4 4 5 ISA ISA COJ43 COJ44 COJ47 COJ49 COJ52 T J J J J J ck ck ck T T 4 6 8 et et et et et U U D D L L 5 5 5 ISA _ _ 3 POTX0DISABLE01 COJ54 COJ56 COJ58 So So So J J J ck ck ck ck ck et et et U U FA D FA X X _ _ S_ _ 5 7 So So So So T So T ck ck ck FA FA X X O X 5 5 _ S_ _ S_ POTX0DISABLE05 POTX0DISABLE07 T T L T So So So X O X O 1 5 _ _ T L T L POTX0FAULT01 POTX0DISABLE03 POLOS03 POTX0FAULT05 3 7 F2 F2 POTX0FAULT03 POLOS05 POTX0FAULT07 POLOS07 _ _ 3 3 E E 2 1 K K F2 F2 NLDEF201 NLDEF205 D D 0 0 3 3 E E 1 5 V V COR42 COR61 4 0 R4 Res 1 R6 Res 1 K K NLDEF203 NLDEF207 _ _ D D 0 0 .3 .3 PIR4202 PIR4201 PIR6102 PIR6101 3 7 V V R5 Res 1 R7 Res 1 COR54 COR70 F1 F1 _ _ +3 +3 .3 .3 PIR5402 PIR5401 PIR7002 PIR7001 3 3 E E 1 4 2 K K F1 F1 _ D D NLDEF101 NLDEF105 +3 +3 0 0 3 3 E E 3 5 7 V V 5 2 R4 Res 1 R6 Res 1 COR44 COR62 K K F0 NLDEF103 NLDEF107 _ _ _ D D 0 0 PIR4402 PIR4401 PIR6202 PIR6201 .3 .3 E COR55 COR72 V V R5 Res 1 R7 Res 1 F0 F0 F0 D NLDEF001 +3 +3 .3 .3 3 3 PIR5502 PIR5501 PIR7202 PIR7201 E E E 6 4 K K NLDEF003 NLDEF005 NLDEF007 D D D +3 +3 0 0 3 3 V V 6 3 R4 Res 1 R6 Res 1 COR46 COR64 K K 0 0 .3 .3 PIR4602 PIR4601 PIR6402 PIR6401 COR56 COR73 V V R5 Res 1 R7 Res 1 +3 +3 .3 .3 PIR5602 PIR5601 PIR7302 PIR7301 +3 +3 1 Semi F 8 u 0 C2 Cap 1 COC281 1 Semi D F 7 u PIC28102 PIC28101 N 7 7 0 Semi Semi F F G 4 5 C2 Cap 1 COC271 u u 0 0 D C2 Cap 1 C2 Cap 1 COC247 COC257 PIC27102 PIC27101 N V D D G .3 N N PIC24702 PIC24701 PIC25702 PIC25701 F 0 Semi n G G 8 +3 0 V 0 COC280 C2 Cap 1 .3 F V V 0 Semi D n 7 +3 .3 .3 0 N F F PIC28002 PIC28001 6 6 Semi Semi 0 n n G COC270 4 5 C2 Cap 1 +3 +3 0 0 4 4 0 0 D C2 Cap 1 C2 Cap 1 COC246 COC256 N PIC27002 PIC27001 D D G PIC24602 PIC24601 PIC25602 PIC25601 r r N N o o G G H PIL2201 PIL2401 ct ct u u u 1 H d d r r u o o In 1 In H PIL1801 PIL2001 r r r r ct ct u o o o o u u 1 2 4 H H H PIL901 PIL1101 PIL1301 PIL1401 d d ct ct ct ct 2 2 u u u u u u u COL22 COL24 1 1 In 1 In L L H H d d d d u u 9 Semi F In 1 In In 1 In 8 0 7 u PIL2202 PIL2402 1 2 0 COL18 COL20 L L 1 3 4 C2 Cap 1 COC279 F 9 1 1 1 3 Semi 9 Semi n D F 6 L L L L COL9 COL11 COL13 COL14 6 0 u F PIL1802 PIL2002 PIC27902 PIC27901 N 3 0 Semi 5 0 Semi n F 7 C2 Cap 1 G 4 C2 Cap 1 0 PIL902 PIL1102 PIL1302 PIL1402 COC263 COC269 u F 2 0 Semi 0 n D D 4 COC273 C2 Cap 1 C2 Cap 1 0 COC245 PIC26302 PIC26301 PIC26902 PIC26901 F N N F 2 0 Semi 8 Semi n D D n 5 C2 Cap 1 G G 7 COC242 0 0 N N PIC24502 PIC24501 PIC27302 PIC27301 0 5 0 Semi D F COC252 G C2 Cap 1 G 5 C2 Cap 1 er 2 PIC24202 PIC24201 COC278 u N 0 D D G COC255 6 C2 Cap 1 1 2 PIC25202 PIC25201 PIC27802 PIC27801 ead N N F 8 Semi D n P3 H G G 6 COP36 0 N F PIC25502 PIC25501 4 0 Semi n G 4 C2 Cap 1 0 COC268 P N 0 D _ _ C2 Cap 1 COC244 1 1 N PIP3601 PIP3602 PIC26802 PIC26801 P N 4 _ _ Semi D _ _ G 5 T T PIC24402 PIC24401 6 6 P N N _ _ _ _ G COC254 C2 Cap 7 7 PU PU T T _ _ D T T IN IN N PU PU PIC25402 PIC25401 P N _ _ _ _ T T G PU PU 4 4 P N P N P N U U _ _ _ _ CL CL _ _ _ _ er 2 5 5 O O IN IN T T 0 0 P N 2 2 ______PE PE 4 T T 1 1 1 2 T T T T P N ead PU PU V V _ _ _ _ CL CL CL CL T T L L P4 H NLLVPECL0INPUT010P NLLVPECL0INPUT010N COP44 T T 3 3 PU PU PU PU PU PU U U _ _ PE PE PE PE T T T T T T O O IN IN PU PU P N V V V V U U U U ______L L L L 5 5 O O IN IN O O PU PU PIP4401 PIP4402 ______CL CL CL CL POLVPECL0OUTPUT060P POLVPECL0OUTPUT060N POLVPECL0INPUT070P POLVPECL0INPUT070N T T IN IN 3 3 _ _ CL CL CL CL CL CL PE PE PE PE PU PU V V V V CL CL PE PE PE PE PE PE L L L L er 2 IN IN V V V V V V _ _ PE PE POLVPECL0OUTPUT040P POLVPECL0OUTPUT040N POLVPECL0INPUT050P POLVPECL0INPUT050N L L L L L L 5 1 2 ead V V P N CL CL _ _ P3 H L L POLVPECL0OUTPUT000P POLVPECL0OUTPUT000N POLVPECL0INPUT010P POLVPECL0INPUT010N COP35 POLVPECL0OUTPUT020P POLVPECL0OUTPUT020N 6 6 P N _ _ _ _ PE PE er 2 POLVPECL0INPUT030P POLVPECL0INPUT030N 7 7 T T V V P N P N P N P N ______L L NLLVPECL0INPUT050P NLLVPECL0INPUT050N 8 T T PIP3501 PIP3502 1 2 0 0 P N 0 0 2 2 P N 4 4 P N ead PU PU ______T T P4 H COP48 er 2 1 1 3 3 5 5 PU PU T T T T T T T T U U ______8 T T T T T T O O IN IN 1 2 P N ead PU PU PU PU PU PU PU PU ______T T T T T T T T P3 H COP38 7 7 PU PU PU PU PU PU PIP4801 PIP4802 U U U U U U U U _ _ CL CL CL CL T T O O IN IN O O O O IN IN O O IN IN P N ______PE PE PE PE er 2 3 3 PU PU PIP3801 PIP3802 V V V V _ _ CL CL CL CL CL CL CL CL CL CL CL CL CL CL L L L L 3 NLLVPECL0OUTPUT060P NLLVPECL0OUTPUT060N T T IN IN 1 2 ead _ _ 6 6 PE PE PE PE PE PE PE PE PE PE PE PE PE PE COP43 P4 H _ PU PU V V V V V V V V V V V V V V 0 2 4 T R_ 0 2 4 CL CL L L L L L L L L L L L L L L NLLVPECL0OUTPUT000P NLLVPECL0OUTPUT000N NLLVPECL0OUTPUT020P NLLVPECL0OUTPUT020N _ _ _ IN IN P N _ _ T R_ T R_ T R_ PE PE _ _ PIP4301 PIP4302 4 4 CC_ CC_ V V D D _ _ CL CL V V L L NLVCC0T06 NLVCC0R06 NLLVPECL0INPUT070P NLLVPECL0INPUT070N N N T T CC_ CC_ CC_ CC_ CC_ CC_ D D D G G PE PE V V V V V V NLVCC0T00 NLVCC0R00 NLVCC0T02 NLVCC0R02 NLVCC0T04 NLVCC0R04 N N N PU PU V V D D D D D D D G G G T T NLLVPECL0INPUT030P NLLVPECL0INPUT030N L L N N N N N N N U U D D G G G G G G G O O N N _ _ G G A A A A A A A A A A C C C C C C C C C C C C C C C C C C C C 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 CL CL er 2 2 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 A A A A A A A A A A PIL2802 0 9 8 7 6 5 4 3 2 1 PE PE 7 PIJ38020A PIJ38019A PIJ38018A PIJ38017A PIJ38016A PIJ38015A PIJ38014A PIJ38013A PIJ38012A PIJ38011A PIJ38020C PIJ38019C PIJ38018C PIJ38017C PIJ38016C PIJ38015C PIJ38014C PIJ38013C PIJ38012C PIJ38011C PIL2902 PIJ50020C PIJ50019C PIJ50018C PIJ50017C PIJ50016C PIJ50015C PIJ50014C PIJ50013C PIJ50012C PIJ50011C 2 1 1 1 1 1 1 1 1 1 1 2 r ead V V o L L P4 H - - - NLLVPECL0OUTPUT040P NLLVPECL0OUTPUT040N COP47 - - - er 2 + + + + + + PIJ50020A PIJ50019A PIJ50018A PIJ50017A PIJ50016A PIJ50015A PIJ50014A PIJ50013A PIJ50012A PIJ50011A r F F ct 4 6 D D D Semi Semi o u n u D D D - 8 - eeT eeT ccT eeT eeT ccT eeT eeT ccT 7 1 1 ccR eeR eeR ccR eeR eeR ccR eeR eeR H T T T RD RD RD 0 0 + + d 1 2 ead F F T T T ct PIC31402 PIC31602 RD RD RD 2 P N u 8 0 0 0 D Semi Semi V V V V V V V V V V V V V V V V V V u n u D _ _ COL28 COP37 L In 1 P3 H 9 eeT eeT ccT 1 2 C3 Cap 1 C3 Cap 1 ccR eeR eeR H T RD 0 0 COC314 COC316 PIC31802 PIC32002 PIP4701 PIP4702 d 6 6 T RD 2 u 0 0 V V V V V V _ _ L In 1 COC318 COC320 COL29 C3 Cap 1 C3 Cap 1

T T

PIC31401 PIC31601 PIL2801

P N

0 _ _

0 PIP3701 PIP3702 PIC31801 PIC32001 PIL2901

2 2

PU PU PIJ3800 n n 0 n

_ _ T T o o 0 o -1 -1 -1 i i i T T PIJ5000 2 2 8 8 8 U U n F2 F1 F0 F2 F1 F0 F2 F1 F0 e e e 0 0 0 o l l l -1 O O i ect ect ect E E E E E E E E E PU PU 0 0 0 t t t 8 _ _ l l l F2 F1 F0 e ab ab ab 1 1 1 T T 0 l s s s -D -D -D -D -D -D -D -D -D ect E E E 6 6 6 F i i i 0 t U U 5 7 Semi Semi 7 7 7 l p F CL CL D D D D D D D D D ab 1 1 1 e Sel e Sel e Sel S S S 0 u s -D -D -D O O Fau D Fau D Fau D 6 F PIC31502 PIC31702 i 9 1 0 0 eeT eeR eeR eeT eeR eeR eeT eeR eeR Semi Semi _ _ x x O x x O x x O 7 A C C p F PE PE D D D 1 2 e Sel C3 Cap 1 C3 Cap 1 S COC315 COC317 PIC31902 PIC32102 8 8 0 0 u V T T MO MO MO Rat L V V V T T MO MO MO Rat L V V V T T MO MO MO Rat L V V Fau D V V 3 3 5 0 0 eeT eeR eeR x x O A CL CL J SFP-1 J SFP-1 J SFP-1 L L COJ38A COJ38C COJ50C C3 Cap 1 C3 Cap 1 0 V T T MO MO MO Rat L V V PIC31501 PIC31701 COC319 COC321 5 PE PE J SFP-1 COJ50A PIC31901 PIC32101 C C C C C C C C C C C C C C C C C C C C A A A A A A A A A V V A 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 0 1 2 3 4 5 6 7 8 9 0 L L 1 1 1 A A A A A A A A A A D D 1 2 3 4 5 6 7 8 9 0 1 PIJ3801A PIJ3802A PIJ3803A PIJ3804A PIJ3805A PIJ3806A PIJ3807A PIJ3808A PIJ3809A PIJ38010A PIJ3801C PIJ3802C PIJ3803C PIJ3804C PIJ3805C PIJ3806C PIJ3807C PIJ3808C PIJ3809C PIJ38010C PIJ5001C PIJ5002C PIJ5003C PIJ5004C PIJ5005C PIJ5006C PIJ5007C PIJ5008C PIJ5009C PIJ50010C N N D D D D D G G PIJ5001A PIJ5002A PIJ5003A PIJ5004A PIJ5005A PIJ5006A PIJ5007A PIJ5008A PIJ5009A PIJ50010A N N N N N D D D D D G G G G G N N N N N G G G G G 3 3 3 3 3 9 7 9 7 8 K K K K K 0 0 0 0 0 3 3 0 1 V V V V V R3 Res 1 R4 Res 1 R4 Res 1 R5 Res 1 R7 Res 1 COR39 COR47 COR49 COR57 COR78 K K 0 0 .3 .3 .3 .3 .3 3 PIR3902 PIR3901 PIR4701 PIR4702 PIR4902 PIR4901 PIR5701 PIR5702 PIR7801 PIR7802 8 V V R6 Res 1 R7 Res 1 COR60 COR71 K +3 +3 +3 +3 +3 0 .3 .3 PIR6002 PIR6001 PIR7102 PIR7101 V R6 Res 1 COR68 +3 +3 .3 PIR6801 PIR6802 +3 0 _ E 2 4 6 BL PIJ3901 PIJ4501 _ _ _ 0 E E E 9 5 PIJ3401 PIJ3601 PIJ5901 2 2 2 _ 3 4 ISA _ _ _ J J COJ39 COJ45 T 2 4 6 4 6 9 et et BL BL BL PIJ4101 PIJ4201 PIJ4801 PIJ5101 PIJ5301 PIJ5501 PIJ5701 D _ _ _ L 3 3 5 _ F2 F1 F0 J J J ck ck T T T COJ34 COJ36 COJ59 1 2 8 1 3 5 7 et et et U E E E X L L L 4 4 4 5 5 5 5 ISA ISA ISA 0 2 6 T So J J D D D So J J J J J COJ41 COJ42 NLDEF202 NLDEF102 NLDEF002 COJ48 COJ51 COJ53 COJ55 COJ57 ck ck ck et et et et et et et U U U FA D D D _ S_ _ S_ _ _ S_ So So So ck ck ck ck ck ck ck POTX0DISABLE00 FA FA FA X O X O X X O _ _ _ 4 T L So So T L So So T So So So T L X X X 0 S_ _ T T T POTX0FAULT00 POLOS00 POTX0DISABLE02 POLOS02 POTX0DISABLE04 POTX0DISABLE06 POLOS06 O 4 6 F2 _ _ L POTX0FAULT02 POTX0FAULT04 POTX0FAULT06 3 1 1 E 0 1 K F2 F2 _ D NLDEF200 POLOS04 0 3 3 3 E E 0 3 4 V R4 Res 1 K K K F1 COR41 D D NLDEF204 NLDEF206 0 0 0 .3 E PIR4102 PIR4101 0 4 6 V V V R5 Res 1 R6 Res 1 R7 Res 1 COR50 COR63 COR74 _ _ _ D +3 .3 .3 .3 3 NLDEF100 PIR5002 PIR5001 PIR6302 PIR6301 PIR7402 PIR7401 3 K F0 F1 F1 +3 +3 +3 0 3 3 3 E E E 6 V 1 5 5 R4 Res 1 COR43 K K K _ D D D 0 0 0 .3 NLDEF000 NLDEF104 NLDEF106 4 PIR4302 PIR4301 V V V R5 Res 1 R6 Res 1 R7 Res 1 COR51 COR65 COR75 F0 _ +3 .3 .3 .3 3 PIR5102 PIR5101 PIR6502 PIR6501 PIR7502 PIR7501 E 5 K F0 D +3 +3 +3 0 NLDEF006 3 3 3 E V 2 6 6 R4 Res 1 K K K COR45 D 0 0 0 .3 NLDEF004 V V V PIR4502 PIR4501 R5 Res 1 R6 Res 1 R7 Res 1 COR52 COR66 COR76 +3 .3 .3 .3 PIR5202 PIR5201 PIR6602 PIR6601 PIR7602 PIR7601 +3 +3 +3 B C A D

Figure A.20: TIB: Optical transceivers to/from neighbours A. Schematics 231 B C A D 2 2 2 1 2 eader P4 H COP4 1 2 1 2 eader eader edor COP6 COP8 P6 H P8 H Tej

PIP401 PIP402 on . si A 8 8 PIP601 PIP602 PIP801 PIP802 L_P L_N s 2 Revi IF_P IF_N Lui ESTA ESTA _D _D 1 2 eader of

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oc Y Y _SFP_11_P _SFP_11_N raw PIP201 PIP202 ELA ELA Sheet D SchD PECL_PED PECL_PED TRA TRA D D ay. NLLVPECL0PEDESTAL0P NLLVPECL0PEDESTAL0N LIB_P LIB_N LV LV el ay el PECL_EX PECL_EX b_and_D PECL_CA PECL_CA PECL_TRIG PECL_TRIG i NLLVPECL0EXTRA0SFP0110P NLLVPECL0EXTRA0SFP0110N LV LV 2 NLLVPECL0CALIB0P NLLVPECL0CALIB0N NLLVPECL0TRIGDELAYED0DIF0P NLLVPECL0TRIGDELAYED0DIF0N LV LV LV LV b_and_D i 1 2 eader gger COP3 SFP_cal P3 H 2 2 \ . . Tri ve\ SFP_cal PIP301 PIP302 2 1 2 1 2 eader eader ri ereo COP5 COP7 P5 H P7 H D St e 7 1 2 7 eader ber 2013 COP1 P1 H PIP501 PIP502 PIP701 PIP702 oogl L_FB_P L_FB_N um 12/ G \ IF_P IF_N N 30/ C: PIP101 PIP102 ESTA ESTA _D _D ED ED Y Y i e e: 3 l e: t ze l at LIB_FB_P LIB_FB_N A ELA ELA _SFP_11_FB_P _SFP_11_FB_N Sem Ti Si D Fi PECL_PED PECL_PED i NLLVPECL0PEDESTAL0FB0P NLLVPECL0PEDESTAL0FB0N BED BED TRA TRA LV LV C15 Cap 10uF COC15 D N PIC1502 PIC1501 Sem PECL_CA PECL_CA G i NLLVPECL0CALIB0FB0P NLLVPECL0CALIB0FB0N LV LV COC20 C20 Cap 10uF D PECL_TO PECL_TO PECL_EX PECL_EX i 3V PIC2002 PIC2001 N Sem 3. NLLVPECL0TOBEDELAYED0DIF0P NLLVPECL0TOBEDELAYED0DIF0N NLLVPECL0EXTRA0SFP0110FB0P NLLVPECL0EXTRA0SFP0110FB0N G LV LV LV LV + Sem i COC14 C14 Cap 100nF D 3V COC10 C10 Cap 10uF PIC1402 PIC1401 N Sem 3. D i G + PIC1002 PIC1001 N G COC19 C19 Cap 100nF Sem D i PIC1902 PIC1901 N 6 6 or or 3V G COC5 C5 Cap 10uF PIL501 PIL601 Sem 3. D 1uH + PIC502 PIC501 N COC9 G Induct 1uH Induct C9 Cap 100nF D or or i i PIL701 PIL801 N PIC902 PIC901 i COL5 COL6 3V G L5 L6 1uH Sem Sem 3. Induct 1uH Induct PIL502 PIL602 + Sem i C4 Cap 100nF C13 Cap 10uF COC4 COC13 D D or or i COC11 COL7 COL8 C11 Cap 100nF L7 L8 PIL301 PIL401 PIC402 PIC401 PIC1302 PIC1301 N N Sem D i G G 1uH PIC1102 PIC1101 PIL702 PIL802 N Sem G Induct 1uH Induct COC18 C18 Cap 10uF Sem D i C16 Cap 100nF COC16 PIC1802 PIC1801 N D or or i G L3 L4 COL3 COL4 COC12 C12 Cap 100nF PIL101 PIL201 PIC1602 PIC1601 N Sem D i 1uH G PIL302 PIL402 PIC1202 PIC1201 N Sem G Induct 1uH Induct COC8 C8 Cap 10uF Sem D i COC6 C6 Cap 100nF N PIC802 PIC801 D i i COL1 COL2 COC17 G L1 L2 C17 Cap 100nF N PIC602 PIC601 Sem D G PIL102 PIL202 N Sem PIC1702 PIC1701 Sem G C3 Cap 10uF COC3 IF_P IF_N D IF_P IF_N COC1 C1 Cap 100nF C7 Cap 100nF COC7 N PIC302 PIC301 _D _D D D _D _D G 5 5 PIC102 PIC101 PIC702 PIC701 N N ED ED i G G ED ED Y Y Y Y Sem ELA ELA L_FB_P L_FB_N ELA ELA COC2 D D C2 Cap 100nF _SFP_11_FB_P _SFP_11_FB_N _SFP_11_P _SFP_11_N L_P L_N D BED BED PIC202 PIC201 N ESTA ESTA G TRA TRA TRA TRA ESTA ESTA PECL_TO PECL_TO PECL_TRIG PECL_TRIG PECL_PED PECL_PED PECL_EX PECL_EX PECL_EX PECL_EX LV LV LV LV PECL_PED PECL_PED LIB_FB_P LIB_FB_N LIB_P LIB_N POLVPECL0TOBEDELAYED0DIF0P POLVPECL0TOBEDELAYED0DIF0N POLVPECL0TRIGDELAYED0DIF0P POLVPECL0TRIGDELAYED0DIF0N LV LV LV LV LV LV POLVPECL0PEDESTAL0FB0P POLVPECL0PEDESTAL0FB0N POLVPECL0EXTRA0SFP0110FB0P POLVPECL0EXTRA0SFP0110FB0N POLVPECL0EXTRA0SFP0110P POLVPECL0EXTRA0SFP0110N LV LV POLVPECL0PEDESTAL0P POLVPECL0PEDESTAL0N IF_P IF_N IF_P IF_N _D _D PECL_CA PECL_CA PECL_CA PECL_CA _D _D ED ED LV LV LV LV ED ED Y Y Y Y POLVPECL0CALIB0FB0P POLVPECL0CALIB0FB0N POLVPECL0CALIB0P POLVPECL0CALIB0N ELA ELA ELA ELA D D _SFP_11_FB_P _SFP_11_FB_N _SFP_11_P _SFP_11_N L_FB_P L_FB_N L_P L_N 4 4 BED BED TRA TRA TRA TRA ESTA ESTA ESTA ESTA PECL_TO PECL_TO PECL_TRIG PECL_TRIG PECL_EX PECL_EX PECL_EX PECL_EX LV LV LV LV PECL_PED PECL_PED PECL_PED PECL_PED LIB_FB_P LIB_FB_N LIB_P LIB_N LV LV LV LV LV LV LV LV CC_T_10 CC_R_10 V V NLVCC0T010 NLVCC0R010 CC_T_11 CC_R_11 D D V V NLVCC0T011 NLVCC0R011 N N CC_T_9 CC_R_9 D D PECL_CA PECL_CA PECL_CA PECL_CA G G V V NLVCC0T09 NLVCC0R09 N N D D G G LV LV LV LV N N D D G G N N 20C 19C 18C 17C 16C 15C 14C 13C 12C 11C CC_T_8 CC_R_8 D G G V V NLVCC0T08 NLVCC0R08 N 20D 19D 18D 17D 16D 15D 14D 13D 12D 11D PIJ3020C PIJ3019C PIJ3018C PIJ3017C PIJ3016C PIJ3015C PIJ3014C PIJ3013C PIJ3012C PIJ3011C G - - 20B 19B 18B 17B 16B 15B 14B 13B 12B 11B + + PIJ3020D PIJ3019D PIJ3018D PIJ3017D PIJ3016D PIJ3015D PIJ3014D PIJ3013D PIJ3012D PIJ3011D D D - - eeT eeT ccT ccR eeR eeR TD PIJ3020B PIJ3019B PIJ3018B PIJ3017B PIJ3016B PIJ3015B PIJ3014B PIJ3013B PIJ3012B PIJ3011B + + RD N N TD RD V V V V V V G G - - eeT eeT ccT ccR eeR eeR TD + + RD TD RD V V V V V V eeT eeT ccT ccR eeR eeR PIL2702 TD RD TD RD V V V V V V i i 20A 19A 18A 17A 16A 15A 14A 13A 12A 11A or 3 3 on PIJ3020A PIJ3019A PIJ3018A PIJ3017A PIJ3016A PIJ3015A PIJ3014A PIJ3013A PIJ3012A PIJ3011A i Sem Sem e on - - i + + EF2 EF1 EF0 ect PIC31002 PIC31202 t e on L27 Induct 1uH eeT eeT ccT C310 Cap 100uF C312 Cap 100nF ccR eeR eeR COC310 COC312 COL27 sabl -D -D -D TD EF2 EF1 EF0 i RD ect TD i Sel RD t V V V e V V V D D D e Faul D S sabl -D -D -D EF2 EF1 EF0 ect PIC31001 PIC31201 PIL2701 i Sel t eeT eeR eeR D D D

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-D -D -D V Tx Tx MO MO MO Rat LO V V i Sel

0 eeT eeR eeR

D D D J3C SFP-1761008-1 0 e Faul D COJ3C S PIJ300 V Tx Tx MO MO MO Rat LO V V eeT eeR eeR i i on J3D SFP-1761008-1 COJ3D i V Tx Tx MO MO MO Rat LO V V e 1C 2C 3C 4C 5C 6C 7C 8C 9C J3B SFP-1761008-1 COJ3B EF2 EF1 EF0 ect 10C Sem Sem t 1D 2D 3D 4D 5D 6D 7D 8D 9D sabl -D -D -D PIC31102 PIC31302 PIJ301C PIJ302C PIJ303C PIJ304C PIJ305C PIJ306C PIJ307C PIJ308C PIJ309C PIJ3010C 10D i Sel D D D D 1B 2B 3B 4B 5B 6B 7B 8B 9B e Faul D C311 Cap 100pF C313 Cap 10uF S COC311 COC313 PIJ301D PIJ302D PIJ303D PIJ304D PIJ305D PIJ306D PIJ307D PIJ308D PIJ309D PIJ3010D 10B N eeT eeR eeR D D G PIC31101 PIC31301 PIJ301B PIJ302B PIJ303B PIJ304B PIJ305B PIJ306B PIJ307B PIJ308B PIJ309B PIJ3010B V Tx Tx MO MO MO Rat LO V V N N D D G G COJ3A J3A SFP-1761008-1 N N D G G N COR11 COR15 R11 Res3 10K R15 Res3 10K D D 1A 2A 3A 4A 5A 6A 7A 8A 9A 3V 3V G 10A PIR1102 PIR1101 PIR1501 PIR1502 N N R16 Res3 10K R20 Res3 10K 3. 3. COR16 COR20 3V 3V + + G G PIJ301A PIJ302A PIJ303A PIJ304A PIJ305A PIJ306A PIJ307A PIJ308A PIJ309A PIJ3010A PIR1602 PIR1601 PIR2001 PIR2002 R6 Res3 10K R10 Res3 10K 3. 3. D COR6 COR10 3V 3V + + N PIR602 PIR601 PIR1001 PIR1002 3. 3. D G + + N G R1 Res3 10K R5 Res3 10K COR1 COR5 3V 3V 2 2 PIR102 PIR101 PIR501 PIR502 3. 3. ED + + Y L ED ELA Y PIJ1001 ESTA ED BED J10 Socket ELA COJ10 Y D L PIJ801 PIJ901 PIJ1301 LIB L ELA J8 Socket J9 Socket J13 Socket PIJ401 PIJ501 PIJ601 PIJ701 COJ8 COJ9 COJ13 J4 Socket J5 Socket J6 Socket J7 Socket COJ4 COJ5 COJ6 COJ7 BLE_PED BLE_TO BLE_SFP_11 ESTA LIB S_TRIG BED ESTA PIJ1101 PIJ1201 LIB ISA ISA ISA S_SFP_11 LO J11 Socket J12 Socket COJ11 COJ12 BLE_CA PIJ101 PIJ201 _D _D _D LO J1 Socket J2 Socket COJ1 COJ2 POLOS0TRIGDELAYED LT_CA LT_PED LT_TO LT_SFP_11 ISA S_CA S_PED TX TX TX POLOS0SFP011 U U U U _D LO LO POTX0DISABLE0PEDESTAL POTX0DISABLE0TOBEDELAYED POTX0DISABLE0SFP011 _FA _FA _FA _FA TX POLOS0CALIB POLOS0PEDESTAL TX TX TX TX POTX0DISABLE0CALIB POTX0FAULT0CALIB POTX0FAULT0PEDESTAL POTX0FAULT0TOBEDELAYED POTX0FAULT0SFP011 EF2_9 EF2_10 D D NLDEF209 NLDEF2010 EF2_8 EF2_11 D D NLDEF208 NLDEF2011 R2 Res3 10K R7 Res3 10K R12 Res3 10K R17 Res3 10K COR2 COR7 COR12 COR17 3V 3V 3V 3V EF1_9 EF1_10 PIR202 PIR201 PIR702 PIR701 PIR1202 PIR1201 PIR1702 PIR1701 1 1 3. 3. 3. 3. D D + + + + NLDEF109 NLDEF1010 EF1_8 EF1_11 D D NLDEF108 NLDEF1011 R3 Res3 10K R8 Res3 10K R13 Res3 10K R18 Res3 10K COR3 COR8 COR13 COR18 3V 3V 3V 3V EF0_8 EF0_9 EF0_10 EF0_11 PIR302 PIR301 PIR802 PIR801 PIR1302 PIR1301 PIR1802 PIR1801 3. 3. 3. 3. D D D D + + + + NLDEF008 NLDEF009 NLDEF0010 NLDEF0011 R4 Res3 10K R9 Res3 10K R14 Res3 10K R19 Res3 10K COR4 COR9 COR14 COR19 3V 3V 3V 3V PIR402 PIR401 PIR902 PIR901 PIR1402 PIR1401 PIR1902 PIR1901 3. 3. 3. 3. + + + + B C A D

Figure A.21: TIB: Optical transceivers to/from calibration box 232 A. Schematics B C A D 1 R_N R_N edor W W on 1 2 1 2 1 2 si COP62 COP72 COP76 P62 Header 2 P72 Header 2 P76 Header 2 s A. Tej Revi Lui PIP6201 PIP6202 PIP7201 PIP7202 PIP7601 PIP7602 EXTRA_2_N EXTRA_1_N EXTRA_3_P EXTRA_3_N EXTRA_10_N EXTRA_9_N EXTRA_11_P EXTRA_11_N EXTRA_18_N EXTRA_17_N EXTRA_19_P EXTRA_19_N 5V + TRGTYPE1_M TRGTYPE0_M POEXTRA020N POEXTRA010N POEXTRA030P POEXTRA030N POEXTRA0100N POEXTRA090N POEXTRA0110P POEXTRA0110N POEXTRA0180N POEXTRA0170N POEXTRA0190P POEXTRA0190N of 4 4 POTRGTYPE10MWR0N POTRGTYPE00MWR0N NLEXTRA030P NLEXTRA030N NLEXTRA0110P NLEXTRA0110N NLEXTRA0190P NLEXTRA0190N GND EXTRA_3_P EXTRA_3_N EXTRA_11_P EXTRA_11_N EXTRA_19_P EXTRA_19_N R_N R_N Sheet Drawn By: W W gger NLEXTRA020N NLEXTRA010N NLEXTRA0100N NLEXTRA090N NLEXTRA0180N NLEXTRA0170N EXTRA_2_N EXTRA_1_N EXTRA_3_P EXTRA_3_N EXTRA_10_N EXTRA_9_N EXTRA_11_P EXTRA_11_N EXTRA_18_N EXTRA_17_N EXTRA_19_P EXTRA_19_N 1 2 COP56 P56 Header 2 1 2 1 2 1 2 ereo Tri NLTRGTYPE00MWR0N COP61 COP71 COP75 TRGTYPE1_M TRGTYPE0_M P61 Header 2 P71 Header 2 P75 Header 2 St PIP5601 PIP5602 R_P R_N RJ 45s RJ45s.SchDoc PIP6101 PIP6102 PIP7101 PIP7102 PIP7501 PIP7502 W W ..\ 5D 6D 7D 8D 5F 6F 7F 8F 5H 6H 7H 8H ve\ t PIJ8005D PIJ8006D PIJ8007D PIJ8008D PIJ8005F PIJ8006F PIJ8007F PIJ8008F PIJ8005H PIJ8006H PIJ8007H PIJ8008H 5B 6B 7B 8B PIJ8005B PIJ8006B PIJ8007B PIJ8008B 5F 6F 7F 8F e Dri 5D 6D 7D 8D 5H 6H 7H 8H NLEXTRA020P NLEXTRA0100P NLEXTRA0180P EXTRA_2_P EXTRA_2_N EXTRA_10_P EXTRA_10_N EXTRA_18_P EXTRA_18_N ber 2013 5B 6B 7B 8B e Rabbi t hi 12/ Googl NLTRGTYPE10MWR0P NLTRGTYPE10MWR0N TRGTYPE1_M TRGTYPE1_M \ Num W 30/ C: 1D 2D 3D 4D 1F 2F 3F 4F 1H 2H 3H 4H RJ45-3 RJ45-5 RJ45-7 COJ80D COJ80F COJ80H J80D TE 5569262-1 J80F TE 5569262-1 J80H TE 5569262-1 1B 2B 3B 4B COJ80B J80B TE 5569262-1 1 2 UTIN / 1F 2F 3F 4F 1D 2D 3D 4D 1H 2H 3H 4H COP55 P55 Header 2 e e: 1 2 1 2 1 2 l e: t ze l 1B 2B 3B 4B COP60 COP70 COP74 P60 Header 2 P70 Header 2 P74 Header 2 A4 PIJ8001D PIJ8002D PIJ8003D PIJ8004D PIJ8001F PIJ8002F PIJ8003F PIJ8004F PIJ8001H PIJ8002H PIJ8003H PIJ8004H To M Ti Si Dat Fi PIJ8001B PIJ8002B PIJ8003B PIJ8004B PIP5501 PIP5502 R_P R_N PIP6001 PIP6002 PIP7001 PIP7002 PIP7401 PIP7402 W W R_P R_P W W R_P R_N W W EXTRA_1_P EXTRA_1_N EXTRA_9_P EXTRA_9_N EXTRA_17_P EXTRA_17_N NLEXTRA000P NLEXTRA000N NLEXTRA010P NLEXTRA080P NLEXTRA080N NLEXTRA090P NLEXTRA0160P NLEXTRA0160N NLEXTRA0170P EXTRA_0_P EXTRA_0_N EXTRA_1_P EXTRA_2_P EXTRA_8_P EXTRA_8_N EXTRA_9_P EXTRA_10_P EXTRA_16_P EXTRA_16_N EXTRA_17_P EXTRA_18_P 3 3 NLTRGTYPE00MWR0P TRGTYPE0_M TRGTYPE0_M NLSTEREO0MWR0P NLSTEREO0MWR0N STEREO_M STEREO_M TRGTYPE0_M TRGTYPE1_M 1 2 1 2 1 2 1 2 COP54 COP59 COP69 COP73 P54 Header 2 P59 Header 2 P69 Header 2 P73 Header 2 R_P R_P W W R_P R_N PIP5401 PIP5402 PIP5901 PIP5902 PIP6901 PIP6902 PIP7301 PIP7302 W W R_P R_N EXTRA_0_P EXTRA_0_N EXTRA_1_P EXTRA_2_P EXTRA_8_P EXTRA_8_N EXTRA_9_P EXTRA_10_P EXTRA_16_P EXTRA_16_N EXTRA_17_P EXTRA_18_P W W POEXTRA000P POEXTRA000N POEXTRA010P POEXTRA020P POEXTRA080P POEXTRA080N POEXTRA090P POEXTRA0100P POEXTRA0160P POEXTRA0160N POEXTRA0170P POEXTRA0180P EXTRA_0_P EXTRA_0_N EXTRA_8_P EXTRA_8_N EXTRA_16_P EXTRA_16_N STEREO_M STEREO_M TRGTYPE0_M TRGTYPE1_M POSTEREO0MWR0P POSTEREO0MWR0N POTRGTYPE00MWR0P POTRGTYPE10MWR0P STEREO_M STEREO_M GND 1 2 P53 Header 2 COP53 PIP5301 PIP5302 per 2 J81 Jum COJ81 PIJ8102 2 1 2 1 2 P64 P68 Header 2 P80 Header 2 COP64 COP68 COP80 SPARE_1_N ARRAYTRIG_N CABLE_DETECT 1 TRGTYPE0_CB_N STEREO_CB_N TRGTYPE1_CB_P TRGTYPE1_CB_N TRGTYPE1_CB_P TRGTYPE1_CB_N EXTRA_6_N EXTRA_5_N EXTRA_7_P EXTRA_7_N EXTRA_14_N EXTRA_13_N EXTRA_15_P EXTRA_15_N NLTRGTYPE10CB0P NLTRGTYPE10CB0N POSPARE010N POARRAYTRIG0N POCABLE0DETECT PIP6801 PIP6802 PIP8001 PIP8002 POTRGTYPE00CB0N POSTEREO0CB0N POTRGTYPE10CB0P POTRGTYPE10CB0N POEXTRA060N POEXTRA050N POEXTRA070P POEXTRA070N POEXTRA0140N POEXTRA0130N POEXTRA0150P POEXTRA0150N 1 1 2 i Header 2 2 2 PIJ8101 1 2 P52 Header 2 EXTRA_7_P EXTRA_7_N EXTRA_15_P EXTRA_15_N COP52 NLEXTRA070P NLEXTRA070N NLEXTRA0150P NLEXTRA0150N PIP6401 PIP6402 C324 Cap Sem 100nF COC324 PIP5201 PIP5202 PIC32402 PIC32401 i GND SPARE_1_N ARRAYTRIG_N NLSPARE010N NLARRAYTRIG0N EXTRA_6_N EXTRA_5_N EXTRA_7_P EXTRA_7_N EXTRA_14_N EXTRA_13_N EXTRA_15_P EXTRA_15_N NLEXTRA060N NLEXTRA050N NLEXTRA0140N NLEXTRA0130N TRGTYPE0_CB_N STEREO_CB_N TRGTYPE1_CB_P TRGTYPE1_CB_N CABLE_DETECT GND_OUT NLSTEREO0CB0N 1 2 1 2 CABLE_DETECT GND_OUT P67 Header 2 P79 Header 2 NLCABLE0DETECT NLGND0OUT COP67 COP79 C323 Cap Sem 100uF COC323 PIC32302 PIC32301 GND TRGTYPE0_CB_P TRGTYPE0_CB_N NLTRGTYPE00CB0P NLTRGTYPE00CB0N 5C 6C 7C 8C PIP6701 PIP6702 PIP7901 PIP7902 or i PIJ8005C PIJ8006C PIJ8007C PIJ8008C 5A 6A 7A 8A 5E 6E 7E 8E 5G 6G 7G 8G PIJ8005A PIJ8006A PIJ8007A PIJ8008A PIJ8005E PIJ8006E PIJ8007E PIJ8008E PIJ8005G PIJ8006G PIJ8007G PIJ8008G 1 2 COL30 L30 Induct 1uH 5C 6C 7C 8C Header 2 ane PIL3001 PIL3002

5E 6E 7E 8E

5A 6A 7A 8A 5G 6G 7G 8G GND EXTRA_6_P EXTRA_6_N EXTRA_14_P EXTRA_14_N COC322 NLEXTRA060P NLEXTRA0140P C322 Cap Sem 10uF

0

P63 0 COP63 PIP6301 PIP6302 PIJ8000 PIC32202 PIC32201 Backpl GND 1C 2C 3C 4C ral i J80C TE 5569262-1 COJ80C 1A 2A 3A 4A 1E 2E 3E 4E 1G 2G 3G 4G RJ45-4 RJ45-6 J80A TE 5569262-1 J80E TE 5569262-1 J80G TE 5569262-1 COJ80A COJ80E COJ80G Cent 1C 2C 3C 4C SPARE_1_P SPARE_1_N NLSPARE010P PIC32502 1E 2E 3E 4E 1A 2A 3A 4A 1G 2G 3G 4G COC325 C325 Cap Sem 100pF PIJ8001C PIJ8002C PIJ8003C PIJ8004C PIJ8001A PIJ8002A PIJ8003A PIJ8004A PIC32501 PIJ8001E PIJ8002E PIJ8003E PIJ8004E PIJ8001G PIJ8002G PIJ8003G PIJ8004G 1 2 P51 Header 2 COP51 1 2 1 2 1 2 P58 Header 2 P66 Header 2 P78 Header 2 HZ_P HZ_N COP58 COP66 COP78 PIP5101 PIP5102 GND PIP5801 PIP5802 PIP6601 PIP6602 PIP7801 PIP7802 CLK_10M CLK_10M ARRAYTRIG_P SPARE_1_P NLCLK010MHZ0P NLCLK010MHZ0N NLARRAYTRIG0P EXTRA_4_P EXTRA_4_N EXTRA_5_P EXTRA_6_P EXTRA_12_P EXTRA_12_N EXTRA_13_P EXTRA_14_P NLEXTRA040P NLEXTRA040N NLEXTRA050P NLEXTRA0120P NLEXTRA0120N NLEXTRA0130P EXTRA_5_P EXTRA_5_N EXTRA_13_P EXTRA_13_N 1 1 INPUT_0_P INPUT_0_N STEREO_CB_P TRGTYPE0_CB_P STEREO_CB_P STEREO_CB_N ARRAYTRIG_P ARRAYTRIG_N NLINPUT000P NLINPUT000N NLSTEREO0CB0P t HZ_P HZ_N e Rabbi t 1 2 1 2 hi P50 Header 2 SPARE_1_P P57 Header 2 COP50 COP57 1 2 1 2 W CLK_10M CLK_10M ARRAYTRIG_P P65 Header 2 P77 Header 2 POSPARE010P COP65 COP77 al EXTRA_4_P EXTRA_4_N EXTRA_5_P EXTRA_6_P EXTRA_12_P EXTRA_12_N EXTRA_13_P EXTRA_14_P POCLK010MHZ0P POCLK010MHZ0N POARRAYTRIG0P PIP5001 PIP5002 PIP5701 PIP5702 HZ_P HZ_N POEXTRA040P POEXTRA040N POEXTRA050P POEXTRA060P POEXTRA0120P POEXTRA0120N POEXTRA0130P POEXTRA0140P duci PIP6501 PIP6502 PIP7701 PIP7702 UTIN / COFD4 INPUT_0_P INPUT_0_N STEREO_CB_P FD4 Fi M TRGTYPE0_CB_P POINPUT000P POINPUT000N POSTEREO0CB0P POTRGTYPE00CB0P INPUT_0_P INPUT_0_N From CLK_10M CLK_10M EXTRA_4_P EXTRA_4_N EXTRA_12_P EXTRA_12_N B C A D

Figure A.22: TIB: RJ45 connectors A. Schematics 233 B C A D i COJ24 COJ25 COJ26 J24 Socket J25 Socket J26 Socket COC29 C29 Cap Sem 100nF 1 PIJ2401 PIJ2501 PIJ2601 PIC2902 PIC2901 edor i on si s A. Tej COC28 COJ20 COJ23 C28 Cap Sem 100pF J20 Socket J23 Socket Revi Lui PIC2802 PIC2801 GND PIJ2001 PIJ2301 ISO_EXT_DEL OSI_EXT_DEL i M CLK_EXT_DEL M NLMISO0EXT0DEL NLCLK0EXT0DEL NLMOSI0EXT0DEL of 4 4 3.3V i + Sheet Drawn By: GND GND COC27 C27 Cap Sem 10uF 3.3V 3.3V + + PIC2702 PIC2701 ay COC38 C38 Cap Sem 100nF gger i PIC3802 PIC3801 Del 3.3V 3.3V ay.SchDoc i + + i Del ernal 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 ereo Tri COC26 C26 Cap Sem 100nF PIU409 PIU4010 PIU4011 PIU4012 PIU4013 PIU4014 PIU4015 PIU4016 PIU709 PIU7010 PIU7011 PIU7012 PIU7013 PIU7014 PIU7015 PIU7016 St Ext ernal COC37 C37 Cap Sem 100pF S S S S PIC2602 PIC2601 M M P5 P6 P7 P5 P6 P7 i M M Ext COC47 C47 Cap Sem 100nF Vcc Vcc PIC3702 PIC3701 P*/ P*/ ..\ PW PW GND OUT* OUT* PIC4702 PIC4701 ve\ i i REF/ REF/ COC25 C25 Cap Sem 100pF OUT/ OUT/ 3.3V e Dri + PIC2502 PIC2501 ber 2013 GND COC36 COC46 C36 Cap Sem 10uF C46 Cap Sem 100pF i 12/ Googl Q CLK D Q CLK D \ PIC3602 PIC3601 PIC4602 PIC4601 Num GND 30/ C: IN LE P0/ P1/ P2/ P3 P4 GND IN LE P0/ P1/ P2/ P3 P4 GND 3.3V i COU4 COU7 U4 DS1123L U7 DS1123L + COC24 C24 Cap Sem 10uF 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 3.3V + e e: PIC2402 PIC2401 l e: t ze l A4 COC45 C45 Cap Sem 10uF PIU401 PIU402 PIU403 PIU404 PIU405 PIU406 PIU407 PIU408 PIU701 PIU702 PIU703 PIU704 PIU705 PIU706 PIU707 PIU708 Ti Si Dat Fi NLLE4 NLLE7 GND GND LE4 LE7 PIC4502 PIC4501 i COC23 C23 Cap Sem 100nF PIC2302 PIC2301 3 3 i COJ27 J27 Socket LE_EXT_DEL_4 LE_EXT_DEL_7 TRIGDELAYED_2 J19 Socket J22 Socket COJ19 COJ22 ISO_EXT_DEL OSI_EXT_DEL ISO_EXT_DEL OSI_EXT_DEL POLE0EXT0DEL04 NLDELAY0CHAIN05 POLE0EXT0DEL07 POTRIGDELAYED02 M CLK_EXT_DEL M DELAY_CHAIN_5 M CLK_EXT_DEL M PIJ2701 i NLDELAY0CHAIN02 DELAY_CHAIN_2 C22 Cap Sem 100pF COC22 PIJ1901 PIJ2201 PIC2202 PIC2201 i GND GND GND GND i C44 Cap Sem 100nF COC44 3.3V 3.3V 3.3V + + + PIC4402 PIC4401 3.3V i C35 Cap Sem 100nF COC35 + NLTRIGDELAYED02 TRIGDELAYED_2 C21 Cap Sem 10uF COC21 PIC3502 PIC3501 3.3V 3.3V 3.3V i + + + PIC2102 PIC2101 C43 Cap Sem 100pF COC43 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 PIU309 PIU3010 PIU3011 PIU3012 PIU3013 PIU3014 PIU3015 PIU3016 PIU609 PIU6010 PIU6011 PIU6012 PIU6013 PIU6014 PIU6015 PIU6016 PIC4302 PIC4301 PIU909 PIU9010 PIU9011 PIU9012 PIU9013 PIU9014 PIU9015 PIU9016 GND C34 Cap Sem 100pF COC34 S S S S S S M M M P5 P6 P7 P5 P6 P7 P5 P6 P7 i M M M Vcc Vcc Vcc PIC3402 PIC3401 P*/ P*/ P*/ PW PW PW GND OUT* OUT* OUT* 3.3V i + REF/ REF/ REF/ GND C42 Cap Sem 10uF OUT/ OUT/ OUT/ COC42 3.3V 3.3V + + PIC4202 PIC4201 C33 Cap Sem 10uF COC33 REF_EXT_DEL TRIGDELAYED J17 COJ17 Q CLK D Q CLK D Q CLK D PIC3302 PIC3301 POREF0EXT0DEL POTRIGDELAYED Socket IN LE P0/ P1/ P2/ P3 P4 GND IN LE P0/ P1/ P2/ P3 P4 GND IN LE P0/ P1/ P2/ P3 P4 GND U3 DS1123L U6 DS1123L U9 DS1123L COU3 COU6 COU9 J14 COJ14 PIJ1701 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Socket PIU301 PIU302 PIU303 PIU304 PIU305 PIU306 PIU307 PIU308 PIU601 PIU602 PIU603 PIU604 PIU605 PIU606 PIU607 PIU608 PIU901 PIU902 PIU903 PIU904 PIU905 PIU906 PIU907 PIU908 GND GND GND LE3 LE6 LE9 NLLE3 NLLE6 NLLE9 PIJ1401 REF_EXT_DEL TRIGDELAYED NLREF0EXT0DEL NLTRIGDELAYED 2 2 3.3V + 9 10 11 12 13 14 15 16 PIU109 PIU1010 PIU1011 PIU1012 PIU1013 PIU1014 PIU1015 PIU1016 S S M P5 P6 P7 M Vcc P*/ PW LE_EXT_DEL_3 LE_EXT_DEL_6 LE_EXT_DEL_9 OUT* J18 Socket J21 Socket J28 Socket COJ18 COJ21 COJ28 ISO_EXT_DEL OSI_EXT_DEL ISO_EXT_DEL OSI_EXT_DEL ISO_EXT_DEL OSI_EXT_DEL M CLK_EXT_DEL M DELAY_CHAIN_4 M CLK_EXT_DEL M DELAY_CHAIN_7 M CLK_EXT_DEL M POLE0EXT0DEL03 NLDELAY0CHAIN04 POLE0EXT0DEL06 NLDELAY0CHAIN07 POLE0EXT0DEL09 REF/ DELAY_CHAIN_1 NLDELAY0CHAIN01 OUT/ PIJ1801 PIJ2101 PIJ2801 i i GND GND GND Q CLK D 3.3V 3.3V 3.3V + + + COC32 C32 Cap Sem 100nF IN LE P0/ P1/ P2/ P3 P4 GND U1 DS1123L COU1 COC41 C41 Cap Sem 100nF PIC3202 PIC3201 i 1 2 3 4 5 6 7 8 PIC4102 PIC4101 3.3V 3.3V 3.3V i + + + 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 9 10 11 12 13 14 15 16 PIU101 PIU102 PIU103 PIU104 PIU105 PIU106 PIU107 PIU108 GND COC31 C31 Cap Sem 100pF PIU209 PIU2010 PIU2011 PIU2012 PIU2013 PIU2014 PIU2015 PIU2016 PIU509 PIU5010 PIU5011 PIU5012 PIU5013 PIU5014 PIU5015 PIU5016 PIU809 PIU8010 PIU8011 PIU8012 PIU8013 PIU8014 PIU8015 PIU8016 COC40 C40 Cap Sem 100pF S S S S S S PIC3102 PIC3101 M M M P5 P6 P7 P5 P6 P7 P5 P6 P7 GND M M M Vcc Vcc Vcc PIC4002 PIC4001 P*/ P*/ P*/ i PW PW PW GND OUT* OUT* OUT* i 3.3V REF/ REF/ REF/ OUT/ OUT/ OUT/ + 3.3V COC30 C30 Cap Sem 10uF + PIJ1501 Socket C39 Cap Sem 10uF COC39 PIC3002 PIC3001 J15 Q CLK D Q CLK D Q CLK D COJ15 PIC3902 PIC3901 IN LE P0/ P1/ P2/ P3 P4 GND IN LE P0/ P1/ P2/ P3 P4 GND IN LE P0/ P1/ P2/ P3 P4 GND U2 DS1123L U5 DS1123L U8 DS1123L COU2 COU5 COU8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 1 ISO_EXT_DEL OSI_EXT_DEL TOBEDELAYED LE_EXT_DEL M CLK_EXT_DEL M NLTOBEDELAYED NLLE0EXT0DEL PIU201 PIU202 PIU203 PIU204 PIU205 PIU206 PIU207 PIU208 PIU501 PIU502 PIU503 PIU504 PIU505 PIU506 PIU507 PIU508 PIU801 PIU802 PIU803 PIU804 PIU805 PIU806 PIU807 PIU808 GND GND GND LE5 DELAY_CHAIN_6 LE8 NLLE5 NLDELAY0CHAIN06 NLLE8 TBD2 LE2 DELAY_CHAIN_3 NLTBD2 NLLE2 NLDELAY0CHAIN03 PIJ1601 J16 Socket COJ16 ISO_EXT_DEL OSI_EXT_DEL TOBEDELAYED LE_EXT_DEL M CLK_EXT_DEL M CLK_EXT_DEL LE_EXT_DEL_5 LE_EXT_DEL_8 ISO_EXT_DEL OSI_EXT_DEL ISO_EXT_DEL OSI_EXT_DEL ISO_EXT_DEL OSI_EXT_DEL TOBEDELAYED_2 LE_EXT_DEL_2 M M M CLK_EXT_DEL M M CLK_EXT_DEL M POTOBEDELAYED POLE0EXT0DEL POMISO0EXT0DEL POCLK0EXT0DEL POMOSI0EXT0DEL POLE0EXT0DEL05 POLE0EXT0DEL08 POTOBEDELAYED02 POLE0EXT0DEL02 B C A D

Figure A.23: TIB: External delays 234 A. Schematics B C A D 1 edor on si s A. Tej Revi Lui of 4 4 Sheet Drawn By: er er.SchDoc et et gger om om ereo Tri Therm Therm St ..\ ve\ e Dri ber 2013 12/ Googl \ Num 30/ C: e e: l e: t ze l A4 Ti Si Dat Fi 3 3 GND 2 PIU4102 VSS CTTR O SCK SI/ CS VDD COU41 U41 TC77-3.3M i 4 3 1 5 PIU4104 PIU4103 PIU4101 PIU4105 C309 Cap Sem 100nF COC309 PIC30902 PIC30901 i GND C308 Cap Sem 100pF COC308 IO_TH CLK_TH CS_TH NLIO0TH NLCLK0TH NLCS0TH 2 2 PIJ8201 PIJ8301 PIJ8401 PIC30802 PIC30801 GND J82 Socket J83 Socket J84 Socket COJ82 COJ83 COJ84 i C307 Cap Sem 10uF COC307 PIC30702 PIC30701 GND IO_TH CLK_TH CS_TH POIO0TH POCLK0TH POCS0TH 3.3V + 1 1 B C A D

Figure A.24: TIB: Thermometer A. Schematics 235 B C A D i i i 1 i COC283 COC290 COC293 C283 Cap Sem 1uF C290 Cap Sem 1uF C293 Cap Sem 10uF edor PIC28301 PIC28302 PIC29001 PIC29002 PIC29301 PIC29302 1V 2.5V 1.8V + GND GND + + COC294 C294 Cap Sem 10nF on s A. Tej si PIC29402 PIC29401 Lui Revi NL10BYP 1_BYP 1 1 NOPB PIU3501 PIU3701 5 6 1 3 of 4 4 NOPB NOPB PIU3805 PIU3806 PIU3801 PIU3803

Sheet Drawn By: OUT OUT

GND 4 PIU3504 4 PIU3704 ADJ BYP OUT GND GND GND GND GND IN IN COU35 COU37 U35 LP38690DT-2.5/ U37 IN SD NC NC DAP y.SchDoc COU38 LP38691DT-1.8/ U38 LP3878SD-ADJ/ 3 3 y i PIU3503 PIU3703 4 8 2 7 9 PIU3804 PIU3808 PIU3802 PIU3807 PIU3809 NL1080IN 1_8_IN PowerSuppl COC289 C289 Cap Sem 1uF ..\ i Power Suppl PIC28901 PIC28902 ve\ GND i NL2050IN NL10IN 2_5_IN 1_IN PIF202 e Dri COC292 C292 Cap Sem 4.7uF gger ber 2013 PIC29202 PIC29201 12/ Googl COC282 COF2 C282 Cap Sem 1uF F2 0.5A \ Num 30/ C: PIC28201 PIC28202 PIF302 ereo Tri GND PIF201 St PIF102 3.3V COF3 F3 1.5A + e e: l e: t ze l A4 Ti Si Dat Fi COF1 F1 1.5A PIF301 3.3V + PIF101 3.3V + 3 3.3V + COC288 C288 Cap Pol 180uF 3 3 PIC28801 PIC28802 GND PIL2502 or 1 2 COL25 COJ60 L25 Induct 8.2uH J60 IPL1-102-01-L-S-RA-K 1 2 PIL2501

PIJ6001 PIJ6002

Q1 CSD18534Q5A Q2 CSD18534Q5A

COQ1 COQ2

1 5 1 PIQ105 5 PIQ101 PIQ205 PIQ201 GND PIF402 F4 2.5A COF4 3 3 4 4 PIF401 i C299 Cap Pol 180uF PIQ104 PIQ204 COC299 C300 Cap Pol 220uF COC300 5V PIC29901 PIC29902 + GND PIC28402 PIC30001 PIC30002 i C284 Cap Sem 470nF COC284 PIL2602 3_3_SW NL3030SW PIC28401 or 3_3_LG NL3030LG C303 Cap Sem 100pF COC303 L26 Induct 22uH COL26 2 2 PIC30301 PIC30302 i 3_3_HG 3_3_BST NL3030HG NL3030BST PIL2601 GND i GND C302 Cap Sem 100nF COC302 11 12 10 13 15 5 9 14 PIU36011 PIU36012 PIU36010 PIU36013 PIU36015 PIU3605 PIU3609 PIU36014 PIC30201 PIC30202 NOPB i D1 BAS240A-13-F COD1 C297 Cap Sem 10nF COC297 LG HG SW PIC29701 PIC29702 PID101 PID102 BST DAP GND H-3.3/ SGND SGND PGND C301 Cap Sem 10uF COC301 GND PIC30101 PIC30102 24V 3151M 5_BOOT 5_SW + NL50BOOT NL50SW EN VIN SS FB NC NC VCC i U36 LM COU36 GND 4 1 8 9 6 3 2 6 4 7 8 1 PIU3603 PIU3602 PIU3606 PIU3604 PIU3607 PIU3608 PIU3601 PIU3904 PIU3901 PIU3908 PIU3909 PIU3906 COC291 C291 Cap Sem 2.2uF NOPB FB 3_3_VCC SW NL3030VCC PIC29102 PIC29101 DAP GND GND BOOT R-5.0/ i SYNC 22672M VIN EN RT/ SS 3_3_SS U39 LM NL3030SS COC287 COU39 C287 Cap Sem 15nF 7 5 3 2 PIC28702 PIC28701 i GND PIU3907 PIU3905 PIU3903 PIU3902 i i 5_RT C298 Cap Sem 39nF NL50RT COC298 5_SS C286 Cap Sem 100nF COC286 NL50SS PIC29802 PIC29801 1 1 GND C296 Cap Sem 1uF COC296 PIC28602 PIC28601 GND PIC29602 PIC29601 i i R79 Res3 61.9K COR79 PIR7902 PIR7901 GND C285 Cap Sem 4.7uF COC285 C295 Cap Sem 4.7uF COC295 PIC28502 PIC28501 GND PIC29502 PIC29501 24V GND + 24V + B C A D

Figure A.25: TIB: Power supplies 236 A. Schematics B C A D 1 edor on s A. Tej si Lui Revi of 4 4 Sheet Drawn By: 0 0 0 0 0 0 0 3 grounded 3 grounded 3 grounded 3 grounded 3 grounded 3 grounded 3 grounded COS1 COS2 COS3 COS4 COS5 COS6 COS7 S1 M S2 M S3 M S4 M S5 M S6 M S7 M PIS100 PIS200 PIS300 PIS400 PIS500 PIS600 PIS700 0 0 0 0 0 0 0 LEDs LEDs.SchDoc GND GND GND GND GND GND GND ..\ ve\ e Dri gger ber 2013 12/ Googl \ Num 30/ C: ereo Tri St e e: l e: t ze l A4 Ti Si Dat Fi 3 3 COD6 D6 LED2 COR86 R86 Res3 100 PID602 PID601 PIR8602 PIR8601 1V + GND al duci COFD6 FD6 Fi COD5 D5 LED2 COR85 R85 Res3 249 PID502 PID501 PIR8502 PIR8501 2.5V GND + COD4 D4 LED2 COR84 R84 Res3 330 PID402 PID401 PIR8402 PIR8401 3.3V GND + 2 2 D3 LED2 COD3 R83 Res3 500 COR83 5V eON LTST-C171GKT. PID302 PID301 PIR8302 PIR8301 t + GND he board. for Li A current he corners of t s for t D2 LED2 COD2 al der 10 m R82 Res3 2.4K COR82 PID202 PID201 PIR8202 PIR8201 24V duci GND + Consi Fi 1 1 al duci FD5 Fi COFD5 B C A D

Figure A.26: TIB: Power monitor LEDs, mechanical holes and grounding Appendix B

Bill of materials

B.1 Bill of materials of Level 1

The following table shows the cost of the different devices which are part of the Level 1 trigger subsystem:

Cost/unit(AC) Total cost(AC) Functionality Reference Manufacturer Quantity min max min max Differential AD8003 Analog Devices 2.92 3.44 2 5.84 6.88 to Resistors Various 0.01 0.02 36 0.36 0.72 single-ended Capacitors Various 0.02 0.05 12 0.24 0.60 Inductors Tyco Electronics 0.10 0.15 6 0.60 0.90 Splitter 3 Resistors Various 0.01 0.02 8 0.08 0.16 Capacitors Various 0.02 0.05 10 0.20 0.50 Inductors Tyco Electronics 0.10 0.15 4 0.20 0.40 Splitter 2 Resistors Various 0.01 0.02 4 0.04 0.08 Capacitors Various 0.02 0.05 6 0.12 0.30 Attenuator Resistors Various 0.01 0.02 4 0.04 0.08 Switching ADG901 Analog Devices 0.98 1.02 8 7.84 8.16 Network Capacitors Various 0.02 0.05 16 0.32 0.80 Matching and Resistors Various 0.01 0.02 19 0.19 0.38 decoupling Capacitors Various 0.02 0.05 22 0.44 1.10 Slow Control 74HC00 NXP 0.10 0.15 1 0.10 0.15 Logic SN74LVC1G32 Texas Inst. 0.12 0.14 1 0.12 0.14 Capacitors Various 0.02 0.15 6 0.12 0.30 AD8003 Analog Devices 2.92 3.44 1 2.92 3.44 Adder Resistors Various 0.01 0.02 27 0.27 0.54 Capacitors Various 0.02 0.05 6 0.12 0.30 Comparator ADCMP604 Analog Devices 2.18 2.78 3 6.54 8.34 Capacitors Various 0.02 0.05 9 0.18 0.45 Comparator ADCMP604 Analog Devices 2.18 2.78 3 6.54 8.34 Colibri Capacitors Various 0.02 0.05 9 0.18 0.45 238 B. Bill of materials

HSMS2855 Avago Tech. 0.67 0.72 3 2.01 2.16 LVDS ADCMP604 Analog Devices 2.18 2.78 1 2.18 2.78 OR gate Resistors Various 0.01 0.02 6 0.06 0.12 Capacitors Various 0.02 0.05 3 0.06 0.15 LVDS HSMS2855 Avago Tech. 0.67 0.72 3 2.01 2.16 OR gate ADCMP604 Analog Devices 2.18 2.78 1 2.18 2.78 Colibri Resistors Various 0.01 0.02 6 0.06 0.12 Capacitors Various 0.02 0.05 3 0.06 0.15 LVDS HSMS2855 Avago Tech. 0.67 0.72 2 1.34 1.44 AND gate ADCMP604 Analog Devices 2.18 2.78 1 2.18 2.78 Delay Resistors Various 0.01 0.02 4 0.04 0.08 Calibration Capacitors Various 0.02 0.05 3 0.06 0.15 Width to HSMS2855 Avago Tech. 0.67 0.72 1 0.67 0.72 Amplitude OPA2830 Texas Inst. 0.76 1.00 1 0.76 1.00 Delay Resistors Various 0.01 0.02 6 0.06 0.12 Calibration Capacitors Various 0.02 0.05 6 0.12 0.30 Read ADCMP600 Analog Devices 1.25 1.45 1 1.25 1.45 Pulse ADG801 Analog Devices 0.65 0.75 1 0.65 0.75 Amplitude AD7478A Analog Devices 0.65 0.75 1 0.65 0.75 Delay Resistors Various 0.01 0.02 3 0.03 0.06 Calibration Capacitors Various 0.02 0.05 14 0.28 0.70 Output switch ADG936 Analog Devices 1.10 1.20 1 1.10 1.20 Delay Calib. Capacitors Various 0.02 0.05 3 0.06 0.15 Power Supply AP2141 Diodes Zetex 0.30 0.35 1 0.30 0.35 Delay Resistors Various 0.01 0.02 1 0.01 0.02 Calibration Capacitors Various 0.02 0.05 7 0.14 0.35 DAC AD5663R Analog Devices 3.10 3.50 1 3.10 3.50 Capacitors Various 0.02 0.05 12 0.24 0.60 Total Components 319 55.26 70.40 Table B.1: Level 1 bill of materials per cluster: Component costs in AC

Table B.1 comprise the costs of the components, which correspond to the final cost of the Level 1 once it will be integrated in the front-end boards. However, the cost of the mezzanines used for the first prototypes was somewhat more expensive. Table B.2 gathers the additional costs of each new manufactured mezzanine, while table B.3 shows the fixed costs of a PCB production, to be shared among all the manufactured boards. B. Bill of materials 239

Concept Unit price(AC) Total cost(AC) Manufacturer Quantity min max min max Connector Samtec 5.00 6.65 1 5.00 6.65 QMSS-016-06.75-L-D-DP-A Connector Samtec 7.00 7.99 1 7.00 7.99 QMSS-016-06.75-L-D-DP-PC4 Capacitors for Various 0.02 0.05 6 0.12 0.30 power filtering FR4 multilayer Lab Circuits 3.32 8.56 1 3.32 8.56 PCB manufacturing Board SETI 19.94 30.40 1 19.94 30.40 assembly Electr´onica Additional mezzanine cost (AC) 35.38 53.90

Table B.2: Level 1 bill of materials per cluster: Mezzanine manufacturing costs in AC

Unit price(AC) Total cost(AC) Concept Manufacturer Quantity min max min max PCB manufacturing Lab Circuits 597.00 1056.00 1 597.00 1056.00 fixed costs Silk Screen SETI Electr´onica 150.00 150.00 2 300.00 300.00 SMD Pick & Place program SETI Electr´onica 120.00 120.00 1 120.00 120.00 Board batch production fixed cost (AC) 1017.00 1476.00

Table B.3: Level 1 mezzanine production fixed costs in AC 240 B. Bill of materials

B.2 Bill of materials of the trigger interface board

Table B.4 contains all the costs required to manufacture one trigger interface board module. Unlike in the case of Level 1, the TIB is an independent module, so the costs of manufacturing the PCB and assembling the components must be always taken into account. Additionally, there will be also some fixed costs gathered in table B.5 to be shared between all the manufactured boards 1. The total number of TIBs will quite smaller, so from the manufacturer point of view all of the boards will be considered as prototypes, which means more expensive prices.

Unit price (AC) Cost (AC) Component Value Quantity min max min max LP38690DT-2.5 0.79 0.91 1 0.79 0.91 LM22672MR-5.0 2.00 2.72 1 2.00 2.72 CDCV304PWRG4 1.63 2.08 1 1.63 2.08 DS1123L-200 11.51 11.51 9 103.59 103.59 SFP box x4 24.93 27.61 3 74.79 82.83 LP38691DT-1.8 0.62 0.826 1 0.82 0.83 CSD18534Q5A 0.76 1.89 2 1.52 3.78 Artix-7 FPGA 203.50 203.50 1 203.50 203.50 B240A-13-F 0.057 0.079 1 0.06 0.08 JTAG connector 0.836 1.41 1 0.84 1.41 Jumper 2 vias 0.062 0.072 1 0.062 0.072 SN65LVDS101 2.68 4.19 12 32.16 50.28 LP3878SD-ADJ 0.92 1.87 1 0.92 1.87 SN65LVDS100 2.60 4.19 12 31.20 50.28 Raspberry Pi 3.03 10.13 1 3.03 10.13 connector RJ45 connector 15.79 17.74 1 15.79 17.74 Power connector 0.68 1.23 1 0.68 1.23 LM3151MHE-3.3 3.16 3.84 1 3.16 3.84 TC77 0.61 0.67 1 0.61 0.67 Green LED SMD 0.038 0.053 5 0.19 0.27 Fuse 0.5 A 0.775 1.141 1 0.78 1.14 Capacitor 0603 10V 1 µF 0.003 0.009 4 0.01 0.04 Capacitor 0603 50V 1 µF 0.032 0.1 1 0.03 0.1 Inductor 0805 1 µH 0.055 0.092 24 1.32 2.21 Inductor 0603 1 µH 0.044 0.11 4 0.18 0.44 Fuse 1.5 A 0.674 1.063 2 1.35 2.13 Capacitor 0805 2.2 µF 0.077 0.168 1 0.08 0.17 Resistor 0603 2.4 kΩ 0.009 0.016 1 0.01 0.02 Fuse 2.5 A 0.594 0.874 1 0.59 0.87 Resistor 0603 4.7 kΩ 0.004 0.008 3 0.01 0.02 Capacitor 0805 4.7 µF 0.183 0.51 2 0.37 1.02

1Considering LSTs and MSTs, in North and South observatories, around 50 operating TIBs are expected. Some more TIBs must be produced as spares B. Bill of materials 241

Capacitor 0603 4.7 µF 0.015 0.026 1 0.02 0.03 Capacitor 0402 4.7 µF 0.099 0.198 44 4.36 8.71 Inductor XAL1010 8.3 µH 2.55 2.78 1 2.55 2.78 Resistor 0603 10 kΩ 0.006 0.011 60 0.36 0.66 Capacitor 0603 10 nF 0.008 0.014 2 0.02 0.03 Capacitor 0805 10V 10 µF 0.011 0.02 64 0.70 1.28 Capacitor 0805 25V 10 µF 0.083 0.143 1 0.08 0.14 Capacitor 0805 15 nF 0.008 0.013 1 0.01 0.01 Inductor XAL5050 22 µH 0.86 0.95 1 0.86 0.95 Capacitor 0603 39 nF 0.005 0.009 1 0.01 0.01 Capacitor 1812 47 µF 0.77 1.71 3 2.31 5.13 Resistor 0603 61.9 kΩ 0.017 0.027 1 0.02 0.03 Resistor 0402 100 Ω 0.006 0.01 2 0.01 0.02 Resistor 0603 100 Ω 0.006 0.01 15 0.09 0.15 Capacitor 0603 25V 100 nF 0.007 0.012 75 0.53 0.90 Capacitor 0805 100 nF 0.011 0.024 1 0.01 0.02 Capacitor 0603 50V 100 nF 0.011 0.014 1 0.01 0.01 Capacitor 0603 100 pF 0.009 0.012 36 0.32 0.42 Capacitor 0402 100 pF 0.005 0.009 4 0.02 0.04 Capacitor 1206 100 µF 0.11 0.235 4 0.44 0.94 Capacitor 1210 100 µF 0.69 1.29 9 6.21 11.61 Al capacitor 180 µF 1.00 1.75 2 2.00 3.50 Al capacitor 220 µF 0.165 0.228 1 0.17 0.23 Resistor 0603 249 Ω 0.006 0.011 1 0.01 0.01 Resistor 0603 330 Ω 0.007 0.011 2 0.01 0.02 Ta Capacitor 330 µF 1.47 3.83 1 1.47 3.83 Capacitor 0603 470 nF 0.017 0.033 1 0.02 0.03 Capacitor 0402 470 nF 0.017 0.022 65 1.11 1.43 Resistor 0603 500 Ω 0.009 0.016 1 0.01 0.02 Screw M2.5 plane 12 mm 0.0177 0.0213 11 0.19 0.23 Nut M2.5 plane 2 mm 0.0136 0.0163 9 0.12 0.15 Spacer M2.5 5 mm 0.092 0.152 9 0.83 1.37 Washer M2.5 0.023 0.028 9 0.21 0.25 Spacer M2.5 12.7 mm 0.041 0.0803 2 0.08 0.16 Raspberry Pi 39.00 39.00 1 39.00 39.00 SFP transceiver 40.38 41.91 12 484.56 502.92 Avago AFBR5715ALZ SFP connector 4.03 4.24 12 48.36 50.88 Al Rack box 1U 220 mm 30.80 32.75 1 30.80 32.75 Closed cover plate 220 mm 10.16 11.54 1 10.16 11.54 Ventilated cover plate 220 mm 17.20 19.57 1 17.20 19.57 PCB 411.17 411.17 1 411.17 411.17 Component assembly 1 Total components 570 1548.24 1548.24 242 B. Bill of materials

Table B.4: Bill of materials of 1 Trigger Interface Board

Unit price(AC) Total cost(AC) Concept Manufacturer Quantity min max min max PCB manufacturing Lab Circuits 1468.00 1468.00 1 1468.00 1468.00 fixed costs Silk Screen SETI Electr´onica 2 SMD Pick & Place program SETI Electr´onica 1 Board batch production fixed cost (AC) 1468.00 1468.00

Table B.5: Fixed costs of the Trigger Interface Board

The costs of table B.4 correspond to the first TIB prototype. The costs of the final version which will be installed in the telescopes cameras will be slightly different. For instance, one of the most expensive components are the optical transceivers (c.a. 40 ACeach), of which there are 12 units in the prototype. In the real case, it is very unlikely to have more than 4 LSTs in each observatory, so there would be only 3 neighbours in the case of LSTs and 0 neighbours in the case of MSTs. Additionally, other optical link is an spare and other is reserved to check the performance of the optical delay of the signals. So in fact, only 5 from the 12 optical transceivers are strictly required for LSTs and 2 for MSTs, which involves saving up to 280 ACin the boards installed in LSTs and 400 ACin the ones placed in MST cameras. As was explained in section 7.4.2.2, all the TIBs will have the housing for the 12 transceivers mounted, but only the required transceivers will be installed. In the same way, another significant costs are the delay chips, which need to be tested before deciding to use them in the final version. Appendix C

Reliability

In a large project as CTA, it is very important to estimate the reliability of the different systems properly in order to foresee the number of spares required, the human resources which should be dedicated to reparations, and in sum the budget required for maintenance. With this aim, all the subsystems must provide to the system engineers with their reliability estimations. This appendix contains the reliability estimations for the Level 1 (table C.1) and the Trigger Interface Board (table C.2). For this estimations, the Middle Time Between Failures (MTBF) or the Failure In Time (FIT) information provided by the manufacturers of the different active components has been used. However, for the pasive components this information is sometimes difficult to find, and due to the high number of elements and the different manufactures which can produce equivalent components, getting the MTBF or the FIT from the manufacturers would be and endless task. For this reason, the reliability of the passive components have been estimated with the generic prediction models included in the FIDES guide[172], instead of with their specific data. A free software tool implementing these prediction models have been used [173], as shown in figure C.1.

Figure C.1: Free MTBF calculator, from ALD [173] 244 C. Reliability

Component Value Unit MTBF (hours) Quantity FIT (in 1 hour) Capacitor 0603 100 nF 1.82 · 1010 33 1.81 · 10−9 Capacitor 0805 10 µF 1.82 · 1010 31 1.70 · 10−9 Capacitor 0603 10 µF 1.82 · 1010 23 1.26 · 10−9 Capacitor 0603 100 pF 1.82 · 1010 32 1.76 · 10−9 Capacitor 0603 1 nF 1.82 · 1010 8 4.39 · 10−10 Capacitor 0603 4 pF 1.82 · 1010 2 1.10 · 10−10 Capacitor 0603 2 pF 1.82 · 1010 10 5.49 · 10−10 Capacitor 0603 5.6 pF 1.82 · 1010 2 1.10 · 10−10 Capacitor 0603 1 pF 1.82 · 1010 2 1.10 · 10−10 Capacitor 1206 Ta 68 µF 1.58 · 109 1 6.33 · 10−10 Capacitor 0603 10 nF 1.82 · 1010 2 1.10 · 10−10 Capacitor 0805 33 µF 1.82 · 1010 1 5.49 · 10−11 Capacitor 0603 120 pF 1.82 · 1010 2 1.10 · 10−10 Capacitor 0603 68 pF 1.82 · 1010 1 5.49 · 10−11 Capacitor 0603 47 pF 1.82 · 1010 1 5.49 · 10−11 Capacitor 1206 Ta 100 µF 1.58 · 109 1 6.33 · 10−10 Capacitor 1206 1 µF 1.82 · 1010 1 5.49 · 10−11 Inductor 0402 15 nH 4.34 · 109 4 9.22 · 10−10 Inductor 0402 20 nH 4.34 · 109 6 1.38 · 10−9 Resistor 0603 100 Ω 3.28 · 1010 10 3.05 · 10−10 Resistor 0603 200 Ω 3.28 · 1010 18 5.49 · 10−10 Resistor 0603 49.9 Ω 3.28 · 1010 23 7.01 · 10−10 Resistor 0603 62 Ω 3.28 · 1010 2 6.10 · 10−11 Resistor 0603 261 Ω 3.28 · 1010 4 1.22 · 10−10 Resistor 0603 56 Ω 3.28 · 1010 8 2.44 · 10−10 Resistor 0603 60.4 Ω 3.28 · 1010 4 1.22 · 10−10 Resistor 0603 360 Ω 3.28 · 1010 8 2.44 · 10−10 Resistor 0603 470 Ω 3.28 · 1010 8 2.44 · 10−10 Resistor 0603 330 Ω 3.28 · 1010 4 1.22 · 10−10 Resistor 0603 191 Ω 3.28 · 1010 2 6.10 · 10−11 Resistor 0603 620 Ω 3.28 · 1010 3 9.15 · 10−11 Resistor 0603 1 kΩ 3.28 · 1010 2 6.10 · 10−11 Resistor 0603 0 Ω 3.28 · 1010 1 3.05 · 10−11 Resistor 0603 100 kΩ 3.28 · 1010 1 3.05 · 10−11 Resistor 0603 10 kΩ 3.28 · 1010 4 1.22 · 10−10 Resistor 0603 1.8 kΩ 3.28 · 1010 4 1.22 · 10−10 Resistor 0603 1 MΩ 3.28 · 1010 4 1.22 · 10−10 Resistor 0603 390 kΩ 3.28 · 1010 1 3.05 · 10−11 Resistor 0603 1.5 kΩ 3.28 · 1010 1 3.05 · 10−11 Resistor 0603 3.3 kΩ 3.28 · 1010 12 3.66 · 10−10 Diode HSMS2855 1.50 · 1011 9 6.00 · 1011 74HC00 logic gate 1.51 · 108 1 6.62 · 10−9 ADG901 RF switch 8.88 · 108 8 9.01 · 10−9 C. Reliability 245

AP2141 power switch 1.00 · 109 1 1.00 · 10−9 SN74LVC1G32 logic 9.66 · 108 1 1.04 · 10−9 AD5663R DAC 3.67 · 109 1 2.73 · 10−10 AD8003 Op.Amp. 5.73 · 109 3 5.23 · 10−10 ADCMP604 comparator 5.73 · 109 9 1.57 · 10−9 ADG936 RF switch 8.88 · 108 1 1.13 · 10−9 OPA2830 Op.Amp. 9.84 · 107 1 1.02 · 10−8 ADCMP600 comparator 5.73 · 109 1 1.74 · 10−10 ADG801 switch 3.67 · 109 1 2.73 · 10−10 AD7478A ADC 3.67 · 109 1 2.73 · 10−10 System FIT 4.77 · 10−8 System MTBF (hours) 2.09 · 107 System MTBF (years) 2391 Table C.1: Reliability estimation for the Level 1, only com- ponents

According with table C.1, An average of only 1 failure in each 2391 years is expected. This number is very high, because it corresponds to a relatively small subsystem. Considering that there will be 265 Level 1 modules in each camera, every camera will suffer one Level 1 failure in 9 years as an average. Additionally, it is important to notice that the estimation of table C.1 corresponds only to the components, considering that the Level 1 is integrated in the front-end board. If the Level 1 is installed as a mezzanine, the failure rate of the connectors must be taken into account. According to FIDES model, for a 52 contacts SMD connector, a MTBF of 1.13 · 108 is expected. Once included in the estimation, an MTBF of 1.53 · 107 hours (1745 years) is obtained for the Level 1 mezzanine.

Component Value Unit MTBF (hours) Quantity FIT (in 1 hour) LP38690DT-2.5 1.81 · 109 1 5.51 · 10−10 LM22672MR-5.0 4.62 · 108 1 2.17 · 10−9 CDCV304PWRG4 3.41 · 108 1 2.93 · 10−9 DS1123L-200 7.13 · 108 9 1.26 · 10−8 SFP box x4 9.14 · 107 3 3.28 · 10−8 LP38691DT-1.8 1.81 · 109 1 5.51 · 10−10 CSD18534Q5A 3.45 · 108 2 5.80 · 10−9 Artix-7 FPGA 1.43 · 108 1 7.00 · 10−9 B240A-13-F 4.34 · 108 1 2.30 · 10−9 JTAG connector 3.64 · 108 1 2.75 · 10−9 Jumper 2 vias 9.64 · 108 1 1.04 · 10−9 SN65LVDS101 2.88 · 108 12 4.17 · 10−8 LP3878SD-ADJ 1.99 · 108 1 5.02 · 10−9 SN65LVDS100 2.88 · 108 12 4.17 · 10−8 Raspberry Pi 2.67 · 108 1 3.74 · 10−9 connector RJ45 connector 1.70 · 108 1 5.87 · 10−9 Power connector 9.64 · 108 1 1.04 · 10−9 246 C. Reliability

LM3151MHE-3.3 4.62 · 108 1 2.17 · 10−9 TC77 2.99 · 108 1 3.34 · 10−9 Green LED SMD 5.39 · 108 5 9.28 · 10−9 Fuse 0.5 A 2.04 · 108 1 4.90 · 10−9 Capacitor 0603 10V 1 µF 1.82 · 1010 4 2.20 · 10−10 Capacitor 0603 50V 1 µF 1.82 · 109 1 5.49 · 10−11 Inductor 0805 1 µH 4.34 · 109 24 5.53 · 10−9 Inductor 0603 1 µH 4.34 · 109 4 9.22 · 10−10 Fuse 1.5 A 2.06 · 108 2 9.69 · 10−9 Capacitor 0805 2.2 µF 1.82 · 1010 1 5.49 · 10−11 Resistor 0603 2.4 kΩ 3.28 · 1010 1 3.05 · 10−11 Fuse 2.5 A 2.05 · 108 1 4.88 · 10−9 Resistor 0603 4.7 kΩ 3.28 · 1010 3 9.15 · 10−11 Capacitor 0805 4.7 µF 1.82 · 1010 2 1.10 · 10−10 Capacitor 0603 4.7 µF 1.82 · 1010 1 5.49 · 10−11 Capacitor 0402 4.7 µF 1.82 · 1010 44 2.42 · 10−9 Inductor XAL1010 8.3 µH 2.63 · 107 1 3.80 · 10−8 Resistor 0603 10 kΩ 3.28 · 1010 60 1.83 · 10−9 Capacitor 0603 10 nF 1.82 · 1010 2 1.10 · 10−10 Capacitor 0805 10V 10 µF 1.82 · 1010 64 3.51 · 10−9 Capacitor 0805 25V 10 µF 1.82 · 1010 1 5.49 · 10−11 Capacitor 0805 15 nF 1.82 · 1010 1 5.49 · 10−11 Inductor XAL5050 22 µH 2.63 · 107 1 3.80 · 10−8 Capacitor 0603 39 nF 1.82 · 1010 1 5.49 · 10−11 Capacitor 1812 47 µF 1.82 · 1010 3 1.65 · 10−10 Resistor 0603 61.9 kΩ 3.28 · 1010 1 3.05 · 10−11 Resistor 0402 100 Ω 3.28 · 1010 2 6.10 · 10−11 Resistor 0603 100 Ω 3.28 · 1010 15 4.57 · 10−10 Capacitor 0603 25V 100 nF 1.82 · 1010 75 4.12 · 10−9 Capacitor 0805 100 nF 1.82 · 1010 1 5.49 · 10−11 Capacitor 0603 50V 100 nF 1.82 · 1010 1 5.49 · 10−11 Capacitor 0603 100 pF 1.82 · 1010 36 1.98 · 10−9 Capacitor 0402 100 pF 1.82 · 1010 4 2.20 · 10−10 Capacitor 1206 100 µF 1.82 · 1010 4 2.20 · 10−10 Capacitor 1210 100 µF 1.82 · 1010 9 4.94 · 10−10 Al capacitor 180 µF 1.82 · 109 2 1.10 · 10−9 Al capacitor 220 µF 1.82 · 109 1 5.48 · 10−10 Resistor 0603 249 Ω 3.28 · 1010 1 3.05 · 10−11 Resistor 0603 330 Ω 3.28 · 1010 2 6.10 · 10−11 Ta Capacitor 330 µF 1.58 · 109 1 6.34 · 10−10 Capacitor 0603 470 nF 1.82 · 1010 1 5.49 · 10−11 Capacitor 0402 470 nF 1.82 · 1010 65 3.57 · 10−9 Resistor 0603 500 Ω 3.28 · 1010 1 3.05 · 10−11 Raspberry Pi 2.00 · 106 1 5.00 · 10−7 C. Reliability 247

SFP transceiver 3.49 · 107 12 3.44 · 107 Avago AFBR5715ALZ System FIT 1.15 · 10−6 System MTBF (hours) 8.68 · 105 System MTBF (years) 99 Table C.2: Reliability estimation for the Trigger Interface Board

In the case of the Trigger Interface Board, a MTBF of 8.65 · 105 hours (99 years) is obtained. This is much smaller than the MTBF of the Level 1 because the system has more components and because there are two components specially critical: the SFP transceivers and the Raspberry Pi. It is difficult to find reliability information about the Raspberry Pi, but it is known that its reliability is limited by the MTBF of the SD card used as hard disk drive (to store the operating system, the slow control software, etc.). The best SD cards have an MTBF of around 2 million hours. Nevertheless, this estimation considers that the SD card is read and write quite often, as in the case of using it in a photograph camera, reaching the maximum number of times that the card can be written. In the case of the Raspberry Pi used in the TIB, the SD card contains the software running in the computer, but it is not used to store data, so it will be written only for software updating. Therefore, a longer lifetime for the SD card could be possible. Regarding the SFP transceivers, there is not much to do to enlarge their lifetime, apart from avoiding to work at high temperatures. Anyway, as there is only one Trigger Interface Board per camera, 99 years of MTBF is acceptable.

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Firmado: Luis Angel´ Tejedor Alvarez.´

Doctor Ingeniero de Telecomunicaci´on.

Madrid, 15 de Julio de 2014