PHY Interface for the PCI Express*, SATA, USB 3.1, Displayport

PHY Interface For the PCI Express, SATA, USB 3.1, DisplayPort, and USB4 Architectures Version 6.0 ©2007 - 2020 Intel Corporation—All rights reserved. PHY Interface for PCI Express, SATA, USB 3.1, DisplayPort, and USB4, ver 6.0 Intellectual Property Disclaimer THIS SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE. A COPYRIGHT LICENSE IS HEREBY GRANTED TO REPRODUCE AND DISTRIBUTE THIS SPECIFICATION FOR INTERNAL USE ONLY. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY OTHER INTELLECTUAL PROPERTY RIGHTS IS GRANTED OR INTENDED HEREBY. INTEL CORPORATION AND THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF PROPRIETARY RIGHTS, RELATING TO IMPLEMENTATION OF INFORMATION IN THIS DOCUMENT AND THE SPECIFICATION. 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All product names are trademarks, registered trademarks, or service marks of their respective owners Contributors Jeff Morris Jim Choate Michelle Jen Kaleb Ruof Andy Martwick Paul Mattos Bruce Tennant John Watkins Brad Hosler Dan Froelich Quinn Devine Jamie Johnston Matthew Myers Duane Quiet Su Wei Lim Todd Witter Bob Dunstan Hajime Nozaki Hooi Kar Loo Andrea Uguagliati ©2007-2020 Intel Corporation – All rights reserved Page 2 of 182 PHY Interface for PCI Express, SATA, USB 3.1, DisplayPort, and USB4, ver 6.0 Saleem Mohammad Peter Teng Poh Thiam Teoh Efraim Kugman Sue Vining Karthi Vadivelu Sathyanarayanan Gopal Daniel Resnick Tadashi Iwasaki Mineru Nishizawa Siang Lin Tan Tina Tahmoureszadeh Yoichi Iizuka Takanori Saeki Jake Li Kokkattutharayil Abhilashkumar Rahman Ismail Andrew Lillie Zeeshan Sarwar Dave Harriman Ben Graniello Frank Kavanagh Minxi Gao Dedicated to the memory of Brad Hosler, the impact of whose accomplishments made the Universal Serial Bus one of the most successful technology innovations of the Personal Computer era. ©2007-2020 Intel Corporation – All rights reserved Page 3 of 182 PHY Interface for PCI Express, SATA, USB 3.1, DisplayPort, and USB4, ver 6.0 Table of Contents 1 Preface .................................................................................................................................... 11 1.1 Scope of this Revision .................................................................................................... 11 1.2 Revision History ............................................................................................................. 11 2 Introduction ............................................................................................................................ 15 2.1 PCI Express PHY Layer ................................................................................................. 18 2.2 USB PHY Layer ............................................................................................................. 19 2.3 USB4 PHY Layer ........................................................................................................... 19 2.4 SATA PHY Layer ........................................................................................................... 19 2.5 DisplayPort PHY Layer .................................................................................................. 20 2.6 Low Pin Count Interface and SerDes Architecture ......................................................... 20 2.7 Support for Short Reach (SR) Applications .................................................................... 21 2.8 Configurable Pairs .......................................................................................................... 22 3 PHY/MAC Interface .............................................................................................................. 22 4 PCI Express, USB, USB4, and DisplayPort PHY Functionality ........................................... 31 4.1 Original PIPE Architecture ............................................................................................. 33 4.1.1 Transmitter Block Diagram (2.5 and 5.0 GT/s) ....................................................... 33 4.1.2 Transmitter Block Diagram (8.0/10/16/32 GT/s) .................................................... 34 4.1.3 Receiver Block Diagram (2.5 and 5.0 GT/s) ........................................................... 34 4.1.4 Receiver Block Diagram (8.0/10.0/16/32 GT/s) ...................................................... 35 4.2 SerDes Architecture ........................................................................................................ 37 4.2.1 SerDes Architecture: Transmitter Block Diagram ................................................... 37 4.2.2 SerDes Architecture: Receiver Block Diagram ....................................................... 37 5 SATA PHY Functionality ...................................................................................................... 38 5.1 Transmitter Block Diagram (1.5, 3.0, and 6.0 GT/s) ..................................................... 39 5.2 Receiver Block Diagram (1.5, 3.0 and 6.0 GT/s) ........................................................... 40 6 PIPE Interface Signal Descriptions ........................................................................................ 40 6.1 PHY/MAC Interface Signals – Common for SerDes and Original PIPE ....................... 41 6.1.1 Data Interface .......................................................................................................... 41 6.1.2 Command Interface ................................................................................................. 45 6.1.3 Status Interface ........................................................................................................ 64 6.1.4 Message Bus Interface ............................................................................................. 72 6.1.4.1 Message Bus Interface Commands .................................................................. 73 6.1.4.2 Message Bus Interface Framing ....................................................................... 75 6.2 PHY/MAC Interface Signals – SerDes Architecture Only ............................................. 76 6.2.1 Data Interface .......................................................................................................... 76 6.2.2 Command Interface ................................................................................................. 76 6.3 PHY/MAC Interface Signals – Original PIPE Only ....................................................... 77 6.3.1 Data Interface .......................................................................................................... 77 6.3.2 Command Interface ................................................................................................. 80 6.4 External Signals – Common for SerDes and Original PIPE ........................................... 85 7 PIPE Message Bus Address Spaces ....................................................................................... 89 7.1 PHY Registers ................................................................................................................. 91 7.1.1 Address 0h: RX Margin Control0 ............................................................................ 92 7.1.2 Address 1h: RX Margin Control1 ............................................................................ 92 7.1.3 Address 2h: Elastic Buffer Control .......................................................................... 93 7.1.4 Address 3h: PHY RX Control0 ............................................................................... 93 7.1.5 Address 4h: PHY RX Control1 ..............................................................................

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