LD-MOS Modeling in HV- CMOS Process - Ehrenfried Seebacher, Werner Posch, Biswanath Senapati, Kund Molnar and Alexander Steinmair

LD-MOS modeling in HV- CMOS Process - Ehrenfried Seebacher, Werner Posch, Biswanath Senapati, Kund Molnar and Alexander Steinmair

Parasitic BJT Modeling LD- MOS Transistor Modeling Parasitic Modeling

Abstract: In this poster we present highly accurate High Voltage LDMOS-transistor models for Unsymmetrical LD- NMOS Symmetrical LD-NMOS analog applications. Special sub-circuits are demonstrated in order to model symmetrical and un- - BSIM3v3 based sub-circuit is used to model symmetrical N- and P- LDMOS transistors with emphasis on modeling of on resistor (RON), quasi correctly RON and the quasi saturation effect saturation effects, body currents and parasitic diode/bipolar effects in addition to the standard MOS effects. The high flexibility of the sub-circuits allows individual configurations for all kind of LDMOS - Using standard S/D diodes is not possible transistors. The paper shows different implementations of the parasitic behavior with diodes or BJTs - LDMOS: well-psub and PTUB-drain well for length and width scalable isolated and non isolated n- and p- channel HV transistors. psub1! - Parasitic PNP turned off in regular operation - e.g. inductive loads Leaving turned on parasitic Unsymmetrical LD- PMOS Isolated HV- NMOS Transistor Symmetrical HV- NMOS Transistor pnp - Parasitic pnp included into model for floating Parasitic modeling for HV CMOS technologies results HV-NMOS and HV-PMOS devices in unequal sub-circuits for symmetrical or unsymmetrical N or P LDMOS transistors. - Parasitic drain-source and well junction caps and leakage currents are modelled within the bipolar SUB D S B S D SUB G G - Length and width scalable models for LDMOS and parasitic bipolar DPTUB Vd - A substrate current will be generated Parasitic BJT Modeling HIT-Kit enables each current of each Introduction: High voltage CMOS technologies with lateral LDMOS transistors are used in markets like portable devices, automotive applications and display drivers. A accurate device model is DNTUB key for the high efficiency of the circuit design. Increased breakdown voltages of HV transistors are achieved by an additional “drift region” between the gate and drain terminal. This HV MOS device to be plotted. device type is called Lateral Diffused MOS (LDMOS) transistor. Moreover parasitics resulting from complicated well structures are not sufficiently accounted for. The lack of existing analytical compact models in commonly available simulators for scalable LDMOS transistors can be overcome by introduction of sub-circuits. Standard low voltage MOS transistor models such as BSIMx.x or EKVx are not accurate enough for these purposes. They even miss the exact device behavior e.g. in the saturation regime but often times even in the quasi-saturation and Rdson regime. PSUB Deviations are due to the fact that the behavior of a HV MOS transistor is generally different compared to standard analog low voltage MOS transistors. These LDMOS transistor sub-circuits need to be compatible with all major SPICE simulators and need to include additional physical effects such scalable quasi- saturation, substrate currents as well as parasitic capacitances, diodes and bipolars. With this approach, highly accurate LDMOS SPICE models can be generated from standard BSIM3 or EKV low voltage transistor models. The characteristic curves presented below Models must be scalable for enabling the designer to select MOS devices of arbitrary length (L) and width (W). show a comparison between measurement data and simulation data and give an impression about the good agreement between measurement and model. Parasitic bipolar scaling is assumed by the device area. Therefore the area parameter of the parasitic bipolar transistor The control of parasitics is essential for HVCMOS technologies and the LDMOS devices because there is no buried layer available in HV CMOS technology. The switching of inductive loads can result in the turn-on of parasitic bipolar transistors. An example of such a parasitic bipolar effect in an LDMOS can be seen in the right upper part of the poster. Highly accurate compact modeling has to be a combination of MOS transistor length and width. Standard SPICE Gummel Poon model is used for the is essential for controlling these parasitics effectively in circuit design and avoiding detrimental substrate currents and latch-up. parasitic BJT. The MOS transistor substrate current is modeled as collector current of the parasitic bipolar structure. Flexible Sub– circuit LD-MOS Transistor Modeling The advanced scaling equations which include the lateral and vertical BJT result in accurate modeling of the bipolar characteristics (Beta and Gummel plot). Temperature behavior of substrate current is modeled from -40 … 200 deg C.

D D The plots below shows the parasitic bipolar behavior of a unsymmetrical N and a P LDMOS transistor. R1 D/G/S/B Drain/Gate/Source/Bulk R1 J2 J1 Body Current Modeling for J2 J1 V1 Voltage controlled voltage source U1 V1 C1

UV1 C1 J1/J2 JFET D1 HV LDMOS Transistors D1 B M1 MOS transistor G

M1 x 10 −5 B R1 Resistor 5 G −2 −2 −2 −2 4.5 10 10 10 10 10 −6 M1 S1 4 C1 Controlled current source in 3.5 S −4 −4 −4 −4 −8 U2 V2 C2 10 10 10 10 ISUB / A 10 3 2.5

order to model the D ISUB / A −6 −6 −6 −6 −10 2 10 10 10 10 10 J3 J4 1 1.5 2 2.5 3 3.5 4 4.5 5 1.5 substrate current R1 VGS / V R2 x 10 −5 1 −8 −8 −8 −8 1.6 10 10 10 10 J2 J1 0.5 W/L = 40/10 W/L = 40/10 1.4 0 IC & IB [A] IC & IB [A] W/L=40/0.5 IC & IB [A] IC & IB [A] W/L=40/1.4 1.2 4 6 8 10 12 14 16 18 2 0 S VDS / V −10 −10 −10 −10 1 10 10 10 10 0.8 UV1 C1 ISUB / A 0.6

−12 −12 −12 −12 0.4 10 10 10 10 10 −6 D1 0.2 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 −14 −14 −14 −14 VGS / V 10 10 10 10 −8 x 10 −5 10 0.2 0.4 0.6 0.8 1 1.2 0.2 0.4 0.6 0.8 1 1.2 0.2 0.4 0.6 0.8 1 1.2 0.2 0.4 0.6 0.8 1 1.2 2 LDMOS Transistor Output Characteristic Sub - circuit Modeling Vbe [V] Vbe [V] Vbe [V] Vbe [V] 1.5 B 10 −10 1 gdb/(A/V) G −3 −3 −3 0.5 x 10 x 10 x 10 M1 −12 14 gmb / (A/V) 0 10 14 0 −2 0 −2 2.2 10 10 10 10 S −0.5 2 −1 10 −14 12 −2 −2 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 6 8 10 12 14 16 18 12 10 −4 10 −4 10 10 VGS / V VDS / V 1.8 −4 −4 Sub-circuit for HV MOS transistor modeling. The controlled Bulk current of NMOS20M (W/L=10/0.5) versus VGS Bulk current of NMOS20M (W/L=10/0.5) versus VDS 10 10 1.6 10 10 −6 −6 st st 10 10 VBS = 0, -1.8, -3.6V, VDS = 16V, (log., lin., 1 derivative) VGS = 1, 2, 3, 4, 5V, VBS = 0V, (lin., 1 derivative)

−6 −6 1.4 10 10 current source is used to implement the bulk current. 8 −8 −8 8 10 10 + = measured, ⎯ = sub-circuit model + = measured, ⎯ = sub-circuit model 1.2 −8 −8 10 10 IC & IB [A] IC & IB [A] W/L=100/20 IC & IB [A] IC & IB [A] W/L=100/20 1 −10 −10 6 6 10 W/L=10/10 10 W/L=10/10 −10 −10 10 10 0.8 Especially in HV-NMOS transistors the bulk current IB is a significant part (up to 5%) of the drain current and has to be considered for accurate −12 −12 4 4 −12 10 −12 10 0.6 10 10 modeling. The model must be scalable in length and width and it should include the special IB behavior of HV-MOS transistors. There are some 0.4 −14 −14 −14 −14 10 10 10 10 2 2 0.2 0.4 0.6 0.8 1 1.2 0.2 0.4 0.6 0.8 1 1.2 0.2 0.4 0.6 0.8 1 1.2 0.2 0.4 0.6 0.8 1 1.2 reasons to implement the bulk current using a controlled current source. Investigations showed that the internal bulk current model of transistor M1 0.2 Vbe [V] Vbe [V] Vbe [V] Vbe [V] could not be used in the sub-circuit because the voltage of node D1 does not correspond to the overall drain voltage at node D, which is mainly 5 10 15 20 25 30 35 40 45 50 2 4 6 8 10 12 14 16 18 20 5 10 15 20 25 30 35 40 45 responsible for the amount of bulk current. Further, the exponential behavior of IB depending on VDS gave an unusable magnitude of increase due to NMOS50HS output characteristic of a typical wafer. W/L = 20/20, PMOS20H output characteristic of a typical wafer. W/L = 40/1.1, NMOS50H output characteristic of a typical wafer. W/L = 40/1, NMOSI50H Gummel plot of the parasitic pnp transistor of a typical wafer. the large voltage range at the drain, e.g. up to VDS=50V. Therefore the VDS dependence of the original BSIM3v3 formula had to be adapted. PMOS50H Gummel plot of the parasitic npn transistor of a typical wafer. W/L = 40/0.5; 40/10;100/20; 10/10 , VBC = 0 V VGS = 2.9,.4.8,6.7,8.6,10.5,12.4,14.3,16.2,18.1,20 V, VBS = 0 V VGS =-2,-4,-6,-8,-10,-12,-14,-16,-18,-20 V, VBS = 0 V VGS = 2.9,.4.8,6.7,8.6,10.5,12.4,14.3,16.2,18.1,20 V, VBS = 0 V W/L = 40/1.4; 40/10;100/20; 10/10 , VBC = 0 V Additional details e.g. the fact that short devices have their maximum IB at about half VGSmax, whereas long devices have their maximum at VGSmax + = measured, ⎯ = sub-circuit model o = measured, ⎯ = Sub-circuit model or the onset of IB depending on VDS and the used oxide thickness (7nm, 14nm, 48nm) were also included. Using the current source gives also the + = measured, ⎯ = sub-circuit model + = measured, ⎯ = sub-circuit model o = measured, ⎯ = Sub-circuit model opportunity to implement the bulk current in symmetrical transistor sub-circuits. The characteristic curves presented above show a comparison between measurement data and simulation data and give an impression about the good agreement between measurement and model. strictly confidential copyright AG austriamicrosystems ©2008