Embedded Computing Design

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COLUMNS FEATURES 7 Editor’s Foreword SPECIAL: How embedded computing is making Alliances, consortiums, and trade organizations new consumer electronics possible By Jerry Gipper 17 Embedded? Consumers are soaking in it By Don Dingee and Jerry Gipper 9 Embedded Europe Embedded world highlights By Hermann Strass TECHNOLOGY: Data acquisition 23 A low-cost, on-site, reconfigurable client DAQ system 12 Eclipse Perspective and News By Srirama Chandra, Lattice Semiconductor How Eclipse fits with embedded development By Madison Turner and Robert Day 30 Image fusion: Shared memory supports flexible, multiple sensor imaging systems By Ralph Barrera, Curtiss-Wright Controls Embedded Computing EVENTS APPLICATION: Home systems – entertainment, ESC Silicon Valley April 3-7 • McEnery Convention Center, San Jose, California security, control, monitoring www.embedded.com/esc/sv 33 Bringing programmability to the CE market: Winning design strategies Server Blade Summit By Todd Scott, Altera April 18-20 • Hyatt Regency, Garden Grove, California www.serverbladesummit.com PRODUCT GUIDE FPOAs surmount multimedia decoding hurdles Page/RSC# Advertiser Product description 39 By Sean Riley, MathStar 10 ACCES I/O Products Analog, Digital, Relay and Serial I/O 44 Advantech SOM Solutions 41 Product listings: Devices – ASIC, DSP, FPGA, SoC, microcontrollers 16 Annapolis Micro Systems FPGA Systems 11 Arcom Control Systems Apollo Fanless Computer 42 Axiomtek Embedded Solutions 2 Diamond Systems Embedded Solutions PCI EXPRESS 45 EDT PCI Boards Avoiding unexpected challenges in PCI Express core integration 8 Embedded Planet Hardware and Software Solutions 42 1402 Grid Connect Ethernet Software By Tony Sousek and Nick Sgoupis, CAST 13 Hellosoft HelloIP-PhoneT 7 Hunt Engineering USB Connected Programmable FPGA Systems 601 ICP America GoPC-Mobile 47 Intel Architecture and XScale E-CASTS 48 Interactive Circuits & Sys. ICS daqPC New VITA standards: Strengths, weaknesses, target applications, 22 Kontron ETXexpress-CD and what you need to know to be able to differentiate between them 5 Micro/sys EBX, EPIC, PC/104 15 Moxa Technologies UC-7420 April 25, 2 p.m. EST 27 Precision Analog Systems Analog and Digital I/O Cards www.opensystems-publishing.com/ecast 24 Radian Heatsink CFD Simulations and Custom Designs 602 SCIDYNE PC/104 Peripherals X-Midas Applications for Small Spaces and Harsh Environments 29 Sundance SMT498 prPMC FPGA Module May 3, 11 a.m. EST 21 Technologic Linux FPGA Computer www.opensystems-publishing.com/mercury.html 32 Themis Computer Themis Slice 37 Toronto MicroElectronics Embedded Computer Solutions 38 Toronto MicroElectronics ECM401 46 Toronto MicroElectronics Micro-P3 E-LETTER 34 Tri-M Systems MOPSlcd7 35 Tri-M Systems TMZ104 www.embedded-computing.com/eletter 1401 VMETRO PCI Express Embedded software drives the digital home 3 WinSystems Fanless EBX 733MHz P3 By C.C. Hung, Mentor Graphics, and Richard Schmitt, Blue Peach WEB RESOURCES Published by: Subscribe to the magazine or E-letter: www.opensystems-publishing.com/subscriptions Industry news: Read: www.embedded-computing.com/news © 2006 Embedded Computing Design Submit: www.opensystems-publishing.com/news/submit All registered brands and trademarks within Embedded Computing Design are property of their respective owners. Submit new products: www.opensystems-publishing.com/vendors/submissions/np / April 2006 EmbeddedOpenSystem Computing Designs Publishing™

A n O p e n S y s t e m s P u b l i c a t i o n

Embedded and Test & Analysis Group n Embedded Computing Design n Embedded Computing Design E-letter n Embedded Computing Design Resource Guide n Industrial Embedded Systems n Industrial Embedded Systems E-letter n Industrial Embedded Systems Resource Guide n PXI, Test & Technology n PXI, Test & Technology E-letter Editorial Director Jerry Gipper [email protected] Contributing Editor Don Dingee Technical Editor Chad Lumsden [email protected] Associate Editor Jennifer Hesse [email protected] European Representative Hermann Strass [email protected] Special Projects Editor Bob Stasonis Senior Designer Joann Toth Senior Web Developer Konrad Witte Graphic Specialist David Diomede Circulation/Office Manager Phyllis Thompson [email protected]

RSC# 01 @ www.embedded-computing.com/rsc OpenSystems Publishing Editorial/Production office: 16872 E. Avenue of the Fountains, Ste 203, Fountain Hills, AZ 85268 Tel: 480-967-5581OpenSystem sn Fax: 480-837-6466 Website:Publishing www.opensystems-publishing.com™ Publishers John Black, Michael Hopper, Wayne Kristoff Vice President Editorial Rosemary Kristoff

Communications Group Editorial Director Joe Pavlat Assistant Managing Editor Anne Fisher Senior Editor (columns) Terri Thorson Technology Editor Curt Schwaderer Associate Editor Jennifer Hesse European Representative Hermann Strass

Military & Aerospace Group Group Editorial Director Chris Ciufo Managing Editor Bonnie Crutcher Assistant Editor Sharon Schnakenburg Senior Editor (columns) Terri Thorson European Representative Hermann Strass European Bureau Chief Stefan Baginski

ISSN: Print 1542-6408, Online 1542-6459 Embedded Computing Design is published bi-monthly by OpenSystems Publishing LLC., 30233 Jefferson Ave., St. Clair Shores, MI 48082. Subscriptions are free to persons interested in the design or promotion of embedded computing systems. For others inside the US and Canada, subscriptions are $56/year. For 1st class delivery outside the US and Canada, subscriptions are $80/year (advance payment in US funds required). Canada: Publication agreement number 40048627 Return address: WDS, Station A, PO Box 54, Windsor, ON N9A 615 POSTMASTER: Send address changes to Embedded Computing Design 16872 E. Avenue of the Fountains, Ste 203, Fountain Hills, AZ 85268 RSC# 02 @ www.embedded-computing.com/rsc

/ April 2006 Embedded Computing Design Alliances, consortiums, and trade organizations Jerry Gipper

n preparing our report on the Consumer Electronics Show to give electronics designers a leg up on staying ahead of the (CES), it struck me how often we wound up at various alliance technology curve. booths during the show. Companies often rally around a ■ FPOAs surmount multimedia decoding hurdles, composed by market or a technology to promote it to potential users and/ Sean Riley of MathStar. Field Programmable Object Arrays or to develop supporting degrees of standards using this (FPOAs) are high-performance programmable logic devices technology. programmed at the object level instead of the gate level. Sean introduces us to this new class of programmable devices and Many developer alliances in existence drive and standardize how they can be used in decoding MPEG2 video. technology. OpenSystems Publishing tracks more than 75 allian- ■ Avoiding unexpected challenges in PCI Express core inte- ces, consortiums, and trade organizations of various types that gration, written by Tony Sousek and Nick Sgoupis of CAST, complement the embedded computing industry in some fashion. Inc. The authors discuss various pitfalls and options to avoid One or two new organizations seem to be added to the list each them in developing your own PCI Express end-point control- month. Some of these alliances or consortiums are ecosystems for ler using off-the-shelf intellectual property. specific suppliers or a technology. The founding supplier usually sets the standards while the alliance members promote their Your suggestions and comments are welcome. Please contact me products based on this standard. Others are market/technology at [email protected]. trade associations that collaborate on defining the technology for next-generation development. Several are even accredited by recognized standards bodies to develop official technology specifications. Jerry Gipper, Editorial Director Many companies hedge their bets by participating in multiple alliances, consortiums, and trade organizations even though they compete or overlap in nature. This sometimes makes validating a company’s true strategy or direction and understanding a company’s goals confusing.

We invite embedded computing alliances, consortiums, and trade organizations to contribute their stories to us so that we can convey relevant information to the general embedded computing industry. I would also like to hear from embedded computing technology users on your opinion of whether these organizations help you make technology decisions.

This issue, in the meantime, covers:

■ In Embedded? Consumers are soaking in it, Don Dingee and I discuss our observations of the 2006 CES. We embarked on a mission to find applications of embedded computing technology at the largest electronics show in North America. Read this to learn what we discovered. ■ A low-cost, on-site, reconfigurable client DAQ system, written by Srirama Chandra of Lattice Semiconductor. Srirama discusses how to design a cost-effective and reconfigurable data acquisition system using FPGA technology. ■ Image fusion: Shared memory supports flexible, multiple sensor imaging systems, authored by Ralph Barrera of Curtiss-Wright Controls Embedded Computing. High- definition images are used in a large number of applications. Higher definition is often achieved by throwing more pixels and more bandwidth at the images. Ralph shows us one way to make improving the definition by combining images from multiple sensors possible. ■ Bringing programmability to the CE market: Winning design strategies, penned by Todd Scott of Altera Corporation. Giv- en that consumer electronics have notoriously short market windows, Todd considers ways to use programmable devices RSC# 7 @ www.embedded-computing.com/rsc

Embedded Computing Design April 2006 / 7 RSC# @ www.embedded-computing.com/rsc Embedded world highlights By Hermann Strass

Events where you look. The stadium has 11,000 data points (sensors) to The embedded world 2006 exhibition and conference in Nuernberg, monitor lights, heating, ventilation, sanitation, and all kinds of Germany, is the world’s largest meeting place for embedded measurement and control electronics. The translucent outside wall technology experts. In February, three exhibit halls were filled of the stadium can be lit from the inside in various combinations with more than 13,000 visitors from 27 different countries and of red, white, and blue depending on which teams are playing. nearly 500 exhibitors showing hardware, software, and tools for Embedded systems also control the parking garage, touted as embedded computing. Conference attendees could choose from Europe’s largest with capacity up to 9,800 cars. Siemens delivered 24 sessions with multiple presentations, tutorials, and workshops. and installed all of the electrical and electronic systems. Attendance was up 22 percent from last year, with 35 percent of the exhibitors hailing from overseas. STMicroelectronics, in France and Italy, has integrated a chemical and biological lab with a processor on a silicon chip. The In-Check A jury of experts selected this year’s embedded world award win- System-on-Chip has all the necessary mechanical, thermal, ners: NEC Electronics Europe in the hardware category, QNX in electrical, and fluidic connections or MicroElectro Mechanical the software category, and pls Programmierbare Logik & Systeme System (MEMS) technology with a microprocessor on a chip (PLS) in the tools category. NEC showed the world’s smallest microcontroller in a very small package of 1.9 mm x 2.2 mm (less than one-tenth of an inch on both sides). This is a complete, packaged microcontroller with flash memory in a performance range from 3 to 20 MIPS. QNX received an award for their true multiprocessing Real-Time Operating System (RTOS) for multicore chips, available in asymmetric or symmetric and bound multiprocessing variants. PLS, Germany, developed an extremely efficient universal emulation configurator to analyze data in on-chip emulators at a higher logic level than traditional trace analyzers. The state machine-based system is independent of source or emulation hardware.

Figure 1, courtesy of NuernbergMesse, shows happy award winners and organizers at embedded world 2006, including, from left to right: conference organizer Matthias Sturm, a professor from the University of Leipzig; representatives from NEC, QNX, and PLS; and exhibition organizer Bernd Diederichs of NuernbergMesse.

Automotive embedded electronics played a big role at embedded Figure 1 world 2006. Chips and systems for FlexRay showed up in great variety. A consortium of mostly European car manufacturers 7.62 mm x 2.54 mm (3" x 1"). It uses a personal computer for developed FlexRay to be used in time-triggered reliable systems, displaying the results. With In-Check, analysis can take place at like drive-by-wire or brake-by-wire. Motor Control Units (MCUs), the point of care, without having to wait one or two days for lab which help further reduce gasoline consumption in car engines, results. This minilab handles DNA analysis and other biochemi- also made an appearance. TTTech, Austria, exhibited the first cal processes. time- and event-triggered system with sensor/actor management certified to safety level SIL 3, which is used in off-highway The silicon chip can switch very fast between typical Polymerase vehicles. Chain Reaction (PCR) tasks at 94 °C, 72 °C, or 60 °C, eliminating the need to transport the biochemical fluids between different Several German companies, such as E.E.P.D., Lippert, and hot spots on the chip. The liquid stays in the microchannel inside Kontron, displayed dual-core embedded systems in various the silicon chip during temperature cycles. Heating elements and embedded form factors. EUROS Embedded Systems GmbH temperature sensors are within micrometer distance on chip and showed a version of their EUROS RTOS, which was specifically microprocessor controlled to ±0.3 °C accuracy. This temperature developed for multicore microprocessor systems. precision is required for DNA analysis, which is further enhanced by laser scanning of fluorescence in certain areas on the silicon Applications chip. Silicon in this case is superior to glass because of higher At the Allianz Arena in Munich, www.allianz-arena.de, currently light intensity. The fluidic part on this MEMS computer system Europe’s most modern stadium for sports such as soccer and is based on experience gained in the mass production of inkjet European football, embedded control electronics turn up every- printheads.

Embedded Computing Design April 2006 / This In-Check system is used for the detection of infectious diseases, sepsis (blood poisoning), pneumonia, meningitis, water pollution, food contamination, or biological warfare substances. STMicroelectronics and Veredus Laboratories announced development of a fast, point-of-need diagnostic capability that will enable health practitioners to quickly detect strains of avian flu and other influenza viruses using In-Check. The diagnostic capability, which uses reliable and inexpensive equipment, produces results within approximately one hour of testing.

News ELTEC and PHYWE, Germany, recently announced collaboration with other companies to form the Open Source Automation Development Lab (OSADL). OSADL members will be creating a standardized and certified real-time Linux for industrial automation applications. Upcoming E-cast: APRIL 25, 2006 – 2 p.m. EST Atmel, Belgium, claims 35 percent better performance per instruction cycle in their new AVR32 microprocessor core compared New VITA standards: Strengths, weaknesses, target to an ARM 11 core. The Atmel core minimizes overhead from applications, and what you need to know to be able to load/store and branch operations and maximizes pipeline through- differentiate between them put of complex algorithms at a low clock rate and low power Moderator: Chris Ciufo consumption. One special feature is direct execution of block Presented by: VMEtro, Curtiss Wright, cipher algorithms in cryptographic applications like Blowfish, Tundra, Hybricon OpenSystems Triple-DES, and Rijndael (AES). Some parts of the AVR can Publishing™ quadruple the throughput of DSP algorithms in Single Instruction Multiple Data (SIMD) instructions, especially when running Registration and archived E-casts available at: under a Linux OS. www.opensystems-publishing.com/ecast

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10 / April 2006 Embedded Computing Design RSC# 11 @ www.embedded-computing.com/rsc PERSPECTIVE AND NEWS How Eclipse fits with embedded development

By Madison Turner and Robert Day

roviding tools for the embedded software developer is a very complex task. The wide range of processor architectures, develop- Pment host systems, Real-Time Operating Systems (RTOSs), and application-specific requirements has traditionally meant these tools have been proprietary in nature. The team does not need deeply embedded probes and hardware tools, as the appli- Unfortunately, this means the embedded cation is running on debugged COTS hard- software developer has had to relearn ware. Instead, much more attention is spent and rebuy solutions all essentially doing on the software issues, not dissimilar to the same thing. No standard environment the enterprise space. The standard Eclipse Figure 1 displays an example of how or tool suite could meet all these diverse platform offers a rich project navigation Eclipse can be used to debug Linux to requirements … until now. and project management plug-in focused the thread level, showing LynuxWorks’ on developing application software. The Luminosity IDE in action. Enter Eclipse. Born from the enterprise CDT project from Eclipse adds some specific C and C++ build tools that give space, this open environment is now pro- Debugging a hard-real viding a common platform that embed- specific C/C++ editors and a sophisticated build environment built around the GNU time system on proprietary ded developers can buy once, use many. hardware But, how exactly can this nonembedded compilers. For a Linux developer, this is a For more deeply embedded devices, the platform meet the needs of embedded good starting point to help manage source Eclipse framework can utilize a debug developers? files and Linux builds. perspective that allows connection to the target via the JTAG port available on most Eclipse is not a product; it is a framework. Each of the embedded Linux providers embedded devices. Embedded developers It allows embedded vendors to plug in also offers a debug plug-in to Eclipse face the issue of the large number of target proprietary tools into a common environ- that allows the developer to debug their boards that exists, each configured slight- ment. Part of its appeal is that it actually embedded Linux applications, with full ly or significantly different. Connection goes much further and defines the look awareness of the target hardware and what wizards ease the process of establishing and feel of plug-ins, too. the Linux operating system is doing as the developer steps through the application. a connection to an embedded target by providing standard configurations for For embedded developers, this means: This debugger is often connected to the COTS board using standard Ethernet popular targets and connection devices. These wizards offer a centralized and ■ They have a common Integrated connections, and hence doesn’t even easy-to-use interface for specifying de- Development Environment (IDE) need hardware connection technology to bug session parameters. For example, meeting many of their common facilitate it. All of this is achieved without the user can choose an output file to load software development needs, such as leaving the Eclipse environment, and bet- automatically and specify a symbol to run project management, version control, ter still, is integrated with available soft- to upon loading. and source code browsing ware management products not specific ■ They also have access to tools meeting to embedded development. While a register view displays and modifies specific embedded needs that plug into register values, a variable view operates the environment and offer a common Linux developers can take advantage similarly for the contents of variables look and feel of open source for both the OS and the tools, but also have an environment that and data structures, with structures and their members laid out hierarchically for a Let’s examine a couple of examples of is embedded aware, of high quality, and logical and usable view of the target data. embedded software tools used for different with a common Application Programming A memory view displays and modifies an purposes, but share this common IDE. Interface (API) to the tools used in hard real-time systems if needed. This last address or address range. In these views, point becomes relevant when embedded values are displayed in the radix specified Debugging a Linux systems have a large application part that by the user: binary, decimal, hexadecimal, application on a standard can be well served by Linux and a hard or octal. A memory map view graphically COTS board real-time part that needs to be serviced displays the layout of the application in In this case, the embedded software team by a hard RTOS. Eclipse can be used target memory in terms of program sec- is very software and application centric. for both. tions, files, or functions.

12 / April 2006 Embedded Computing Design The fastest way to say “hello” with VoIP

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Proven, portable code for IP handsets, ATAs, mobile phones, carrier edge equipment, and other VoIP clients

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With the addition of a scripting language for application-specific debugging support, the combination of an Eclipse-based embedded debugger and JTAG probe can provide Figure 1 unprecedented levels With the addition of a scripting language scripts carry out debugging operations on for application-specific debugging support, the target and format, manipulate, and of insight into the the combination of an Eclipse-based em- display that information on the host. In bedded debugger and JTAG probe can this way, extremely sophisticated de- provide unprecedented levels of insight bugging techniques can be developed target application. into the target application. In this scenario, specific to the application under test.

Embedded Computing Design April 2006 / 13 Figure 2 For example, a block of target memory and memory usage. It also makes task- values representing a video file can be specific break-points available. uploaded via JTAG and viewed in a media player on the host to ensure the integrity These examples show how the differ- of the content. A tool such as the Mentor ent hardware, software, and application- Graphics Nucleus EDGE IDE shown in specific requirements typical in today’s Figure 2 supports these functions. diverse embedded applications can be united in a single development environ- Another powerful feature that relies on ment – powered by an open source platform the Eclipse framework in concert with called Eclipse, the today and tomorrow of a JTAG connection is kernel awareness embedded tool environments. for a hard RTOS. Kernel structures, including tasks, communications mechanisms, Madison Turner is a technology timers, and memory pools, are monitored analyst at Mentor Graphics Embedded over the JTAG connection and made Systems Division, where he focuses on easily navigable within the debug view. next-generation development tools and Kernel-aware debugging makes it easy to methodologies. analyze task interaction, real-time logic, Robert Day is the vice president of marketing for LynuxWorks. His responsibilities include leading program management teams and driving worldwide marketing initiatives, including corporate communications and brand strategy.

For more information, contact Madison or Robert at: Mentor Graphics 739 N. University Blvd. Mobile, AL 36608 Tel: 251-208-3400 E-mail: [email protected] Website: www.mentor.com/embedded

LynuxWorks 855 Embedded Way San Jose, CA 95138-1018 Tel: 408-979-3900 E-mail: [email protected] Website: www.lynuxworks.com RSC# 1401 @ www.embedded-computing.com/rsc RSC# 1402 @ www.embedded-computing.com/rsc

14 / April 2006 Embedded Computing Design RSC# 15 @ www.embedded-computing.com/rsc RSC# 16 @ www.embedded-computing.com/rsc Embedded? Consumers are

By Don Dingee and soaking in it Jerry Gipper

rom our perspective at Embedded used to calling a gas pump. With Computing Design, we see a con- Microsoft Windows CE and sumer embedded computing mar- the Microsoft .NET framework ket nearly six times the size of integrated, this fuel dispenser the personal computer market. The does much, much more. It FConsumer Electronics Association fore- integrates a full multimedia casts $135 billion in total factory sales station with a 10.4" color display of consumer electronics in 2006 and PCs and speaker, enabling consumers represent less than $20 billion of that to engage with full-motion, site- number. The majority of devices included specific commercial content and in the remaining $115 billion forecast con- gain access to coupons, specials, tain an embedded computing element. promotions, lottery tickets, traffic reports – a whole range of information. Figure 1 Computers are being designed into every- Dresser’s iX Technology Platform also day devices more and more, and devi- enables functions for retailers such as ces under the broad label of consumer advanced diagnostics, point-of-sale fea- Serving up entertainment electronics really are driving the revolu- tures independent of the in-store POS It’s clear vendors are vying for where tion. And it’s a big playing field, so much system, and management of the multi- and how media and data are stored and so that it has spawned the largest trade media functions and usage reports. We exchanged in the home. Companies are show in North America, the Consumer contemplated that it would only be a taking several different approaches with Electronics Show (CES) in Las Vegas. matter of time before the fuel dispenser devices dedicated to exchanging and communicates directly via wireless to managing content for home entertainment When the words road trip were uttered, systems. the Embedded Computing Design editor- your car to do a quick health check. ial team jumped at the chance to pile into Multimedia home entertainment was a a car and make the drive up to Las Vegas Another multimedia device we saw was the major buzz area at CES. Vendors hawking for the couple of days in January to see Pepper Pad (Figure 1), www.pepper.com, their solutions constantly surrounded us. firsthand the spectacle that is CES. We a 2.3 pound Linux-based handheld with All seemed to have a common element of a weren’t looking for the normal stuff, built-in Wi-Fi and Bluetooth, 20 GB hard PC buried in the system somewhere, either although it was abundant; large screen disk, 800 x 600 color LCD and touch displayed obviously or hidden within a HDTVs, mobile phones, GPS devices, screen, keypad and navigation and scroll new HDTV. Intel and Microsoft again personal media players, and the like were controls, speakers and microphone jack, took the lead as they touted their solu- easy to find. Instead, we were looking for USB, and an SD/MMC slot. Built as a tions, Intel with their Viiv technology and some of the novel ways embedded com- multimedia platform to run Java, flash, Microsoft with PlaysForSure. The brands puting technology is being applied to and Mozilla-based applications as well permeated the show as they competed to make our lives easier. as C and C++ code, its Intel Xscale gain mindshare. PXA270 processor is coupled with an Multimedia devices morphing Intel 2700G media processor to pack a lot The Multimedia over Cable Alliance One of the first displays seen before of power in a small package. It’s design- (MoCA), www.mocalliance.org, is target- even entering the hall was the Dresser ed to be a quick, portable connection to ing use of the existing cable infrastructure Wayne, www.wayne.com, Ovation iX the Internet for e-mail, IM, videos, Web in many homes as the main entertainment fuel dispenser, what most of us are browsing, and similar activities. backbone. According to the alliance, coax

Embedded Computing Design April 2006 / 17 cable – made to carry high-quality, high- CDs, MP3s, recorded TV programs, and digital photos. EI offers the Life|ware approach, speed video signals – is in more than unifying the user experience to control lighting, climate, security system, cameras, and 70 percent of U.S. homes, and has large entertainment systems, all through the same easy-to-use interface and a single remote. amounts of unused bandwidth. The standard is based on high speed (270 Mbps), The SVP Alliance, www.svpalliance.org, focuses on creating standards for video pro- high Quality of Service (QoS) signaling, cessing chips to help protect content rights. Targeting set-top boxes, digital televisions, and the innate security of a shielded, and portable multimedia devices, the Secure Video Processor technology uses certificate- wired connection combined with state-of- based licensing to protect content and allow enabled receivers to decrypt and decom- the-art packet-level encryption. Promoter press it. companies in the set-top box and cable operator industry such as Comcast, Cox, By the way, one thing we couldn’t help but notice – if the television manufacturers have Dish Network, Linksys/Cisco, Motorola, their say, you will never buy another tube-based TV again. Everything is flat-panel Panasonic, RadioShack, Toshiba, and technology of one kind or another. There is also a big push for custom televisions with Verizon are behind this standard. Entropic cabinets and cases that can match any home or room décor. Mass customization is making Communications, www.entropic-commu- its impact on television. nications.com, also a promoter company, and Octalica, www.octalica.com, currently Audio sounding great make chipsets for MoCA compliant de- Dolby Laboratories, www.dolby.com, exhibited a range of applications for their licensed vices. Entropic’s c.LINK chipset with an IP in a large booth, including automotive. In collaboration with Intel, Dolby is working to RF interface and a baseband controller create what they call the PC Entertainment Experience, a branded approach to delivering and integrated MAC began shipping at the high-quality, certified audio including the ability to author DVDs with Dolby Digital end of 2004 and now leads the market, just surround sound. reaching the 500,000 mark as of March 1. Induction Dynamics has taken a high-density ED Digital launched their Digitrex, iron-alloy magnetic material invented by the www.digitrexusa.com, brand in the United U.S. Navy for sonar applications, Terfenol-D, States with their first product for the and designed it into a product called Solid market, announcing what they call the Drive (Figure 3), www.soliddrive.com, which networked TV (Figure 2) featuring na- can transform a solid surface such as drywall, tive support for Microsoft Windows glass, granite, or wood into a speaker. They Media Connect technology. This allows claim Solid Drive is omnidirectional at near- consumers to view pictures and movies, ly all frequencies and maintains channel and listen to music stored on their Windows XP PC anywhere in their separation. Now the walls will be able to talk Figure 3 home on the networked TV. The Digitrex as well as listen. Network TVs are easy-to-use, full 1080i LCD flat panels with wired and 802.11 b/g Wolfson Microelectronics, www.wolfsonmicro.com, showed its new WM8569 single- wireless networking capabilities, and take chip stereo audio codec for DVD, personal video recorder, LCD TV, and automotive applications. The WM8569 integrates D/A and A/D functions in a single 28-pin SSOP device, operating on 24-bit sigma delta converters with sample rates of 192 kHz for the D/A and 96 kHz for the A/D. Control is implemented with a simple 3-wire SPI, and the device provides better than 100 dB signal-to-noise ratio.

All your homes are controlled by … Similar to the home entertainment side, home automation and control strategies are also varied, using several different network and user interface approaches. Control networks tend to be simpler and lower cost.

Home automation systems of one kind or another have been around for many years, but there seems to be an inflection point initiating momentum in automation systems. It is Figure 2 likely a combination of system costs, home costs, and fuel costs all coming together to make it more practical for the typical home to become automated. The influence of home advantage of Microsoft’s PlaysForSure multimedia centers is also evident as the media center can also be the brains for home technology. Steve Jean, vice president of automation. marketing and product development for ED Digital, said, “It’s never been easier SmartLabs announced the first of its INSTEON chips, www.insteon.net, in its pavilion. for consumers to enjoy all the music files, INSTEON, short for instantly on, a control network fast enough to be perceived as instant, digital pictures, and videos they’ve stored uses a dual mesh with both powerline wired and RF links inside the home, and can bridge over time, and share them with family to other networks, including X10 and Wi-Fi. See the sidebar on INSTEON Home Control and friends, while relaxing in the comfort Technology from SmartLabs for background and technical highlights. An alliance with and convenience of their living or family more than 300 member companies supports INSTEON including names like Somfy, First entertainment room.” Alert, Maya, Integration Associates, Elk, Visonic, Universal Electronics, and EI, and at least 40 new products are in development for home automation roles including lighting, Another company, Exceptional Innovation (EI), security, comfort, and consumer electronics. www.exceptionalinnovation.com, showed its Life|storage digital media storage server, The Z-Wave Alliance, www.z-wavealliance.org, also had a pavilion with member with 1.5 TB of RAID 5 storage for videos, companies including Intermatic, Leviton, Logitech, and others showing various devices.

18 / April 2006 Embedded Computing Design SIDEBAR

If the television INSTEON home manufacturers have control technology their say, you will puts developers

never buy another in control By Dan Cregg tube-based TV again. SmartLabs, the leader in home automation since 1992, has seen the consumer market for home automation and control products increase for years. In that time, they also identified a central reason why home automation has not seen the explosive growth Z-Wave is a low-cost, two-way wireless that PCs and wireless phones experienced: Simply no industry-standard technology mesh network product designed for was strong enough, flexible enough, or smart enough to support it. residential control systems based on a chipset from Zensys, www.zen-sys.com. In 2001, SmartLabs began its quest to bridge the technological divide and bring The ZW0201 SoC (Figure 4) contains an home automation for the masses within reach. SmartLabs engineers listened to their integrated RF transmitter, an 8051 micro- customers, and more often than not, their complaints mirrored problems developers controller, flash and SRAM, and a range have traditionally faced; namely, customers wanted something simple, reliable, and of peripherals. It uses either 915 MHz (United States) or 868 MHz (European affordable that wouldn’t be obsolete by the time they installed it. A tall order, but Union) with a lightweight, low-power SmartLabs fulfilled it with INSTEON, and the news is as good for developers as it is protocol, and is simple to maintain as for consumers. the network self-organizes and discovers new nodes on command. One of the greatest hurdles in developing for home automation has been reliability. Previous powerline solutions offered a limited command set and suffered from unacknowledged signaling methods and common powerline issues such as phase coupling. Existing wireless technologies demand complex routing strategies, compli- cated setup, and constant network supervision, and RF in the home often presents coverage issues.

INSTEON has purposely been kept simple, both for designers and users, allowing control nodes to be made at a very low cost. In an INSTEON network, shown in Figure 1, both wired and wireless physical layers are leveraged (dual mesh), gaining the strengths of each and avoiding the weaknesses. All INSTEON devices are true peers. Every device on the network repeats every message heard, utilizing a simulcast methodology. All Figure 4 messages are confirmed, and every message is resent if an acknowledgement is not The HomePlug Powerline Alliance, received. If available, both powerline and RF networks are used, with the powerline data www.homeplug.org, sticks to powerlines being the default if unmatched messages arrive simultaneously. There are no masters or for its network. It is more than a simple slaves to manage. Reliability is kept high and synchronization kept simple through use control network, however; there are actual- of short messages – an entire message cycle is under 0.04 seconds. ly four standards in use and development. HomePlug 1.0 was the original standard. Offering higher bandwidth services for entertainment needs, HomePlug AV supports MAC bandwidths of over 100 Mbps. HomePlug BPL delivers Internet access through broadband powerline networking. HomePlug Command and Control focuses on very low-cost applications. Companies such as Comcast, Earthlink, GE Security, Intel, Linksys/Cisco, Motorola, RadioShack, Samsung, Sharp, and Sony sponsor the standards.

ZigBee, www.zigbee.org, is also gaining momentum, and we saw one of its supporters, Hawking Technology, Figure 1 www.hawkingtech.com, with their new Continued on page 20

Embedded Computing Design April 2006 / 19 Some of the technical specifications of INSTEON include: HomeRemote wireless home automation system. It provides Web-based or SMS-based monitoring and control of n Dual mesh: RF and powerline wireless sensors and devices based on a n Peer-to-peer mesh broadband Ethernet to ZigBee gateway. n Devices are repeaters n Messages acknowledged, with automatic retry The touch of your finger n 13, 165 bits/second data rate Several companies are going after a sim- n 10 word standard and 24 word extended (with user data) messages, over 16M plified home automation interface with unique device IDs and 65K commands a unified touch screen and background n Powerline: 131.65 kHz BPSK application and driver software to bring n RF: 902 to 924 MHz FSK, 150 foot line-of-sight range interfaces from several systems together. Casaworks, www.casaworks.com, brought But, wait a second. What if you want to control everything with a PC, PDA, or cell phone? their Cielo home management system, With INSTEON, that kind of control is an option, but not a requirement. That simplicity depicted in Figure 5, which integrates frees up the developer to pour time and energy into the actual device, instead of getting their Studio software with a variety of sidetracked trying to hypothesize and design around a location in a network hierarchy interfaces to home systems. Scenes can be where that device should go. programmed to establish a set of controls – lighting, audio, temperature, and win- SmartLabs developed INSTEON as virtually an open source platform to ensure that dow coverings, based on user input, pro- developers are properly equipped to fully leverage the INSTEON technology into their grammed time, or other event. projects. There are more than 500 manufacturers and developers currently working with INSTEON, and it is already being innovatively applied in ways SmartLabs did not even imagine. Freedom breeds creativity. Creativity builds solutions. Solutions make life better. And really, isn’t that what technology is supposed to be all about?

By now the cynics are thinking, great technology, but how much to get involved? A complete developer’s kit is just $99; kits contain two powerline modules, one Figure 5 power control, one lamp dimmer, with a USB or serial connection to a programming Convergent Living, www.convergentliving. host, and a software development kit. SmartLabs aims to get the best technology to com, shared with us their central home the best minds as easily and as painlessly as possible. The low cost also allows the remote concept called the Companion in startups operating out of windowless garages the same access to INSTEON as their a separate interview before CES. Based multinational competitors. on Linux and using Macromedia flash and Firefox for the user interface, subsystems Developers will also find support and a developer forum on INSTEON.net hosted by are integrated into a master control inter- the INSTEON Alliance, a focused community for developers to incorporate the INSTEON face on a 8.4" color LCD touch screen. standard into their products. Additionally, the INSTEON Alliance will host its inaugural Most systems are integrated via Ethernet connections. INSTEON Development and Technology Conference May 2 at the Santa Clara Convention Center. Home Automation, Inc. (HAI), www. homeauto.com, introduced the OmniTouch Consumers are ready to take control of their homes. INSTEON is here and ready to go with Video (Figure 6), a color touch screen to work. The only question left is, how? It’s a question developers will be answering bringing control of lighting, temperature, – brilliantly – for a long time. security, and multiroom audio systems together with the ability to display digital video of up to six cameras.

Dan Cregg, now CTO of SmartLabs, began his tenure there as director of engineering Russound, www.russound.com, introduced their UNO-TS2D, a desktop version of and product development in 1997 when SmartLabs acquired SmartLinc, a company their wall-mounted color touch screen for he cofounded. Dan also founded and was president of HomeRun Automation, which control of multiroom audo/video systems. was purchased by SmartLinc in 1997. Dan has also held engineering positions at McDonnell-Douglas, SVG Thermco, and Universal Electronics.

For more information, contact Dan at:

SmartLabs, Inc. 16542 Millikan Avenue • Irvine, CA 92606 Tel: 949-221-9200 ext. 147 E-mail: [email protected] • Website: www.INSTEON.net Figure 6

20 / April 2006 Embedded Computing Design Xantech, www.xantech.com, demonstrated their SPLCD64V LCD touch screen controller, with a companion XTR39 touch screen remote. These units combine functions of a myriad of home entertainment devices into single units with a graphical interface.

On the go AquaSonus, www.aquasonus.com, showed an interesting device (Figure 7), a pool security hydrophone designed to alert swimming pool owners to the possibility of a submerged large body, such as a child or pet. The device installs at the pool edge, with a hydrophone protruding under the water. It uses proprietary DSP algorithms to analyze the pool and differentiate between the routine sounds of the pump, cleaning equipment, rain, debris, and an actual intrusion of concern. It transmits information wirelessly to a monitor inside the home, showing status and emitting an alarm on a detected intrusion.

Figure 7 Eleksen, www.fabrickeyboard.com, displayed their Bluetooth keyboard (Figure 8) composed of fabric. Intended to be portable or designed directly into clothing or other applications where flexibility is needed, it offers a full-size keyboard where a rigid design would probably not fit.

GameRunner, www.fpgamerunner.com, showed their in- novative controller for video games, a treadmill with game controls mounted on a set of handlebars. It breaks the notion that the game experience requires being seated Figure 8 for hours, and offers quite an experience for first-person gaming. The game character walks when the user walks on the treadmill, and runs faster as the user picks up speed.

Realm Systems, www.realmsys.com, showed their iDentity Platform with two key elements, the iD3 Personal Server and the iD1200 Management Router. The iDentity Platform enables a robust, secure VPN to be created. Using a fingerprint sensor from AuthenTec, www.authentec.com, the iD3 acts as a possession token to provide two-factor authentication with the user’s fingerprint. The iD3 connects to a host PC on a USB port, and then uses SSL to establish secure communication with the iD1200, which enforces user- and group-based policies. With a 400 MHz PowerPC processor, up to 128 MB RAM and 2 GB of storage, an RFID chip, and Bluetooth, the iD3 provides functions such as encrypted file storage and traceless computing using no application and leaving no data on the PC host.

Finally, one of the last, more interesting stops we made was at the OtterBox, www.otterbox.com, booth. OtterBox manufactures a broad line of waterproof, crushproof, drop-proof cases and accessories for electronic devices. Rated to MIL-STD-810F and made from high-impact polycarbonates and rubber overmolding with compound latching, they transform an ordinary device into a rugged one quickly and easily. OtterBoxes, shown in Figure 9, also offer clear screen membranes, access to device interfaces, and a range of accessories to enhance the user’s rugged device experience while still protecting it. By putting your device in one of these boxes, you gain a tremendous amount of environment and shock protection at a fraction of the cost of a fully rugged system. We could hardly wait to try one of these on the next camping trip. Figure 9 Changing our way of life RSC# 21 @ www.embedded-computing.com/rsc The range of consumer electronics devices available today is really impressive. Though disappointed that more home appliances with embedded electronics weren’t featured at CES, as it was mostly a multimedia, home entertainment event, we observed how electronics are showing up in everything from the clothes we wear to the tools we use throughout the day. Many devices are gaining intelligence in ways invisible to the user. The human interface is becoming more natural. As usefulness increases, these devices are becoming part of our way of life. There is still a long way to go, but the signs are clearly visible in this wave of consumer electronics.

Embedded Computing Design April 2006 / 21 RSC# 22 @ www.embedded-computing.com/rsc By Srirama Chandra

n a large factory floor, several types of real-world signals that Types of communication networks include Ethernet, wireless link, and fiber optic represent various parameters, for example, temperature, link. The type of communication network depends on the rate of data collection, the Opressure, and voltage, from different locations may be environment, allowable measurement, and control latency. monitored, logged, processed, and controlled. In such cases, a Not only must the client DAQ system distributed data acquisition systems network is used. In a distributed accommodate different communication interfaces, it also must be able to acquire data acquisition system, a centralized server communicates with and measure different sets of real-world signals. Srirama examines some of the client Data Acquisition (DAQ) systems and logs all the acquired issues involved in designing such client DAQ systems and then proposes a stan- data at a centralized location for further analysis. dard architecture for a low-cost client DAQ system that can easily be customized The central system communicates on-site. with the client DAQ systems Introduction Interfacing with different types of networks through a communication and measuring different types of real- world signals must be considered when network (Figure 1). designing client DAQ systems, which, with all of the options, is no easy task. Plus, the ability to make modifications on-the-fly as the needs change would be beneficial.

Interfacing with different types of networks Most distributed systems are installed with several issues in mind, including expected traffic, expandability, type of environment, security, robustness, fail-safe operation, interoperability, and interference immu- nity. Some of the types of networks are: Ethernet, fieldbus (for example, RS-485), and wireless (IEEE 802.11b, 802.15.1, 802.15.4, and so on). Each type of network has associated advantages, in fact, so much so that no single network type can satisfy all of the monitoring requirements. Figure 1 Additionally, networks need support for

Embedded Computing Design April 2006 / 23 both revolutionary and evolutionary infra- digital signals. The analog signals are process actuators, and other devices re- structures. The approach taken is a hybrid- generated by sensors or transducers that quiring an analog driving voltage. This is networking environment in which there convert temperature, pressure, sound, or achieved with the use of Digital to Analog are several types of networks on a factory light into voltage. The electronic sampling Converters (DACs). Many data acquisition floor. of analog signals is called Analog to boards have both ADCs and DACs. Digital Conversion (ADC). The digital The client DAQ system must be capable output from the ADC should then be Client DAQs should also provide Digital of interfacing with multiple types of net- further processed or stored. Some signals I/O (DIO) lines to operate relays, measure works. If a process moves from one net- can be generated from high-speed real- the speed of a fan-through tachometer, work domain to another, the client DAQ world signals (for example, vibration and turn a system on or off. Typically, di- system must be able to move with it. measurement) and some from much lower gital signal monitoring requires timers, speed signals (for example, power supply counters, and frequency measurements. Measuring different types of voltage measurement). The digital control signals should be able real-world signals to perform frequency generation and pulse- Client DAQ systems should be able to Some applications will require client DAQ width modulation, among other functions. interface with different types of real-world systems to generate analog voltages to signals that are represented by analog or drive chart recorders, audio amplifiers, A client DAQ system should be able to interface with any combination of real-world signals. Further, the system also should be able to perform some of the signal processing function before transmitting to the central station for further analysis. The DIO systems also require timers and counters.

An on-site, customizable client DAQ system The client DAQ system should not only accommodate any of the standard interfaces on the network side, but also any combination of data acquisition and control interfaces to real-world signals. This requires that the client DAQ hardware provide all types of network interfaces as well as hardware support for processing all types of acquisition interfaces. Not surprisingly, such a system will be very expensive because it needs all types of network interfaces and data acquisition interfaces. However, only a small subset of its functionality will be used at any installation location.

To reduce the cost of hardware, the proposed client DAQ architecture uses a standard base system that can be customized depending on the installation location. Simply plugging in the network interface module can customize the network side of the client DAQ system. Plugging in the required set of data acquisition interface modules customizes the data acquisition section of this module. Implementing all of the required interface and processing logic within the base module reduces the cost of these modules. To optimize the cost of the base module, it is customized with only the required processing and interfacing logic necessary for the installed configuration.

The base architecture, once customized with the necessary plug-in modules both on the networking and data acquisition side, communicates with the main central server and downloads the required logic RSC# 24 @ www.embedded-computing.com/rsc for communication module interface,

24 / April 2006 Embedded Computing Design data acquisition module interface, and the client DAQ system has two modes of corresponding processing algorithms. A client DAQ system operation, the preconfiguration mode and postconfiguration mode. The LatticeXP One possible on-site, customizable client nonvolatile FPGA and the LatticeMICO8 DAQ system architecture uses nonvolatile should be able to (see Figure 2) soft processor core are used FPGAs with a soft processor core. To as an example. better understand this architecture, a interface with any brief description of the technologies used In the preconfiguration mode, the base follows. combination of real- client DAQ system will have only the logic required to detect the networking and data In-system upgradeable world signals. acquisition modules. nonvolatile FPGA Most FPGAs require an external non- In the postconfiguration mode the client the SRAM with minimum disruption to volatile memory device to store the device DAQ system is equipped with all of the system operation. configuration. After power-on, the FPGA required data acquisition interface modules configures itself by downloading the con- and the network interface modules plug- figuration from the external memory Microcontroller soft core ged in. Additionally, in this mode, the base device. Often the external memory de- A microcontroller in the FPGA at the module logic has all the necessary inter- vice is serial, and it may take an FPGA client DAQ provides the ability to process facing and processing logic. hundreds of milliseconds to download the and analyze data near the collection configuration. point before passing on to the network. The transition from the preconfiguration A microcontroller dedicated to each DAQ and postconfiguration modes, also refer- SRAM with on-chip embedded flash function allows the use of a simple and red to as commissioning, is achieved as technology provides an advantage over low-cost 8-bit solution. An open IP core follows: the traditional FPGA in that it can be re- license, which applies many of the concepts 1. Plug in all necessary networking and configured in microseconds from its of the successful open source movement to data acquisition modules to the pre- on-chip flash memory, as opposed to programmable logic applications, makes configured base module. a traditional FPGA taking hundreds of it even easier to develop appropriate 2. The system is connected to the net- milliseconds for reconfiguration. In ad- algorithms. work and is powered on. dition, once the FPGA is operational 3. The onboard DSP processor commu- using the configuration stored in SRAM Client DAQ description nicates with the main central server memory, the flash configuration can be To facilitate customization on both the through the plugged-in network updated with a new configuration. This networking and the data acquisition module and sends the configured new configuration can be uploaded into sides, the proposed architecture for the DAQ module information. 4. The main central server then sends the entire configuration for the nonvolatile FPGA required for operating with the plugged modules and the configuration-specific DSP processing algorithm. 5. The client DAQ system then updates the FPGA code and the flash memory with the newly downloaded codes. 6. The client DAQ system is now ready to perform the data acquisition operation with the site-specific networking as well as the data acquisition interfaces and is in postconfiguration mode.

Before changing either the networking interface or the data acquisition interface of the postconfigured client DAQ system, it should be decommissioned to preconfiguration mode. The decommissioning process is initiated from the server. During the decommissioning process, both the preconfiguration FPGA code and the preconfiguration DSP processing algorithm are downloaded through the networking interface. The client DAQ system then reprograms the FPGA as well as the flash memory with the newly downloaded code to get back into the preconfiguration mode. Once in the preconfigured mode, both the networking interface as well as the data acquisition Figure 2 interface can be changed.

Embedded Computing Design April 2006 / 25 Client DAQ system in Configuring the client DAQ system With the new code in both the flash preconfigured mode in preconfiguration mode memory as well as in the FPGA nonvolatile Figure 3 shows the block diagram of the The first step in installing a client DAQ configuration store, the client DAQ system is now ready to perform the actual site- proposed client DAQ system architecture system is to plug in the necessary net- specific data acquisition task. in the preconfigured mode. working module as well as the site- specific data acquisition modules. After Postconfiguration mode The system is divided into three sections: all the modules are plugged in, the system On-site customizable communication in- is turned on and connected to the network. Figure 4 shows the postconfigured client terface, common base module, and on-site The DSP processor first starts to execute DAQ system, which has the following modules plugged in: customizable data acquisition and control from the flash memory. The contents of interface. the flash memory are then transferred into the DDR memory through the processor  10/100 Ethernet interface communication module The common base module section is interface section of the FPGA, and from  Slow ADC and DAC module equipped with a socket for the network then on the processor executes from the DDR memory, freeing the flash memory  Digital relays/FET control module module, as well as multiple sockets for  Fast ADC interface module data acquisition interface. The start-up pro- for updating. The processor then detects the plugged-in communication module gram is stored in the flash memory. The As noted previously, the LatticeXP FPGA as well as the DAQ modules, and sends Lattice Power Manager IC performs the logic in the postconfiguration mode de- a message to the server or the main sequencing, reset generation, and super- pends on the network interface as well controller through the network interface visory functions. The Lattice ispClock as the installed data acquisition modules. about the configured status of the client chip provides all the clocks required by There is a one-to-one relationship between the board. The LatticeXP FPGA in the DAQ module. the networking module interface and the preconfigured mode is programmed with associated logic within the FPGA. But, the following subfunctions: The main controller then downloads both the logic specific to a data acquisition the site-specific processor algorithm as module is realized by the use of the stan-  Interfaces to all types of networking well as the site-specific FPGA configura- dard LatticeMICO8 functional block, modules tion through the communication network. and the associated processing function is  Processor bus interface The downloaded DSP algorithm is then implemented using the execution code  Flash and DDR memory interface programmed directly into the flash loaded into the on-chip embedded RAM.  DAQ module detection hardware memory. Because the LatticeXP FPGA For every data acquisition module, a copy operates from its SRAM configuration of LatticeMICO8 core is instantiated The DSP processor code in the flash memory, its nonvolatile configuration within the LatticeXP FPGA fabric. The memory enables plug-in module detection memory is free for updating while the implementation logic between individual and communication with the central server FPGA is functioning. The DSP processor types of DAQ blocks differs only in the system over any of the communication then reprograms the nonvolatile on-chip executable code loaded into the on-chip interfaces. FPGA configuration memory. Embedded RAM.

Figure 3

26 / April 2006 Embedded Computing Design Figure 4

RSC# 27 @ www.embedded-computing.com/rsc

Embedded Computing Design April 2006 / 27 SID e b A R Functional blocks of the LatticeXP FPGA

 The 10/100 Ethernet interface: This functional block performs  LatticeMICO8 + slow ADC/DAC interface: This is one of the all of the Media Access Control (MAC) layer functions and enables instantiations of the LatticeMICO8 soft processor with its algorithm the client DAQ system to communicate with the central server to periodically acquire the code from the ADC, and to perform system. preprocessing operations on each of the acquired samples such as  DDR memory interface: This drives the DDR memory and provides offset shifting. The LatticeMICO8 processor also compares the input simple memory interface structure to the rest of the blocks. voltage level with a preset level and interrupts the processor if the  Processor interface: This handles all of the DSP processor bus input level exceeds the threshold level. Otherwise, it simply logs the interface state machine logic and maps execution and data voltage value in a prefixed location in the memory using the DMA memory into DDR. block. If there is a command from the DSP processor, it picks the  DMA controller: This is a multichannel DMA controller with a data from the external memory using the DMA and sends the data channel dedicated to transferring data to and from the DDR to the DAC. memory and the networking interface, each of the data acquisition  LatticeMICO8 + timers and counters: The LatticeMICO8 performs module interfaces, and the DSP processor interface. the counter and timer function as determined by the logic interface  LatticeMICO8 instantiation per DAQ module: For every DAQ function of the digital and other I/O module DAQ. module plugged in, a copy of LatticeMICO8 and its executable  LatticeMICO8 + fast ADC interface: This module is coded such that code are instantiated within the FPGA. Each of the instantiations the data from the ADC is sent directly from the DAQ interface to the differs only in the processing algorithm loaded into the embedded DDR memory using the DMA controller. Once the data transfer is memory of the LatticeXP FPGA. The maximum number of DAQ complete, the DSP processor is interrupted with information about modules supported determines the size of the FPGA selected. the status of the transfer and the memory block location to which the The data to and from each of the LatticeMICO8 processors and ADC data is transferred. The DSP processor performs all the signal the memory is handled through the DMA controller that is also processing functions directly in the memory, builds the packet, and instantiated on the FPGA. A description of the algorithm loaded transmits it to the main processor. into the FPGA’s embedded memory block corresponding to each of the LatticeMICO8 follows. The flash memory consists of the algorithm specific to the configuration.

The LatticeXP FPGA is now configured enables the module-specific algorithm In conclusion, a low-cost nonvolatile with the following function blocks: implementation without having to refit FPGA such as the LatticeXP used in con- the logic within the FPGA. Because cert with an open source code soft pro-  10/100 Ethernet interface the LatticeMICO8 occupies very few cessor such as the LatticeMICO8 enable  DDR memory interface LUTs (200), multiple instantiation of the the implementation of a lowest-cost solu-  Processor interface LatticeMICO8 does not require a large tion client DAQ system that can be used  DMA controller FPGA. Additionally, the LatticeXP FPGA as a standard solution in a distributed data  One instantiation of LatticeMICO8 family offers one of the most economical acquisition system. per DAQ module solutions at any given FPGA size. All these factors contribute to reducing the Srirama Chandra is Decommissioning cost of the implementation. the marketing manager If the equipment needs to be brought back for the in-system This architecture enables a single base to preconfiguration status, it can be init- programmable mixed- module to interface not only with different signal products at iated directly from the central station. For DAQ modules, but also with different net- Lattice Semiconductor this, both the flash memory contents as works through on-site customization of the Corp. Prior to joining well as the LatticeXP FPGA configura- entire system. Because the same hardware Lattice, Srirama tion are changed to preconfiguration code board is used across all locations, process worked for Vantis using the onboard DSP processor. managers can standardize their entire dis- and AMD in sales and applications tributed data acquisition system using and previously was a telecom design Once the programming is complete, the these modules. engineer with Indian Telephone client DAQ system can be removed from Industries. Chandra received his MS the network and used anywhere. The throughput of the system is increas- degree in Electrical Engineering from ed because the LatticeMICO8 processors Indian Institute of Technology, Madras. Summary offload the main DSP processor from all Because the on-site specific configuration the slow peripheral operations as well as To learn more, contact Srirama at: and not a superset of all possible con- manage the data transfer buffer memory Lattice Semiconductor Corp. figurations determines the size of the management. The processor just has to LatticeXP FPGA, the size of the FPGA perform the communication and fast ADC 5555 N.E. Moore Court • Hillsboro, OR 97124 is small. The LatticeMICO8 provides an data processing functions. Consequently, a Tel: 503-268-8634 • Fax: 503-268-8347 easy method to implement the module- slower, less expensive DSP processor will E-mail: [email protected] specific algorithm using software. This be satisfactory for a given function. Website: www.latticesemi.com

28 / April 2006 Embedded Computing Design RSC# 29 @ www.embedded-computing.com/rsc Image fusion: Shared memory supports flexible, multiple sensor imaging systems e now have the ability to focus multiple sensors on an object and view that object from different perspectives. A system that uses sensors sensitive to different wave- By Ralph Barrera Wlengths, for example, combining a visible spectrum sensor with an infrared sensor, adds more information, such as the thermal signature of the object. Today, demand for high-definition images The use of multiple sensors for imaging adds to system com- is growing rapidly. Unfortunately, simply plexity. The problem then becomes how to acquire data from multiple high-speed sensors, combine or fuse the acquired displaying more pixels per frame or trans- data in meaningful ways, and present the final image to a user. Today, some available systems do image fusion, but they tend to mitting frames at a higher rate can’t always be solutions for a set application with little flexibility or growth capability. A better approach is to use a shared memory-based satisfy the need for higher-definition images. system architecture for image fusion. The use of shared memory enables a system designer to build an image fusion system that can In many cases improving the actual infor- accommodate multiple types of sensors and processing elements while providing an easy growth path when additional sensors or mation content of the image being viewed viewers are required. For example, using shared memory, a system that starts with two sensors (visual and infrared) can easily grow would help. To accomplish this, a number when another modality becomes available.

of algorithms have been developed to high- In most systems, data from only two sensors would be combined light or accent an image by detecting its at any given time. But, some cases necessitate having more than two sensors available. Also, occasions may arise when the image edges or to adjust its colors or shades. While from a visible spectrum camera would be fused with the image from an infrared sensor. As conditions between the sensor and these techniques have greatly increased the the object of interest change it might also be desirable to replace the visible spectrum camera with one that operates in a low-light amount of information being displayed, the environment. There are other applications when the selection of sensors would involve visible light, x-ray, ultrasound, and the need for improvements in image information images from an MRI, CAT, or PET scan. A typical system with both multiple sensors and image viewers is shown in Figure 1. continues to grow. One approach involves The use of shared memory technology allows multiple sensors using shared memory to facilitate images to be connected to the network and called upon as the situation warrants. Shared memory is dual-port memory that appears on the derived from multiple sensors. host bus as additional host memory. The host reads and writes data through one port while the network writes data to memory through

30 / April 2006 Embedded Computing Design to another image without impacting the other monitors. To display an image, the monitor references the partition in memory containing the image desired. Given the nature of a shared memory network, all data is broadcast around the network ring. This means that the data is present within each node simultaneously and all of the time. To present a new image the monitor only needs to display a different section of the shared memory. No additional network transmissions are required.

Shared memory also provides a benefit to the data archival system. With all data present in the archival node’s shared memory, both the raw data and the fused data can be stored for future retrieval and analysis. The entire scenario can be replayed with either the same merged images or a new set. This enables the raw data to be retrieved multiple times without rerunning the procedure. In medical applications this means a new analysis can be made without inconveniencing the patient. In military applications it supports analysis without the risk associated with redoing the mission. Figure 1 For a shared memory network to perform a second port. Data written to memory by the host is automatically multiple video image transfers properly an appropriate amount transmitted by the hardware to all nodes on the network. Insertion of bandwidth and memory size is necessary. The Curtiss-Wright and transmit/receive FIFOs buffer the data flow to avoid the Controls SCRAMNet GT200 offers an ideal platform for shared data collisions often encountered in standard networks. memory processing. The GT200 can transfer data at a rate above 210 MBps over a network. The GT200 is offered with a starting Another advantage of shared memory is that it allows sensors memory size of 128 MB of onboard shared memory. to be added without disturbing the existing network. Using this approach, each sensor is assigned its own partition of the shared During a demonstration of a video distribution system with four memory. As new sensors are added they also receive their own video sources and four monitors in May 2005 at the MEECC partition. This growth process can continue until all shared memory conference in Long Beach, California all images were displayed is used or until the throughput of the network has been exceeded. on each monitor without any frames being dropped. To test the Figure 2 shows one example of a memory assignment that would capabilities of the network an additional throughput load was support multiple sensors and processing elements, along with an added to bring the network up to approximately 90 percent of its area assigned for system coordination. capacity. The test resulted in flawless data transfers without any loss of video frames. The ability to run a fully loaded network To combine the data from the various sensors a processing ele- without data loss is critical for applications where dropped ment must be added to the network. The type of processing to data might mean bringing patients back for an additional be performed will determine medical procedure or putting combat personnel at risk to redo a the nature of the element. For mission. some applications a standard PC with an x86 processor may Ralph Barrera is product manager for be sufficient, but for high-speed the SCRAMNet Reflective Shared Memory signal processing the use of product family at Curtiss-Wright Controls a DSP or an FPGA element Embedded Computing in Dayton, Ohio. could be employed. Again, the He has been in the military and aerospace use of shared memory allows industry for more than 30 years, holding the network to grow and be positions in engineering and marketing. He easily modified to meet the received his PhD at the University of Dayton changing requirements of the and his MS and BS degrees in Electrical application. Engineering from The Ohio State University.

An image fusion system using Curtiss-Wright Controls Embedded Computing – Dayton a shared memory network can support multiple monitors that 4126 Linden Avenue • Dayton, OH 45432-3068 can be focused on the same fused Tel: 937-252-5601 • Fax: 937-252-1349 image or on different images. One monitor, for example, can E-mail: [email protected] display the raw data from a Website: www.cwcembedded.com Figure 2 single sensor and then switch

Embedded Computing Design April 2006 / 31 RSC# 32 @ www.embedded-computing.com/rsc Bringing programmability to the CE market: Winning design strategies

The Consumer Electronics (CE) market sets the pace for short windows of opportunity for market success. Getting your product out first is a must, and how successful you are will determine your company’s survival.

CE manufacturers are looking for new, flexible, low-cost, fast development solutions such as design once, build many products, which was borrowed from other engineering sectors. This solution involves creating a consumer electronics platform that can be reprogrammed for multiple finished products at multiple price points, offering a range of differentiating features and benefits, or even allowing addition of new capabilities as the market tells you what is most desired. In this article Todd discusses how you can create a winning design strategy by bringing programmability of hardware to the CE market. By Todd Scott

CE is the hottest segment in the electronic design world today. Digital televisions, portable By incorporating Programmable Logic media players, educational toys, residential security, and networking products are all Devices (PLDs) in a platform-based in a state of continual advancement. In some categories, new generations of products design, CE designers can set a clear path are introduced nearly every quarter. Windows of opportunity for market success are toward rapid, low-cost innovation. The shrinking, forcing CE developers to seek and apply new, flexible, low-cost, rapid develop- design approach can include ASICs or ment solutions. ASSPs to implement basic electronic functions, while using low-cost FPGAs, While Application-Specific Standard Product (ASSP) and Application-Specific Integrated CPLDs, or structured ASICs to add the Circuit (ASIC) logic implementations provide a low-cost, fixed platform for product latest in-demand features in a far shorter design, each has critical drawbacks. Relying on ASSPs reduces potential for differentia- time for consecutive product line releases. tion or adding the latest in-demand features, while ASIC development can significantly A PLD-based platform design strategy jeopardize on-time delivery and is notoriously expensive. Staying ahead of the design allows greater product differentiation curve requires a product development strategy that enables rapid innovation at a low cost for potentially increased margins. The to ensure a first-mover advantage. Designing one product independently from the next programmable platform can help get will not get you there. products to market first and help keep a brand in the lead. Additionally, PLDs What if a product or a whole product line could be developed rapidly while maintaining offer risk reduction. With a strategic the ability to react in weeks to customer feedback and market changes by delivering programmable design approach, modifi- differentiated feature sets ahead of the competition? What if features could be tailored cations can occur even after production based on a single basic design for multiple users, price points, or market geographies? begins.

Embedded Computing Design April 2006 / 33 PLDs are not new in CE products. They are found in some of the latest flat-panel televisions, set-top boxes, DVD recorders, personal media players, electronic educational toys, and many other consumer products worldwide. They are well suited to nearly any design where rapid response, design flexibility, and time-to-market crunches occur. Further, designing strategically with programmable logic can help companies overcome market hurdles throughout the CE product life cycle (see Figure 1). Whether at concept, emerging market, aggressive growth, or mature market stage, applying programmability to a design solves a marketability problem and accelerates product revisions and rapid, low-cost innovation from prototype through commercial availability.

Figure 1

Combine PLDs with ASICs or ASSPs to win Competitively priced, differentiated products are critical to any CE company’s survival. After a new product specification is set, ASIC development can begin. However, ASICs typically have a development cycle of one year or more. During this critical time, product requirements may vary due to changing standards, consumer demand, or competitive actions. Programmable logic provides a low-cost solution to this marketing design dilemma. PLDs can be programmed late in the development cycle without changing the basic ASIC or ASSP platform. They allow for innovation without waiting for ASIC respin cycles (see Figure 2). This helps enable product differentiation, minimize development time, reduce risk, and provide a true competitive advantage in the race for market share.

RSC# 34 @ www.embedded-computing.com/rsc Figure 2

34 / April 2006 Embedded Computing Design Being a leader in the CE market In today’s competitive marketplace, innovation, differentiation, and flexibility in product development are critical to a company’s success. The following examples illustrate this.

Emerging market The rapidly evolving home multimedia LAN market uses PLDs to meet the requirements of greater bandwidth and much higher Quality of Service (QoS). Far different from residential data LANs, home multimedia LANs need to seamlessly share real-time Audio/ Video (A/V) content. Meeting this challenge with minimal risk requires low-cost solutions that easily and quickly adapt to changing requirements and rapidly evolving standards.

A typical home multimedia LAN architecture, shown in Figure 3, is based on a central switch that directs A/V traffic to terminals in each multimedia center or device location in the home. This LAN must be highly scalable and adaptable to fit an almost endless number of implementations required in today’s homes.

Figure 3

Terminals use CPLDs to bridge older ASSPs for continual feature evolution, eliminating the need for board redesign. CPLDs also allow rapid new product introductions to maximize sales. In the switch, low-cost FPGAs provide a scalable platform enabling high-bandwidth multimedia content to be moved anywhere within a home network. This scalability allows a cost-effective range of products or product line, targeting home solutions.

Aggressive growth The HDTV market is another growth market that relies on programmable logic. For leadership in a sector experiencing growing consumer interest, company and product differentiation is essential. In the HDTV market, a range of display sizes and features provides an obvious path to establishing customer leadership perceptions. A market that is still looking for continuous product enhancements, as well as increasing retail price competition, requires a balance between low-cost standard solutions and a unique intellectual property that differentiates the products.

Low-cost PLDs and structured ASICs are used to implement features complementary to existing ASSP functionality in high-volume digital displays. PLDs also ease development

Designing strategically with programmable logic can help companies overcome market hurdles throughout the CE product life cycle. RSC# 35 @ www.embedded-computing.com/rsc

Embedded Computing Design April 2006 / 35 and feature enhancement for the newer, larger displays. Figure 4 illustrates the development range of HDTVs based on a single ASSP-based platform. Because FPGAs are available in a range of device sizes, this platform design approach uses a smaller device in a lower-end 42-inch HDTV to improve the picture quality over the ASSP-only solution. In the top-line products, such as a 60-inch display or larger, a large FPGA can significantly improve picture quality and add differentiated features such as increased input/output ports, multimedia networking, and streamlined user interfaces. A programmable platform approach provides an HDTV product line with a Figure 5 range of feature and quality requirements ahead of any ASSP roadmap and faster than competitors using an ASSP-only or 1983 1993 2003 2013 ASSP-ASIC development model.

Process Today’s PLDs – Cost effective 3 µm 0.8 µm 0.13 µm 32 nm for CE applications Technology Like most silicon solutions, the cost of Equivalent 125 14K 960K 9M PLD system implementation has rapidly ASIC Gates decreased while product functionality and complexity have dramatically increased. Transistor Ten years ago, 52 devices were required 12K 1,5M 230M 1,500M Count to create the equivalent logic density of today’s single PLD. While densities have Equivalent ASIC dramatically increased, cost is declining Gates Purchased 30 375 36K 300K by an average of 25 to 30 percent per year for $5 (see Figure 5 and Table 1). Continuous cost reduction is possible because PLDs use Table 1 the most advanced process technologies and are built to suit more customers than from others. In addition, ASSPs are seldom available for the most current functions, so just a few large-volume opportunities. CE developers must often turn to custom ASICs.

These conditions call for greater flexibility ASICs have the advantage of low per-component prices, but the long development times and agility in product development than they require run counter to the need to innovate and quickly offer distinguishing features ASSPs and ASICs provide, but relying in markets saturated with similar products or that are otherwise changing. The high on ASSPs exclusively does not allow de- nonrecurring engineering costs needed for custom ASICs are also a significant barrier for velopers to differentiate their products developers. As a result, CE developers are increasingly turning to low-cost PLDs.

CE product developers can take advantage of low-cost ASSPs for well-established functions, while relying on programmable logic to deliver the differentiating capabilities of their product. The time required to configure the FPGA is in milliseconds and goes unnoticed by the user. Resulting FPGA designs use fewer logic resources by nearly one-third, the cost of which are only about one-fifth of the typical total bill of materials, and take advantage of FPGA reconfigurability. Additionally, the use of FPGAs and ASSPs reduces manufacturing costs by reducing the number of required components resulting in smaller board sizes.

Many companies have evaluated the alternatives and concluded that no other logic component solution achieves either Figure 4 their cost targets or meets their aggressive

36 / April 2006 Embedded Computing Design development schedules better than an FPGA-based design.

The consumer electronics market is forcing product developers to reevaluate existing development models. The traditional methods of relying on ASSPs or custom ASICs to achieve the lowest costs are proving inadequate to the demands for rapid innovation and increased product differentiation. Product developers now can turn to low-cost programmable logic-based solutions, allowing them to respond to rapidly changing needs of consumers. Continuous innovation and design enhancements will continue this trend. CE designs not only can afford the programmable approach, but also demand it.

Todd Scott is senior director for Altera’s broadcast and consumer business unit in San Jose, California, where he manages a marketing and engineering team addressing these two fast-growth business sectors. He has been with Altera for nearly five years, and has served as marketing director with Lattice Semiconductor and held other marketing and engineering roles with LSI Logic and Raytheon Semiconductor. Todd graduated from Cal Poly with a degree in Electronic Engineering augmented with numerous management and marketing postgraduate courses.

For more information, contact Todd at:

Altera 101 Innovation Drive San Jose, CA 95134 Tel: 408-544-7768 • Fax: 408-544-8066 E-mail: [email protected] Website: www.altera.com/end-markets/ consumer/csm-index.html

RSC# 37 @ www.embedded-computing.com/rsc

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RSC# 38 @ www.embedded-computing.com/rsc By Sean Riley

ecoding a digital video stream is a compute-intensive process necessary in a wide variety of applications from set-top boxes to multiscreen security and surveillance. Whether the encoded bitstream is MPEG2, MPEG4, H.264, JPEG2000, or some other variant, the incoming pixel rate can be quite large. Sometimes these obstacles can be overcome with dedicated video decoding hardware, but what happens when the decoder needs to handle more than one type of encoding scheme? DDCompounding the problem, the image resolution often will vary between standard definition and high definition. Add to this the requirement of decoding multiple streams at once, and it becomes apparent that many hardware architectures are not up to the job.

Luckily, reconfigurable silicon architectures including FPGAs, CLPDs, ASSPs, and now a new class of devices, Field Programmable Object Arrays (FPOAs), are ready to meet this challenge. Sean will discuss what FPOAs, which are high-performance programmable logic devices that are programmed at the object level instead of the gate level, have to offer the industry.

The Moving Picture Experts Group defined the MPEG2 standard as a method Proﬁ les of compressing video and audio data for transmission across a variety of mediums. Simple Main SNR Spatial High The bandwidth available for each of these High X X transmission methods varies greatly, so the MPEG2 standard was designed with High-1440 X X X a wide range of video quality options. These options include resolution of the Main X X X X Levels image being captured, the frame rate, the Low X X compression of the color components of the video, and the ability to encode the motion of objects within the video over time. In Table 1 addition, the MPEG2 specification allows an MPEG2 encoder leeway in dropping high-frequency components of the video image without sacrificing the quality of Obviously, several multichannel video Accumulator (MAC), or Register File the video as seen by a human viewer. streams may need to be decoded in a (RF), and can be interconnected with a typical multimedia decoder. The inherent synchronous, 1 GHz programmable con- The capabilities are grouped into Levels flexibility of MPEG2 forces this require- nection. and Profiles, as shown in Table 1. Gen- ment on anyone developing a playback erally, levels refer to screen resolution and device. In this implementation, the FPOA is pro- profiles refer to video quality level. Of grammed to accept multichannel MPEG2 particular interest here are Main Profile The FPOA architecture can be used as video data streams, separate them from at Main Level, MP@ML, or commonly a very high-performance, reconfigurable, each other, decompress the compressed called standard definition, and Main Profile multistream video codec. Because FPOAs bitstream, transform the image from its at High Level, MP@HL, commonly called are programmed at the object level encoded form through an Inverse Discrete high definition. Because of the flexibility instead of the gate level, they do not Cosine Transform (IDCT), scale the video of the MPEG2 standard, it is widely require a lengthy timing closure as in as necessary, and send the reconstructed adopted as the standard for DVD players other architectures. An object can be an video streams out to external display in a large portion of the world. Arithmetic Logic Unit (ALU), Multiply drivers.

Embedded Computing Design April 2006 / 39 by Motion Vector and blends them back into the 8 x 8 blocks coming out of the IDCT. The Video Scaler performs video scaling and other video postprocessing. The rest of the modules manage various I/O and memory resources internal and external to the FPOA. Because the FPOA is operating at 528 MHz, roughly half its peak operating frequency, it has headroom to support more than four channels or faster video bit rates.

The MOA1400D FPOA from MathStar, pictured in Figure 2, supports 400 ALU, MAC, and RF objects, and can be clocked at operating frequencies of 1 GHz, making it an ideal engine to run a wide variety of decoders including MPEG2, MPEG4, H.264, and JPEG2000, depending on the specific parameters of their decoding algorithms. The MOA1400D is reconfigurable, so updates can be made to the application in the field.

Figure 1

Figure 1 outlines this particular imple- information to be compressed into a mentation of an MPEG2 decoder. This smaller bitstream than simply compressing decoder can process four independent the raw video frame by frame. In parallel, channels of MPEG2 standard definition the Run-Length Expander rebuilds the (MP@ML) or one channel of MPEG2 correct order of 8 x 8 blocks of pixels. high definition in 4:2:0 (MP@HL) or The MPEG2 encoder further compresses 4:2:2 (HP@ML) format. For purposes of information by rounding pixel values to this discussion, standard definition is as- discrete numbers through a process called sumed to be 720 x 480 resolution video and quantization. Inverse Quantization (IQ) high definition is assumed to be 1920 x reverses this process. 1080 resolution video. The device can be reconfigured in milliseconds to perform The IDCT performs an inverse discrete Figure 2 either task. cosine transform on each 8 x 8 block of pixels, changing the values from 2D Sean Riley joined The Host Interface connects the FPOA frequency domain back into the spa- MathStar as vice with an external host via a Local Bus tial domain. The Motion Compensation president of marketing with a raw data rate of 2.5 Gbps. The module rebuilds each motion-compensated in April 2005. He is compressed video streams are received block from the reference block pointed to responsible for the by the FPOA on this interface and pass- planning, definition, ed to the Video Buffer Verifier (VBV) positioning, and mar- Controller. The VBV Controller manages keting of MathStar’s the multichannel video frame storage in The MPEG2 encoder FPOA product line. memory and flags the channel change on Sean joined MathStar frame boundaries. The Header Parser and further compresses from Intel Corporation where he spent 13 Control performs any necessary bitstream years in various marketing, engineering, parsing of the encoded video data. The and general management roles. Variable Length Decoder (VLD) culls information by rounding information from the video data based on To learn more, contact Sean at: lookups in the following six tables: macro block type, macro block address increment, pixel values to discrete motion vector, coded block pattern, DC MathStar coefficient, and AC coefficient. 19075 N.W. Tanasbourne Drive numbers through Suite 200 The Motion Vector module determines if Hillsboro, OR 97124 the encoder did any motion estimation; if so, it rebuilds the encoded motion a process called Tel: 503-726-5500 vector and calculates the address of the E-mail: [email protected] appropriate reference macro block. This Website: www.mathstar.com is a special feature of MPEG2 that allows quantization.

40 / April 2006 Embedded Computing Design ASIC IP Cores DevicesASIC IP Cores Company name/ Company name/ ASIC ASIC FPGA Model number FPGA Model number Comm Structured ASIC Comm DSP Security SoC Comm Structured ASIC Comm DSP Security SoC

4DSP www.4dsp.com Lattice Semiconductor www.latticesemi.com

Floating Point FFT Core • • LatticeSC •

Polyphase Filterbank • LatticeECP •

Wideband Digital Down Converter • LatticeXP •

Actel www.actel.com ispLeverCORE • • •

ProASIC PLUS • LSI Logic www.lsilogic.com

ProASIC3 • ZSPxxx •

Altera www.altera.com VisionSpectrum •

Cyclone II • RapidChip Xtreme2 •

HardCopy II • RapidChip Integrator2 •

Stratix II • CoreWare •

Stratix II GX • MathStar www.mathstar.com

AMIRIX Systems www.amirix.com SOA13D40 FPOA •

Ethernet • MIPS Technologies www.mips.com

Aspex Semiconductor www.aspex-semi.com Pro Series •

Linedancer • MIPS32 4Kc/4KEc • • •

Atmel www.atmel.com MIPS32 24K •

AT40K • MIPS64 •

ATCxx • QinetiQ www.qinetiq.com

Cambridge Consultants www.cambridgeconsultants.com Quixilica Floating Point •

XAP3 Core • Quixilica Floating-Point QR Processor Core •

ChipX www.chipx.com QuickLogic www.quicklogic.com

CX Family • PolarPro •

Comtech AHA www.aha.com RF Engines www.rfengines.com

AHA4541 • DSP Cores for FPGA •

CPU Technology www.cputech.com XILINX www.xilinx.com

Quintillium Family • Endpoint LogiCORE •

DSP Top www.dsptop.com VIRTEX-4 FX60 •

Digital Filters • VIRTEX-4 •

Infineon Technologies www.infineon.com Spartan •

TC1100 •

Embedded Computing Design April 2006 / 41 Avoiding unexpected challenges in PCI Express core integration

By Tony Sousek and Nick Sgoupis

s a fast, versatile, and popular interface, PCI Express (PCIe) is a natural candidate for development Aas an IP core for easy reuse. However, more than conformance to the PCIe specification is required to make such a core a success for designers hoping to minimize how much PCIe technical detail they need to understand. With this in mind, Tony and Nick evaluate three approaches to PCI core integration.

PCIe integration challenges Any endpoint controller core implementing the PCIe standard leaves many worries for designers integrating that core into their system. Specifically, a core that stops at providing a Transaction Layer Packet (TLP) interface might meet the specification, but designers will be left on their own when it comes to handling and processing transaction requests and generating or processing transaction completions. So much detailed PCIe understanding is required to do this successfully that the designer starts to lose the benefits of using a prebuilt core.

A successful TLP interface must perform several tasks within specific constraints for both incoming and outgoing requests, and potentially involves multiple elements in the designer’s application System-on-Chip (SoC). Figure 1 shows a typical system design, with the elements potentially re- quiring special considerations for correct PCIe operation listed in red.

For incoming requests, completion packets must be formed with respect to the max_payload and read completion boundary settings defined in the PCIe configuration space. This means that read requests bigger than the max_payload must be answered by several packets, and all the packets except the last must end at the read completion boundary.

All fields in the completion TLP must be correctly encoded, with each packet having the correct value in its lower address and byte count fields, as well as having the proper completion status.

Additional stipulations include:

 Writes to the I/O space require completion, while writes to the memory space do not.  The completion address in a RSC# 42 @ www.embedded-computing.com/rsc completion packet differs with the

42 / April 2006 Embedded Computing Design type of request; the lower address of I/O requests is set to 0, while that of memory requests depends on the starting address of the current completion packet.  Applications need to correctly report to the core their problems, such as a local memory write error or a local peripheral read/write error, and return a completion error status in response to the nonposted requests.

On the outgoing requests side, similar detailed challenges are normally left to the PCIe core integrator for both forming requests correctly and processing completions within tight timing and memory address constraints.

In forming outgoing requests, it is essential they not cross the 4 kB boundary, and nonposted requests must be identified by a unique tag. The size of read requests is Figure 1 restricted by the max_read_request_size parameter stored in the configuration space in the device control register. Write requests are similarly restricted by the max_payload parameter.

Any violations of the packet forming rules result in the request packet being discarded and an error being detected at the receiver, causing a system malfunction.

Completion processing for outgoing requests also takes close attention. Each completion must be processed by the order of its tag, but it is difficult to ensure that multiple outstanding completions are processed in the correct order. The designer must define an appropriate completion time-out limit, which must be greater than 50 µs and less than or equal to 50 ms; the Figure 2 minimum recommended is 10 ms. Packets have to arrive for completion in the correct order, that is, the completion values in the lower addresses for multiple completion TLPs must be correct. In addition, both unsupported request and completer abort responses from the completer must be processed.

Ways to make integration easier Among the approaches to making PCI core integration easier, three stand out:

1. Providing detailed examples 2. Developing an efficient proprietary interface 3. Creating an application interface layer for standard SoC buses

Through example As suggested by the Quality for IP Metric from the VSI Alliance, www.vsia.org, the deliverables of every core should include Figure 3

Embedded Computing Design April 2006 / 43 well-documented examples. It would be possible to include with the PCIe core a well- Through an AIF and standard buses structured set of effectively designed and explained example implementations to illustrate An AIF subsystem as in the previous ways to handle the technical challenges mentioned. approach but designed to work with industry-standard SoC buses, such as the Unfortunately, relying solely on examples still leaves designers needing to understand Open Core Protocol specification, www. PCIe spec details, and merely provides a set of partial blocks they must still customize for ocpip.org, or the OpenCores Organization their own system. Moreover, this approach does little to help designers verify the complete Wishbone specification, www.opencores. system, including all the TLP processing. com, rather than a proprietary bus offers the best solution for core users. In addition Through a proprietary interface to using off-the-shelf verification for One might design an effective and efficient subsystem for processing incoming requests the PCIe core itself, there may also be (a completion controller) and DMA channels able to generate outgoing requests and available verification IP for the selected process their completions. Such a subsystem could indeed isolate designers from the standard SoC bus, significantly reducing PCIe spec TLP details, but then designers must still understand the subsystem’s pro- the verification burden. Moreover, because prietary interface, and handle verification of the system, including this interface, on their it is likely that the designer already knows own. Figure 2 (page 43) depicts a typical SoC architecture using an Application Interface his or her standard SoC bus, working with (AIF) with the PCIe core. a well-designed PCIe application interface for that bus should be straightforward.

Implementing the AIF approach Though it requires the most work of the three approaches, using an AIF block for the PCIe endpoint controller core should be seriously considered. The AIF bridges the TLP interface and any of several industry-standard SoC bus interfaces, handling all the standard data transfers as well as the more esoteric exceptions and possible error conditions (see Figure 3 page 43).

The AIF sits between the Endpoint Controller core and the system into which the core is being integrated. On the core side, the AIF implements a complete TLP interface, handling all the low-level details mentioned previously.

On the system side, the AIF has a flexible architecture designed for easy adapta- tion to any of several industry-standard SoC bus specifications, such as OCP, Wish- bone, ARM’s AMBA, www.arm.com, or IBM’s CoreConnect, www-03.ibm.com/ chips/products/coreconnect/. It includes:

 A Completion Controller with queu- ed request processing that allows simultaneous processing of up to two requests  A DMA core with up to eight DMA channels  An optional Message Controller, which is planned for future release

CAST, Inc. has a PCIe endpoint controller core compliant with PCIe base specification 1.0a, including the transaction, data link, and physical protocol layers.

The scalable and flexible core has a modu- lar architecture and a high-performance, low-latency design. It supports multiple device link widths to better match the bandwidth needs of specific applications, RSC# 44 @ www.embedded-computing.com/rsc such as x1 or single lane and x4 or four

44 / April 2006 Embedded Computing Design lane, and offers bidirectional data rates a cofounder of CAST in 1993. In the firm’s early consulting days, he worked on antenna, from 250 MBps for x1 to 1 GBps for x4. elevator, and other systems, and has since focused on refining CAST’s development It supports most advanced PCIe capabili- environment and tool set as well as designing a variety of IP cores. He has BS and MS ties, including message signaled interrupts, degrees from Columbia University. multiple virtual channels, advanced error reporting, end-to-end cyclic redundancy To learn more, contact Tony or Nick at: check, and power management features. Multilane versions of the core support CAST, Inc. lane reversal and polarity inversion. 11 Stonewall Court • Woodcliff Lake, NJ 07677 The synchronous, latch-free core design Tel: 201-391-8300 • Fax: 201-391-8694 has an AIF layer that implements an asyn- chronous clock boundary between the core E-mail: [email protected] • E-mail: [email protected] logic and the user’s application. Standard bus interfaces such as Wishbone or AMBA Website: www.cast-inc.com are available, as is a generic interface for use with any system.

The core was rigorously verified for compliance with the PCIe specification using PureSpec PCIe verification IP and the PureSuite compliance test suite from Denali, www.denali.com. The core has been further verified by implementing it in an FPGA and using the Agilent Protocol Test Card.

A wise option Though the PCIe-EP PCIe Endpoint Controller core from CAST, Inc. is fairly new to the market, experience to date with two significant initial customers is validating the AIF approach. Both are using the AIF with a Wishbone standard interface, and their integration efforts are going smoothly.

Designers selecting a PCIe endpoint controller core would be wise to look for a capability similar to the AIF, or grapple with understanding and implementing the details of the PCIe TLP interface themselves.

Tony Sousek is a principal engineer for CAST, Inc., working in the company’s facility in Brno, Czech Republic. He has worked on medical, satellite, security, and other systems for several firms in the Czech Republic, and has performed design engineering for PCI and other interface IP for CAST since 2001. He holds an MSEE from the Technical University of Brno.

Nick Sgoupis is a senior principal engineer for CAST, Inc. working in Putnam Valley, New York. He worked on hardware modeling systems at Racal-Redac, and was RSC# 45 @ www.embedded-computing.com/rsc

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