High-Density Through Silicon Vias for 3-D Lsis

INVITED PAPER High-Density Through Silicon Vias for 3-D LSIs Silicon stacked chips that perform highly-parallel data transfer have been successfully fabricated for image processing, artificial retinas, and for microprocessor and memory testing.

By Mitsumasa Koyanagi, Fellow IEEE, Takafumi Fukushima, and Tetsu Tanaka, Member IEEE

ABSTRACT | High density through silicon via (TSV) is a key in and bonding wires in system-in-package (SiP) due to the fabricating three-dimensional (3-D) large-scale integration limited total stacked-chip thickness and the difficulty of (LSI). We have developed polycrystalline silicon (poly-Si) TSV reducingthewirebondingpitch.TheseproblemsinLSIs technology and tungsten (W)/poly-Si TSV technology for 3-D and SiP can be solved by vertically stacking several chips integration. In the poly-Si TSV formation, low-pressure chem- and connecting them with the through silicon vias (TSVs). ical vapor deposition poly-Si heavily doped with phosphorus Therefore chip stacking using the TSV has been attracting was conformally deposited into the narrow and deep trench considerable attention from many researchers in the LSI formed in a Si substrate after the surface of Si trench was device and package technology areas [1]–[13]. We can thermally oxidized. In the W/poly-Si TSV formation, tungsten easily reduce the wiring length, the pin capacitance, the was deposited into the Si trench by atomic layer deposition chip size, and the microbump pitch by employing three- method after the poly-Si deposition, where poly-Si was used as dimensional (3-D) LSIs and 3-D SiP, and consequently we a liner layer for W deposition. The 3-D microprocessor test chip, can increase the signal-processing speed and decrease the 3-D memory test chip, 3-D image sensor chip, and 3-D artificial power consumption. Three-dimensional LSIs are also retina chip were successfully fabricated by using poly-Si TSV. useful for increasing the wiring connectivity within a chip. It, therefore, becomes possible to produce new LSIs KEYWORDS | Microbump; three-dimensional (3-D) large-scale such as real-time image-processing chips, neuromorphic integration (LSI); through silicon via (TSV); wafer bonding; chips, memory-merged processor chips, and intelligent wafer thinning; 3-D system-in-package (SiP) memory chips by using 3-D LSIs [14]–[20]. In this paper, we describe a high-density TSV process technology using a polycrystalline silicon (poly-Si) TSV I. INTRODUCTION and a tungsten (W)/poly-Si TSV for the fabrication of The signal propagation delay and the power consumption 3-D LSIs. by the interconnections seriously increase as the large- scale integration (LSI) capacity and packing density increases. In addition, I/O circuits in LSI tend to consume II. FABRICATION PROCESS FOR more power to rapidly drive the output pins and the THREE-DIMENSIONAL LSI external wiring with large capacitances and inductances in We proposed a fabrication method for 3-D LSI for the first package and print circuit boards. As a result, it becomes time in 1989 in which LSI wafer is thinned from the back more and more difficult to achieve high performance and surface after bonding to the thick LSI wafer [21]–[24]. low power consumption in LSIs. Meanwhile, it also Furthermore, we proposed to use the TSV to vertically becomes difficult to increase the number of stacked chips connect many layers of 3-D LSI and developed a poly-Si TSV in 1995 [25], [26]. The cross-sectional structures of the 3-D LSI fabricated by our 3-D integration technology

Manuscript received March 24, 2008; revised July 22, 2008. are illustrated in Fig. 1(a), where the LSI wafer having Current version published February 27, 2009. TSVs is bonded face-to-face to the thick LSI wafer. The The authors are with the Department of Bioengineering and Robotics, Tohoku University, Sendai 980-8579, Japan (e-mail: [email protected]; TSVs are formed before the transistor formation in the via- [email protected]; [email protected]). first process, whereas they are formed after the transistor Digital Object Identifier: 10.1109/JPROC.2008.2007463 formation or before the multilevel metallization process in

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the metal microbump is formed on the base of the TSV, as shown in Fig. 2(c). By repeating this sequence, 3-D LSIs as shown in Fig. 1(a) can be easily fabricated. In the 3-D LSI fabrication process where the TSVs are formed from the back surface, the thick LSI wafer without the TSVs is glued face-to-face to the supporting material and then thinned from the back surface. After that, TSVs are formed from the back surface and the metal microbump is formed on thebaseoftheTSV.Byrepeatingthissequence,3-DLSIs as shown in Fig. 1(a) can be also fabricated. In this fabrication process, however, it is a key to remove the oxide at the bottom of trench before the conductive material is filled into the TSV trench. In the fabrication process of the 3-D LSI shown in Fig. 1(b), the supporting material is removed after the thinned LSI wafer with TSVs andmicrobumpsisface-upbondedtothethickLSIwafer or the stacked wafer. In either of these 3-D LSI fabrication processes, the thick LSI wafer, which acts as the supporting material, remains even after completing the 3-D LSI fabrication process. Therefore, a very wide range of thicknesses from several tens of nanometers to several tens of micrometers can be used for the thinned wafers bonded to the thick LSI wafer. The thickness of several tens of nanometers can be achieved by removing the Fig. 1. Cross-sectional structure of 3-D LSI. (a) Face-down and silicon substrate of silicon on insulator (SOI) wafer after (b) face-up stacking. bonding an SOI wafer with thin silicon body to the thick LSI wafer. the via before back end of line (BEOL) process. The TSVs are formed after the multilevel metallization process in the via after BEOL process. When the TSVs are formed before the multilevel metallization process, the metal microbumps are formed on the top surface of chip and connected with the TSVs by the multilevel metallization layers.ForthecasewhentheTSVsareformedafterthe multilevel metallization process, they have to be formed through the thick dielectric layer for multilevel metallization into the silicon substrate. It thus may be difficult to employ this method for an LSI wafer having a multilevel metallization of more than five levels; for such a case, it is recommended to form the TSVs before the multilevel metallization process or to form them from the back surface. After the TSV formation, the thick LSI wafer with the TSVs is glued face-to-face to the supporting material as shown in Fig. 2(a). Various kinds of materials can be used as the supporting material, including quartz glass, a bare silicon wafer, and an LSI wafer. The LSI wafer glued to the supporting material is thinned from the back surface by the mechanical grinding and chemical mechanical polishing (CMP)toexposethebaseoftheTSV.Thisisfollowedby the formation of metal microbumps, as shown in Fig. 2(b). The thinned LSI wafer with the supporting material is then bonded back-to-face to another thick LSI wafer having TSVs. This thick LSI wafer having TSVs is again thinned Fig. 2. Fabrication process flow for 3-D LSI in which the TSVs are from the back surface to expose the base of the TSV, and formed before wafer bonding.

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Fig. 3. SEM cross-section of poly-Si TSVs.

III. POLY-Si TSV PROCESS Poly-Si TSV is suitable for the via-first process since the process temperature for poly-Si TSV is higher than 650 C. Poly-Si TSV enables us to form high-density TSVs. Fig. 3 Fig. 4. Cross-sectional SEM of poly-Si TSV base (a) and shows a scanning electron microscope (SEM) cross-section photomicrographs of the back surface (b), (c) after the mechanical grinding and CMP. of poly-Si TSVs. In this poly-Si TSV formation, n+ poly-Si heavily doped with phosphorus was deposited into the narrow and deep trench in a silicon substrate by low- hard mask [Fig. 4(b)]. Both photoresist and Al hard mask pressure chemical vapor deposition (LPCVD) method after are removed after the In-Au deposition to obtain In-Au the surface of the Si trench was thermally oxidized. The microbumps [Fig. 4(c) and (d)]. After the formation of thickness of silicon oxide was 0.4 m. The resistivity of poly- In-Au microbumps, the thinned wafer was then aligned Si was approximately 1 m cm. As is clear in the figure, and temporarily bonded to the bottom LSI wafer. In-Au poly-Si is conformally deposited into the deep Si trench with microbumps were also formed on the front surface of the a depth of 55 m and a diameter of 2.5 m. Any voids were bottom wafer before aligning the two wafers. We have not observed in SEM observations. After filling the Si developed a new wafer aligner having an alignment trenches with poly-Si, the wafer is bonded to the supporting accuracy of 1 m for 3-D integration technology [25]. material and then thinned to approximately 30 m from the This wafer aligner can also provide a uniform force and has back surface using the mechanical grinding and CMP to expose the base of the poly-Si TSV. Fig. 4(a) shows the cross- sectional SEM of poly-Si TSV base after the mechanical grinding and CMP. Poly-Si, silicon oxide and silicon substrate were uniformly polished at the back surface and a very flat surface was obtained after the mechanical grinding and CMP. Fig. 4(b) and (c) shows the photomicrographs of the back surface after the mechanical grinding and CMP. The cross-sectional size of poly-Si TSV is 2 by 12 min Fig. 4(b) and 2 by 2 m in Fig. 4(c). The bases of poly-Si TSVs are clearly observed in the figure. It is also obvious that poly-Si and silicon oxide is not mechanically damaged. We confirmed that poly-Si TSVs are electrically well insulated by silicon oxide, as shown later [Fig. 8(a)]. After thinning the wafer, In-Au microbumps were formed on the back surface using the liftoff technique. The fabrication sequence of In-Au microbump is described in Fig. 5. Aluminum (Al) metallization is formed on the base of poly-Si TSV first. Thin W capping layer is deposited on the Al metallization. Then a polyimide is spin-coated for the planarization. After that, a photoresist is coated for the liftoff [Fig. 4(a)]. This photoresist is patterned using Al Fig. 5. Fabrication sequence of In-Au microbump.

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a function to increase the temperature during temporary wafer bonding to guarantee firm contact between the upper and lower microbumps. The In-Au microbumps and an epoxy adhesive layer are used to bond two wafers. The liquid epoxy adhesive is injected into the gap of approximately 4 m between the two wafers in a vacuum chamber after the temporary bonding of the microbumps, as shown in Fig. 6 [26]. Then, the bottom wafer was thinned again to approximately 30 m from the back surface to expose the base of the TSV. Fig. 7(a) shows an SEM cross- sectional view of In-Au microbump after the adhesive injection. The sizes of the upper and lower microbumps are 10 by 10 m and 5 by 5 m, respectively. It is clear in the figure that the upper and lower microbumps are bonded with high alignment accuracy and both microbumps partially melt. It is also obvious in the figure that the epoxy adhesive is completely injected into the narrow gap of 4 m between the upper and lower wafers. Any voids were not found in SEM observations. We also confirmed that voids did not exist by using test structures in which a quartz glass wafer with microbumps was bonded onto a silicon wafer

Fig. 7. (a) SEM cross-sectional view of In-Au microbump after the adhesive injection and (b) photomicrograph of In-Au microbumps which were formed in a logic circuit pattern.

with microbumps. Fig. 7(b) shows a photomicrograph of In-Au microbumps which were formed in a logic circuit pattern. In this figure, an In-Au microbump was formed on a pair of four poly-Si TSVs with a size of 2 by 12 mto reduce the TSV resistance. The combination of temporary wafer bonding using In- Au microbumps and epoxy adhesive injection into wafer gaps enable us to bond wafers at a lower temperature than 250 C. Other methods such as benzocyclobutene bonding, direct oxide bonding, and Cu–Cu bonding usually need a higher temperature than 350 C. Lower bonding temperature can mitigate the influences of metal impurity diffusion into the silicon substrate. In addition, our method based on temporary wafer bonding with In-Au microbumps and epoxy adhesive injection is tolerant for particles since the epoxy adhesive can be injected into the wafer gaps even though particles remain within the gaps. Therefore, higher wafer bonding yield and hence the lower cost can be expected in our method. Furthermore, Fig. 6. Process sequence of adhesive injection method. (a) Install high-density TSVs with high reliability can be realized by stacked wafers temporarily bonded by In/Au microbumps in a our 3-D integration technology based on temporary wafer vacuum chamber, (b) an injection inlet of temporarily bonded wafers is dipped into a liquid adhesive, (c) nitrogen gas is introduced into the bonding with In-Au microbumps and epoxy adhesive chamber, and (d) a liquid adhesive is injected into the gap between injection since In-Au microbumps with small sizes can be temporarily bonded wafers. completely surrounded by the epoxy adhesive underfill.

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IV. TUNGSTEN/POLY-Si TSV PROCESS AND ITS SCALING CAPABILITY It is very important to choose a suitable material for the TSVs in the 3-D integration technology. Mostly we have employed a low resistive poly-Si for the TSVs since poly-Si is a stable material and affects the device characteristics less than other materials. However, tungsten (W) or copper (Cu) are suitable for the TSV material in the case when TSVs having much lower resistances are required. Specifically, W and Cu are indispensable for scaling down thesizeoftheTSVs.Wehavealsodeveloped3-D integration technology using W/poly-Si TSVs [27], [28]. W/poly-Si TSV is suitable for the via before BEOL process. An atomic layer deposition (ALD) method was used for the W deposition. We supplied two kinds of reaction gases WF6 and SiH4, alternatively, to form W. In this case, it is very important to quickly remove unreacted gases and byproduct gases before and after the chemical reaction of suppliedgases.InourALDmethod,WF6 gasisintroduced into the ultrahigh vacuum CVD chamber first and absorbed on the surface of deep trench. Then the unadsorbed WF6 gas was evacuated. After that, SiH4 gas Fig. 8. (a) The current–voltage characteristic and the resistance of is introduced to the chamber to change WF6 to W, and the poly-Si vertical interconnection and (b) the capacitance–voltage remaining gases are vented out. The evacuation time is the and leakage current–voltage characteristics of poly-Si TSVs. key parameter in our ALD method because it determines the surface topology and step coverage of W deposited deep trench. Then we simulated the W step coverage in a However, we have to carefully select the adhesive mate- deep trench by Monte Carlo analysis. Fig. 9 shows the rial so that the mismatch in coefficient of thermal expan- W thickness and step coverage in a deep trench as a func- sion between the adhesive material and the silicon tion of a reaction gas evacuation rate. The W thickness substrate is minimized in order to avoid the wafer war- at the top position, middle position, and bottom position pages.Thenumberofwafersbondediseventuallylimited of the trench is plotted in the figure. As is clear in the by the wafer warpages. figure, the thickness differences among three positions The current-voltage characteristic and the resistance of become smaller and the step coverage improves as the poly-Si vertical interconnection for 3-D LSI are plotted in reaction gas evacuation rate increases. From these Fig. 8(a). This characteristic was measured using a daisy results, we optimized the W deposition conditions to be chain with 144 vertical interconnections which were the adsorption time of 120 s, the reduction time SiH4 of allocated to the three layers of the 3-D device test chip. A 60 s, the evacuation time after WF6 introduction of 120 s, vertical interconnection consists of poly-Si TSV and In/Au and evacuation time after SiH4 introduction of 60 s at the microbump. Four poly-Si TSVs with a size of 2 mby12m are connected in parallel in one vertical interconnection. As is obvious in the figure, a linear current–voltage characteristic was obtained. From this characteristic we obtained the resistance value of approximately 10 for one vertical interconnection with four poly-Si TSVs and one microbump. The resistance of one microbump was less than 0.1 . The capacitance–voltage and leakage current– voltage characteristics of poly-Si TSVs are plotted in Fig. 8(b). These characteristics were measured using a daisy chain with 72 vertical interconnections, which were allocated to the three layers. From these characteristics, we obtained the capacitance value of 0.22 pF for one vertical interconnection. As a result, the RC delay of 2.2 ps for one vertical interconnection is derived from these results. A leakage current of one vertical interconnection was less Fig. 9. W thickness and step coverage in a deep trench as a function than 0.5 pA at the applied voltage of 10 V. of a reaction gas evacuation rate.

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Fig. 12. The current–voltage characteristic and the resistance of Fig. 10. SEM cross-sectional view of the W film deposited into a W/poly-Si vertical interconnection. deep Si trench having diameter of 2 m.

12 m. In this TSV, a poly-Si layer with a thickness of deposition temperature of 350 C. Fig. 10 shows an SEM 0.5 m was formed as a liner layer before the W depo- cross-sectional view of the W film deposited into a deep Si sition. Therefore, the trench size for the W deposition trench having a diameter of 2 mandadepthof40m. decreases to 1 by 11 m. In the formation of this W/poly-Si The W film thickness was almost identical at the top TSV, we employed the W deposition conditions such as the surface, middle of the trench, and bottom of the trench adsorption time of 1 s, reduction time of 15 s, evacuation (0.3 m), whereas it was 0.18 m at the trench corner time after WF introduction of 5 s, and evacuation time surface. Excellent step coverage of approximately 100% 6 after SiH introduction of 5 s at a deposition temperature was obtained by employing the optimized conditions. 4 of 350 C. The poly-Si liner layer improves the step Fig. 11 shows the (a) SEM cross-sectional view and coverage and adhesivity of W film in trench since WF (b) photomicrograph of the back surface of the W/poly-Si 6 dissolves at the poly-Si surface, which acts as a catalyst. It TSV with a trench depth of 50 m and trench size of 2 by is obvious from the figure that tungsten was filled into the bottom of the deep and narrow trench. The photomicrograph of the back surface after the mechanical grinding and CMP is also shown in Fig. 11. W, poly-Si, silicon oxide, and silicon substrate were uniformly polished, and a very flat surface was obtained after the mechanical grinding and CMP. The current–voltage characteristic and the resistance of W/poly-Si vertical interconnection are plotted in Fig. 12. This characteristic was measured using a daisy chain with 76 vertical interconnections, which were allocated to the three layers. Four W/poly-Si TSVs with a size of 2 by 12 m are connected in parallel in one vertical interconnection. From Fig. 12, we obtained a resistance value of approximately 0.23 for one vertical interconnection, which gives rise to a W resistivity of 26 cm. Furthermore, we have fabricated a very narrow W/poly-Si TSV with a cross-sectional width of 0.7 m, as shown in Fig. 13. Thus, we have developed a W/poly-Si TSV technology combining the method of liquid adhesive injection after temporally bonding wafers by metal microbumps. Fig. 14 shows the scaling capability of the W TSV. The diameter, length, and RC delay of a TSV, the silicon oxide thickness underneath the TSV, and the microbump size (side length) are plotted as a function of the TSV pitch in Fig. 14(a). The maximum number of TSVs as a function of Fig. 11. (a) SEM cross-sectional view of the W/poly-Si TSV and (b) photomicrograph of the back surface with a trench depth the ratio of the total area of the TSVs to the chip area is of 50 m and trench size of 2 by 12 m and photomicrograph plotted in Fig. 14(b). In deriving the maximum number of of the back surface after the mechanical grinding and CMP. TSVs, we assumed that the area of each layer in the 3-D LSI

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Fig. 13. SEM cross-sectional views of W/poly-Si TSV with a cross-sectional width of 0.7 m.

is 10 by 10 mm and the allowable area for the TSVs was 1%, 5%, and 10% of each layer. We approximated the RC delay of the TSV as 2" ðl=rÞ2= lnð1 þ d=rÞ,where, l, r, ",andd denote the resistivity of the TSV conductive material, the length and the radius of TSV, the dielectric constant, and the thickness of the insulator underneath the TSV, respectively. It is obvious from the figure that we can Fig. 15. (a) Configuration of 3-D microprocessor test chip and (b) an SEM cross-sectional view of it. significantly increase the maximum number of TSVs

without a serious area penalty by reducing the TSV size. Forexample,wecanformtensofthousandsofTSVsina chip with an area penalty of 1 mm2 even for the case of a TSV pitch of 10 m. Therefore, in the case of a 3-D memory LSI, we can achieve approximately ten times higher packing density by stacking 11 memory layers compared with a conventional 2-D memory chip having the same footprint. The total area penalty (10 mm2) for ten memory layers can be canceled out in the eleventh layer. If the TSV pitch is reduced to 1 m, we can form 106 TSVs in achipwithanareapenaltyof1mm2.TheRCdelayofa TSV decreases to less than 5 fs as the TSV pitch is reduced to 1 m.

Fig. 14. Scaling capability of TSV. (a) Diameter and length of TSV, thickness of insulator underneath the TSV, microbump size and RC delay as a function of TSV pitch. a: TSV length, b: microbump size, c: TSV diameter, d: insulator thickness. (b) Number of TSV as a function of TSV pitch. Fig. 16. Measured waveforms of 3-D microprocessor test chip.

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V. THREE-DIMENSIONAL LSI TEST CHIP FABRICATION Three-dimensional LSIs are suitable for parallel processing and parallel data transferring due to the increased connectivity of their short vertical interconnections compared with conventional LSIs. We can create various kinds of new LSIs with parallel processing and parallel data- transferring capabilities by employing 3-D stacked structures having many vertical interconnections. So far we have fabricated several 3-D LSI test chips such as 3-D microprocessor chip, 3-D shared memory, 3-D image sensor chip, and 3-D artificial retina chip using 3-D integration technology based on wafer-to-wafer bonding with poly-Si TSVs [29]–[34]. Fig. 15 shows a configuration of a 3-D microprocessor test chip and an SEM cross-sectional view of it. A processor, logic circuits, and cache memory are formed in the first, second, and third layer, respectively, in this 3-D microprocessor chip. These three layers are connected by poly-Si TSVs with a size of 2 by 12 m and In-Au microbumps with a size of 5 by 5 m, as shown in Fig. 15(b). The silicon layer thickness is approximately 30 m. The epoxy adhesive was injected into the gap of approximately 4 m between the upper and lower wafers. As is obvious in the figure, any voids are observed between the upper and lower wafers. Measured waveforms of this 3-D microprocessor test chip are shown in Fig. 16. In this test chip, a processor in the first layer operates at the supply voltage of 2.5 V and SRAM cache memory in the third layer operates at 3.3 V. The supply voltage is changed from 3.3 to 2.5 V by the level converter in the Fig. 17. (a) Configuration of 3-D shared memory test chip and second layer. It is demonstrated in the figure that data (b) an SEM cross-sectional view of it.

Fig. 18. Cross-sectional structures of human retina and 3-D artificial retina chip.

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ture as shown in Fig. 18(a), which consists of photo- receptor layer, horizontal cell layer, bipolar cell layer, amacrine cell layer, and ganglion cell layer. We can implement basic functions of a human retina by a 3-D artificial retina chip, as shown in Fig. 18(b). Fig. 19 shows a photomicrograph of a 3-D artificial retina chip fabricated by 3-D integration technology. This artificial retina chip has a three-layer structure. Functions of the horizontal cell layer, bipolar cell layer, amacrine cell layer, and ganglion cell layer are simplified and allocated into two layers of an artificial retina chip. A quartz glass is glued on top of this artificial retina chip. We confirmed a basic function of edge

Fig. 19. Photomicrograph of 3-D artificial retina chip. enhancement in this 3-D artificial retina chip.

VI. CONCLUSION B1[ (Vin1) and B0[ (Vin2) are read from the SRAM cache We have developed polycrystalline silicon (poly-Si) TSV memory in the third layer and then transferred to the technology and tungsten (W)/poly-Si TSV technology processor in the first layer through the second layer to combining the method of liquid adhesive injection after successfully perform the arithmetic operation. A configu- temporally bonding of wafers by metal microbumps for ration of 3-D shared memory test chip and an SEM cross- 3-D integration. In the poly-Si TSV formation, LPCVD sectional view of it are shown in Fig. 17. Several blocks of poly-Si heavily doped with phosphorus was conformally data in a memory layer are simultaneously transferred to deposited into the narrow and deep trench formed in an Si another memory layer through a number of TSVs. CPUs substrate after the surface of the Si trench was thermally are connected to the respective memory layers of this 3-D oxidized. In the W/poly-Si TSV formation, tungsten was shared memory. Therefore, many CPUs can share the deposited into the Si trench by ALD method after the poly- identical data without any conflicts after the data transfer. Si deposition, where poly-Si was used as a liner layer for W The 3-D shared memory test chip with ten memory layers deposition. We have successfully fabricated 3-D micropro- was fabricated as shown in Fig. 17(b). We also fabricated a cessor test chip, 3-D memory test chip, 3-D image sensor 3-D artificial retina chip using 3-D integration technology. chip, and 3-D artificial retina chip by using poly-Si TSV A human retina has a three-dimensionally stacked struc- technology. h

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ABOUT THE AUTHORS Mitsumasa Koyanagi (Fellow, IEEE) was born in technology, optical interconnection, and parallel computer system Hokkaido, Japan, on February 4, 1947. He received specific for scientific computation. He fabricated the smallest MOS the B.S. degree in electrical engineering from transistor with a gate length of 70 nm in 1992. He proposed three- Muroran Institute of Technology, Japan, in 1969 dimensional integration technology based on wafer-to-wafer bonding for and the M.S. and Ph.D. degrees in electronic the first time in 1989. Since 1994, he has been a Professor in the engineering from Tohoku University, Sendai, Department of Machine Intelligence and Systems Engineering (currently Japan, in 1971 and 1974, respectively. the Department of Bioengineering and Robotics), Tohoku University, He joined the Central Research Laboratory, Japan, where his current interests are nano-CMOS devices, memory Hitachi Ltd., in 1974, where he worked on research devices, low voltage and low power integrated circuits, new intelligent and development of MOS memory device and memory for parallel processor systems, three-dimensional integration process technology and invented a stacked capacitor DRAM memory cell, technology, optical interconnection, parallel computer system specific which has been widely used in the DRAM production. Stacked capacitor for scientific computation, real-time image-processing systems and DRAM was the first commercialized 3-D LSI. He employed high-k artificial retina chips, retinal prosthesis and brain implant devices, and materials in DRAM for the first time in 1978. In addition, he fabricated brain-like computer systems. He has been researching three-dimensional MOS transistors with shallow junction using laser annealing technology integration technology and optical interconnection for more than for the first time in 1979. From 1980 to 1985, he was with the Device 15 years. Development Center, Hitachi Ltd. In 1985, he joined the Xerox Palo Alto Prof. Koyanagi received the 2006 IEEE Jun-ichi Nishizawa Medal, the Research Center, CA, where he worked on research and development of 1996 IEEE Cledo Brunetti Award, the 2001 Award of Ministry of Education, submicrometer CMOS devices, polysilicon thin-film transistors, and the Culture, Sports, Science and Technology, the 1994 Solid-State Devices design of analog/digital LSIs. In 1988, he joined the Research Center for and Materials Award, the 2004 Optoelectronic Technology Achievement Integrated Systems, Hiroshima University, Japan, as a Professor, where Award from the Japan Society of Applied Physics, and the 1990 Okouchi he worked on scaled MOS devices, three-dimensional integration Prize.

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Takafumi Fukushima was born in Gunma, Japan Tetsu Tanaka (Member, IEEE) was born in on February 6, 1976. He received the B.S., M.S., Miyagi, Japan on March 3, 1964. He received the Ph.D. degrees in synthetic chemistry from B.S. and M.S. in electronic engineering and the Yokohama National University in 1998, 2000, Ph.D. degrees in machine intelligence and systems 2003, respectively. His research interests include engineering from Tohoku University, Sendai, polymeric studies focusing on synthesis and char- Japan, in 1987, 1990, and 2003, respectively. He acterization of high-performance heat-resistant joined Fujitsu Laboratories Ltd. in 1990, where he polymers such as polyimides, BCB, and epoxy has been engaged in the research and develop- resins. From 2001 to 2003, he was technical ment of the scaled MOS devices including SoI advisor at PI R&D Corporation in Yokohama, devices. From 1994 to 1995, he was a visiting where he studied adhesives, interlayer dielectrics, electrodeposition, industrial fellow in the University of California, Berkeley. He joined and photoresists based on soluble block-co-polyimides. After that, he Tohoku University as an associate professor in 2005 and became a worked at Venture Business Laboratory of Tohoku University as a professor in 2008. He is currently working on retinal prosthesis, brain postdoctoral fellow. He is currently working at Tohoku University as a implant devices, three-dimensional LSIs, nano-CMOS devices, nano-dot research associate on many aspects of bioengineering and robotics memory, etc. He is a member of the IEEE Electron Devices Society and the including micro-TAS, optical interconnection, 3-D stacked LSI, and retinal IEEE Solid-State Circuits Society. prosthesis.

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