pESIGN OF THE M.3 COMPUTER

A Thesis

�ubmitted to the Faculty of Graduate Studies

in Partial Fulfilment of the Requirements

for the Degree of

Master of Science

in the Department of Electrical Engineering

Yniversity of Saskatchewan

_Kenneth E. Cameron.

Saskatchewan _ Saskatoon,

-The University of Saskatchewan claims copyright in conjunction with the author. Use shall not be made of the material contained herein without proper acknowledgment. Acknowledgment

Tr� author wishes to express his sincere gratitude to Dr. A.D. "

Booth for his invaluable guidance throughout this project. Grateful acknowledgment is also made to J.M.S. Devries for his helpful suggest- ions and keen interest in the project, to T.R. Viswanathan for ,assist­ ance in circuit design, to H.C. Ratz for advice in the early stages of the project and to A. Michalenko for assistance in editing this thesis.

The author also extends thanks to W.R. Woodward and B.E. Michael for their capable workmanship in assembling the computer.

Acknowledgment is made of financial support to the National

Research Council (Grant #B.T. 140) and the Defence 'Research Board

(Grant #2804-05). Abstract

A solid state digital computer, the M.3, has been designed, constructed and partially tested. The computer logic is based on the M.2 computer con­ structed by A. D. Booth in 1956, b�t with fundamental changes to the logic associated with the store and the arithmetic section.

The M.3 is a serial, fixed'point computer which uses 32 bit words and two address instructions. The 150 KC/S clock frequency permits addition or subtraction in 250 microseconds. Division requires 8000 microseconds and multiplication requires 250 to 8000 microseconds. A drum store provides 8192 word storage with an average random access time of 8500 microseconds.

Peripheral equipment consists of an 80 character per second tape reader and a 60 character per second tape punch or a 10 character per second typewriter.

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Plate I

Front View of M.3 Computer TABLE OF CONTENTS Page

1. HISTORY OF DIGITAL COMPUTERS 1

2. THE M. 2 COMPUTER 8 2.1 The Memory 9 2.2 The Control 11 2.3 The Arithmetic Unit 14 2.3.1 Right Shift 15 2.3.2 Left Shift 15 2.3.3 Addition 16 2.3.4 Subtraction 17 2.3.5 Multiplication 17 . 2.3.6 Division 19

3. REASONS FOR TRANSISTORIZING THE M.2 20

4. DESIGN OF LOGICAL CIRCUITS 24 4.1 Design Technique 24 4.2 The Basic Flip Flop 26 4.3 Basic "And" Gates 29 4.4 Basic IIOr" Gates 31 4.5 One Shot Circuits 33 4.6 The Inverte� 36 4.7 D.C. Delay 36 4.8 A.C. Amplifiers 37 4.9 Emitter Followers 39 . 4.10 Neon Driver 41 4.11 Circuit Layout Techniques 41

5. THE STORE 43 5.1 The Magnetic Drum Memory 43 5.2 The Counter and Coincidence Senser 45 5.3 The Head Switch 50 5.4 The Block Switch 54 5.5 The Write Circuit 57 5.6 The Read Circuit 63

6. OVERALL SYSTEM DESIGN OF THE M.3 67 6.1 The Control 67 6.2 The Arithmetic Section 75 6.2.1 Transfer of a Number from Memory Location I;XII 75 to the Shift Register 6.2.2 Transfer of a Number from Memory Location "XII 75 to the Cycle Register 6.2.3 Right Shift and Left Shift 78 6.2.4 Addition and Subtraction' 78 6.2.5 Clear Operations 83 6.2.6 Multiplication 84 6.2.7 Division 86

REFERENCES 88

M.3 ORDER CODE 89

APPENDIX A 91 LIST ·OF FIGURES

Fig. Title Page

2.1 M.2 Control Schematic 12 2.2 Right Shift Logic 15 2.3 Left Shift Logic 15 2.4 Adder Logic 16 2.5 M.2 Multiplier Schematic 18 2.6 M.2 Divider Schematic 19 3.1 Non Restoring Divider Logic 21 4.1 Basic Building Block 25 4.2 .Basic Flip Flop 27 4.3 Basic Flip Flop Showing Input Gating 27 4.4 Symbolic Flip Flop Representation 27 4.5 Symbolic Counter Representation 27 4.6 M.3 "Andll Gates 30 4.7 Symbolic Representation of an "And" Gate 30 4.8 Basic "Or" Gates 32 4.9 Symbolic Representation of "Or " Gate 32 4.10 Basic One Shots 34 4.11 M.3 Inverter 36 4.12 Short Time D.C. Delay Element 37 4.13 Basic A.C. Amplifiers 38 4.14 Basic Emitter Followers 40 4.15 Neon Driver Circuit 41 5.1 Counter and Coincidence Senser (M.3 Unit 1) 46 5.2 Coincidence Senser Circuit 47 5.3 M.3 Timing Pulses 49 5.4 Head Switch Circuit for Head 0000 52 5.5 Block Switch Circuit for Block 0000 55

5.6 Head Switch - Block Switch - Read - Write Interconnections 56 5.7 Write Gate 59 5.8 Pulse Shaper and Power Amplifier Logic 61 5.9 Write Circuit Power Amplifier 61 5.10 Read Circuit 64- 5.11 Frequency Response of Read Amplifier 65 6.1 Control Register (M.3 Unit 5) 68 6.2 The Function Table 70 6.3 0.6 Shift Register - Counter 71 6.4 Control (M.3 Unit 6) 72 6.5 Shift Register (M.3 Unit 3) 76 6.6 Cycle Register (M.3 Unit 4) 77 6.7 Accumulator (M.3 Unit 2) 79 6.8 Arithmetic Unit (M.3 Unit 7) 81 6.9 Arithmetic Unit Coincidence Senser 82 6.10 Zero Accumulator Circuit 84 1 "'.-

I. HISTORY OF DIGITAL COMPUTERS

The history of computing machines began when man learned to

count. The familiar decimal system- originated with the use of the fingers

(digits) for simple ee.leulations. Later,.·notched sticks, stones and knot-

ted strings were used to represent quantities in calculations involving

. larger numbers. .

The earliest known mechanical device used for arithmetic calcu-

lations is the Abacus. This instrument, which consists of moveable beads

strung within a wooden frame, was developed in the·Far East about 600 BoC.

Addition, subtraction, multiplication and division can be performed with

the Abacus, but the earliest users of the Abacus probably used it only for

addition and subtraction.

The next step in the development of the automatic caloulating

. machine came in 1642 when a crude, stylus oper_ated, numerical· wheel eakeu-

lator was devised by Pascal. Numbers were represented by the visible fig-

ures on a set of rotatable wheels, each wheel being numbered from 0 to 9.

Numbers could be added to or subtracted from the instrument by rotation

of the wheels. Carry over to the wheel on the left was oontrolled by a

. carry meehanf.sm, Later, this caloulator was modified by Leibnitz to

enable the performanoe of multiplication and division. However, both modi-

fied and unmodified version were �eliable. The early calculators of_

Pasoal and Leibnitz were greatly improved during the late seventeenth cen-

tury by several people. Morland, Stanhope, and later Troncet, made out-

standing improvements to the manually operated-oaloulator. Further improve-

ments, including the addition of an electric drive, transformed the early

caloulators into the modern desk calculator.-

In 1812 Charles Babbage proposed·the idea of building a machine

which would be oapable of performing accurately the simple calculations

I .. - .. ------

2

required for generating tables of functions. Support for a small model

was obtained from the Royal Society and the model was completed in 18220

The instrument was found to perform very well and the government of the

day advanced support for the design and construction of a much larger

model. This model, the "Difference Engine" was designed to work to 20

decimal places using sixth order differences. Throughout the construc­

tion of the machine, the lack of preCision lathes and cutting tools

caused many engineering difficulties. Finally, this plus the loss of

financial support caused the project to be abandoned entirelyo

In 1833 Babbage proposed to build a calculating machine which

a would perform all the arithmetic operations of universal computero _

The computer, the "Analytic Engine" was to have storage facilities for

one thousand, fifty digit numbers. To speed up addition, Babbage devised

a mechanical method of simultaneous operation of all carries (anticipated

carry) • This, for example, would allow the machine to automatically zero

all 9's when 1 had been added to 899999 and to add 1 to the 80 This

technique has been the basis of the adder system of several modern mach­

ines.

The Analytic Engine contained many other features which make it

the true ancestor of today's computing systems. In the design of his mach­

ine, Babbage originated all the logical elements which are used in today's

computers. It consisted of two main parts, the mill and the store. The

mill was the equivalent of today's arithmetic unit and the store had the

same purpose as the memory of modern computerso

The use of punched cards as a computer input was first suggested

by Babbage. The card used with the Analytic Engine was a slightly modi­

fied version of the punched card Which had been in use for many years to

control the weaving of complex designs on the Jacquard loom. 3

The results of calculations were to be printed by a mechanism which would set up a block of type representing the results, check the

correctness of this block, and then print ito The faculty of checking

the printed output was one advantage which this mechanism pad over al­ most all subsequent modelso

The machine was designed in such a way that it could make a

choice between two or more alternative operations. This is the so­

called "conditional transfer" or "branch" instruction which is present

in the structures of all modern computers and is partially responsible

for their usefulness.

Thus Babbage conceived the idea of the first universal calcu­

lating machine. Prior to his death in 1871, Babbage prepared many de­

tailed drawings from which the analytic engine could have been construc­

ted, had precision tools been available. His son, Major H. P. Babbage,

constructed a portion of the mill and print out mechanism between 1880

and 1910. This machine was able to calculate and print out the multiples

of1r'to 20 decimal places as was shown at one demonstration. It has

since been placed on display at the South Kensington Science Museum.

The first data sorting system was developed in 1889 by Herman

Hollerith to handle information gathered in the American census. As an

input to his mechanism, Hollerith used a punched card similar to that

suggested by Babbage. This mechanism became the basis of the accounting

machines which the predecessors of International Business Machines began

to manufacture in 1903.

It was not until a century after Babbage conceived the Analytic

Engine that the next universal computer was designed. In 1937, Professor

Howard Aiken of Harvard University, assisted by International Business

Machines, designed and constructed the Harvard Mark I Automatic Sequence 4

Controlled Calculatoro This computer, which was completed in 1944, used

similar logic to that of the Analytic Engineo The mechanical construction was quite different though, as the machine used electromechanical elements

instead of the mechanical elements of Babbage1s time. The store of the machine was not entirely divorced from the arithmetic unit since seventy­ two of the storage registers also acted as adders or subtractors. In order

to obtain faster addition rates, the "anticipated carry" system designed by Babbage was usedo Sixty other storage registers were also available, but as they were manual� controlled, they could be used only for storing

constants 0

The Harvard Mark I was designed with a central multiplier and

divider, plus a number of special units to generate functions such as

log x, lOX, and sin Xo Input to the computer was by punched card or by

automatic typewritero There was also an automatic sequence control unit

which directed operations from punched paper tapeo

The Mark I is still in operation and has been used for many use­

ful tasks over the past nineteen yearso Its speed is many times slower

than the speed of the most recent computers, but in 1944 it was able to do

tasks for which it was designed at a rate many times faster, and with far

greater reliability than any alternative methodo

An engineer with Bell Telephone Laboratories, Go Ro Stibitz, was

the first person to design a computing device which used electromagnetic

instead of electromechanical operatd.on, This computer, known as the _'BCom­

plex Number Computer" required some assistance from the human operator and

was classed as semi-automatic. Composed entirely of telephone relays, and

using teletype equipment for input and output, the computer was capable of

performing multiplication or division accurately in a few secondso

During the war, Bell produced three special purpose relay compu­

ters which calculated ballistics' tables to be used in gun sight calibra-

" I tion and with fire control equipment. Follo��ng the war, Bell received a

government contract'for the development and construction of two rel�

operated general 'purpose digital computers. The new computers were known

as the Bell Model V Computers. Many new computer design concepts were

apparent in their construction. All arithmetic operations were performed

on floating decimal point numbers. With this notation, the number 594

woUld be represented by 0.5940000 multiplied by 1000.000,000,000,000,0.

The biquinary system, similar to that used on the Abacus, was used to

represent each decimal number on the relays. Using this code, 7 rel�s

are needed to represent each decimal number. Assuming an open relay is

represented by 0 and a closed relay by 1, the relay configurations are

as follows:

DEC IMAL DIGIT RELAYS

00 5 o 1 234

o 1 0 1 0 0 0 0 1 1 0 o 1 000 2 1 0 o 0 1 0 0 3 1 0 o 0 010 4 1 0 00001 '5 0 1 1 000 0 6 0 1 o 1 000 7 0 1 o 0 1 0 0 a 0 1 o 0 010 9 0 1 o 000 1

The machine was very accurate and never proceeded to a new

calculation until the previous one had been checked. Any mistake made

by the computer caused the machine to stop and turn on a lamp, indicat-

ing the trouble spot.

This computer pair has been in operation since 1947 and, due

to its self checking and to the reliability of the telephone relay"thf),

machines have accomplished a great deal of work with a ,minimum of errors

and maintenance.

I • 6

Another large relay computer, the Harvard Mark II, was built by the Harvard University group. Construction was started in 1945 and in 1947 the machine was in operationo The Mark II used floating point numbers similar to those used in the Bell Model V. The use of special high speed relays plus the elimination of the self checking property made the operating speed of this machine considerably faster than that of the Bell computers.

With relay calculators, it was difficult to perform more than fifty additions per second due to the time required to switch a rel�.

This switching time was dependent upon the inertia of a moveable. portion

of the rel� and also upon the inductance of the coilo By using elec-

tronic tubes and diodes as logical elements in a computer, much faster

switching times could be obtained.

The possibility of constructing a computer using electronic

components as logical elements was first investigated by the Moore School

of Electrical Engineeringo A computer known as the "ENIAC" (Electronic

Numerical Integrator and Calculator) was designed by JoPoEckert and

J.W. Mauchly as a result of this investigation. The computer design was

completed in 1945 and the- "ENIACo was working in 1946. Although the

machine as was initially designed had limited applications, logical chan-

ges during construction caused the final model to be quite vers$tile.

The use of electronic components allowed the machine to operate a� a pre-

viously impossible speed of 5000 additions per second. The "ENlAC" used

a logical structure quite similar to the relay machines of that dayo

Modern computers, although performing the same tasks as early

machines, are quite different. Calculating speed has been increased by

several hundred times, yet physical size and power consumption have been

greatly reduced. 7

Semioonductor dev�lopments and new memory devices are primarily responsible for this change. Semiconductor circuits switch many times faster than electronic tube circuits, yet require much less power and virtually no maintenance. They are also compact .and require no forced ventilation. Recently developed memory devices using magnetic storage provide fast access time yet require no retaining power and very little recording or emitting power. High speed semioonductor memories are also being developed.

New mathematical techniques have simplified the logic required to perform arithmetic operations within a computer. The use of number

systems with a base other than ten has also simplified computer logic.

The following chapters describe how a moderate speed, modern computing system has been developed. 8

2. THE M.2 COMPUTER

In 1956 a general purpose digital computer, the "M.2n, was de­

signed at Birbeck College, University of London by A. D. Boo�h. The logical operations required for addition, subtraction, multiplication and division are performed �n the M.2 by hot-tube electronic circuits. The

M.2 logic derives from a series of computers: the nARC", a stored pro­

gr� ��lay computer; the nSEC", an electronic computer eapabl.e ot addition

Ii and subtracti9n with a magnetic drum mem�ry; the APEXC n, a modified SEC with double speed and an automatic multiplier and the "MAC", the prototype

of the M.2 \!hich was similar in design to the "APExcn but contained an

automatic divider.

The M.2 is a binary computer working with 32 bit numbers con­

fined to the -1 x The first range { (1 ( a bit is a, binary c;iigit) • digit,

of a number represents the sign, being ° for, a positive number and 1 for

a neg�tive �umber. Negative numbers are expressed in the complementar,y form mod. 2. Thus +t appears as 0.0100,0000,0000,0000,0000,0000,0000,000

and -t appears as 1.1100,0000,0000,0000,0000,0000,0000,000 (i.e. 2-t).

Instructions are also �epresented by �2 bit numbers. To ease

program optimization, "two address code" instructions are used. A typi­

cal instruction is: Add the number :i,n location nx" into the accumul:.tor

and obtain the next instruction from location nyn. The first 10 bits of

the instruction contain the "Xn address, the n!_xt 10 the tey" address, the

next 5 the order to be performed_and the next 6 the input to the control

counter. The last bit, the "vector recorda instruction, when set to unity

causes recording of the, same number in all word locations of one track.

The M.2 is composed of three main units; the memory which is

responsible for storing both instructions and data until required, the 9 control which is capable of receiving and executing instructions stored in the memory and the arithmetic unit which must on command from the con­ trol operate on stored data to produce the combinations of ordi� arith­ metic.

2.1 The Memory

The memory of ,the M.2 consists of a machined aluminum cylinder which is rotated at 3400 R.P.M. by a small induction motor. The surface of the cylinder is coated with a thin homogeneous layer of ferrous oxide and plastic. Thirty-two recording heads are spaced evenly along the drum surface, each on an individual track. The spacing between the drum sur­ face and the head is approximately .00025 inch.

Two clock tr'acks are engraved on one end of the drum to provide an address for each bit of stored information on the drum. The first track is the "word marker track". It has thirty one single groove mark­ ers and one double groove marker spaced evenly around the drum. Electri­ cal impulses induced in a small reading head by this track indicate the beginning of each word. The impulses are amplified and the resulting pulses are counted by a 5 stage binary counter. A special gating network causes the double pulse to set the counter to zero. Successive word markers each advance the counter by one. The binary number contained in the counter while the reading head is between any pair of word markers is known as the "word location" of that particular word.

To complete the location of any particular word on the drum, the recording head used to record information must also be specifiedo As there are 32 different heads, a five bit "track location" number must accompany the "word location" number. This results in the ten bit "mem­ ory location" address used by the M.2. 10

»» The second clock track is known as tp.e "bit marker_track".

This track has 32 slots engraved between each pair of markers_on the word marker track. An unmarked recovery space equivalent in length to 4 bit spaces is left at the beginning and end of each set of slotso

The M.2 is a serial machine -in which data transferred between the memory and the rest of the computer become avail_ble one bit at a time starting with the least significant bit. Tq transfer information te a memory location, the control addresses the "I" track location and a com­ parison is made between the "X" word location (stored in the control) ,and the word location shown by the word marker countero When these are equal

(coincidence), the memory emits 32 bit markerso

If the least significant bit of the word being recorded is a

"I", the first bit marker pulse is gated to cause a four microsecond cur- rent pulse to pass in one direction through the recording head windingo

The resulting magnetic field magnetizes a small spot on the drum surface.

If a bit in the word is a "0", the corresponding bit marker produces a similar current pulse which �ass.s through the recording head winding in the opposite direction. This produces a magnetized spot with opposite polarity to the spot recorded by a "l't. The remaining bits in the word are recorded on the drum in a similar manner by their correspond­ ing bit marker pulses.

The memory generates an "operation complete pulse" (opo compo pulse) after emission of the thirty second bit marker pulse. This indica- tes to the control and arithmetic unit the completion of any operation in which information is transferred to or from the memoryo

Information recorded on the drum induces a small voltage in the recording head as each magnetized element of the drum surface rotates un- der the recording head. If a "l" has been recorded in a particular bit location, the voltage induced in the head resembles a single cycle of a 11

sine vave. If a "0" vas recorded, the induced voltag� resembles a single

wave a cycle of a negative sine 0 To determine the identity of bit, ,the recording head output is amplified and the signal obtained is sampled

during the centre t of the sine wave corresponding to each bito If the

amplifier output: dnd'l'lg.._this time is going negative, the sampling circuit reoognizes the bit-as a 1'1"0 If the output is going positive, it is recog-

nized as a "0"0

Access time to this type of memory is inherently slow as the

drum must rotate to the proper word location before information can be re-

corded or from .. +- re�eived the memorya . '.�

�, ' Information no longer needed can be erased from the memory by

recording new information over the old. If recorded information is not

removed in this manner, it vill be retained for many years with negligible

deterioration.

2.2 The Control

'The M.2 control consists, 6f 'three main sections: the "control

register which stores 'an instruction ,until it,is executedg the'decoder

which interprets the instruction in the control registerg and the control

counter, vhieh has been incorporated into the control register to control

the number qf basic oper�tions performe4 in aninstructiono Oper�tion of

','.l!' state the eomputer",must",exeeut� the instruetio�_stored ;in the contrOil

register. If it is in:th�' zero state:;:-,the memQI'Y.":must shirt � neW instruc­

tion into� tne control: register. The 'pomputer ;InUst �:pcute three basd,e in-

structio� types; instN!';t;i.ons vhich' shift a single vord to or ,.,rrom the

memory, instructions which require more than one basic operation and branch

instructions.

With instructions requiring transfer of information between mem-

ory and arithmetic unit, the CoFoF. change to the "I" state shifts the "I" Digits .out r--.-��------� ARITHJ.IETIC Digits in UNIT MEMORY Cont Lnuous clock read

in 32 Pulses

Word l.!arker Operation Head complete Counter � Switch . N 1 J;r J J»'(» J .. ( () ,ontro 11 Flip "TI o -_. :J 0 • 1I I .__-+-'I_-+-----�I__------_t_---_t---...._t Flop 01 'llr CO -to o . -N V'I • o - :::r (I) 3 o ::t. o

REGISTER Vector Control Register C, Record Counter Inst. Shift Pulses (32) Control

-� track location from control register stages 1 to S (CoRo 1-5) through the "and" gate, g4' to the track se�eetor and permits the decoder to issue the order stored in CoR. 21-25 to the arithmetic unit (Figure 2.1).

When coincidence occurs between the available word location and the "XI word location (C.R. 6-10), 32 shift pulses from the memory cause the exe­ cution of the order. Following the thirty-second shift pulse, the OPe compo pulse generated � the memory passes through the arithmetic unit to zero the C.F.F., shift the '�n track location (CoRo 11-15) through gs to the track selector and shift the UY" word location (CoR. 16-20) through g6 into the C.R. 6-10 locations. Zeroing of the C.F.F.o instructs the memory to read and opens g3 to allow the 32 shift pulses emitted by the memory on coincidence to shift the next instruction into the control register. Following the thirty-second pulse, the OPe compo pulse genera­ ted by the memory returns the CoF.F. to the "1" state ready to execute the next instruction.

With instructions requiring the completion of more than one basic operation, the C.F.F. change to the "1" state shifts the "X" track location into the track selector and permits the decoder to emit an in� struction. As this type of instruction does not require coincidence with a word location, operation starts immediately. Each basic operation per­ formed passes a pulse through g7 to the control counter (C6)0 When the required number of operations have been performed, the most significant

stage of 06, 0.R.26 generates an "operation complete" pulse to zero the

C.F.F., shift the "In track location into the track selector and shift the nyn word location into C.R. 6-10.

When coincidence occurs, the zeroed CoF.F. shifts a new instruc- tion into the control register in a manner similar to that described in the previous example. The opo compo pulse following the shift resets the \ \ I e.F.F. to unity,.ready to execute the new instruction.

With branch instructions, the next instruction shifted into the control register is determined by the sign of a number stored in the arithmetic unit. When the CoF.Fo switches to the "1" state, the "xn track location is set into the track selector by and a gating pulse I g4 from the decoder tests the sign of the number in questiono If the sign bit is a "0" indicating a positive number, the arithmetic unit emits an operation complete pulse which zeros the CoFoFo and opens gs and g6 �o .- shift the next instruction to the control register from the wyn memor,y location. However, if the sign bit is a "In, the arithmetic unit emits a pulse on�the branch n < 0 line which zeros the CoFoFo but does not open gs or g6. This results in the new instruction being shifted to the con­ trol register from the "X" memory location. Following the instruction shift, the operation complete pulse generated by the memory will set the c. F.F. to a "l" ready to execute the new instructiono

2.3 The Arithmetic Unit

Operation of the arithmetic unit is controlled by the control unit. When instructed, the arithmetic unit will perform right shifts, left shifts, additions, subtractions, multiplications and divisionso

Provision is made for the emission of an operation complete pulse on com- pletion of an operation, or alternatively, for generation of basic opera­ tion complete pulses for the control counter 0 The arithmetic unit con- tains two electronic storage registers, the accumulator and the shirt register. Both can store a 32 bit word, and have the property that stored digit patterns can be shifted to the right onlyo

of order To explain the operation the arithmetic unit J) each will be considered separately. , .. '------...,...,=------

15

2.3.1 Right Shift

In the right shift, the least significant digits of the number

• A"stored in the accumulator are shifted into the most significant end of

the shift register. The sign digit of-Avis propagated to fill the most

significant end of the accumulator. The least significant digits of the

number stored, in the shift register are losto \, ac�umulator shift register digits ElJQ�}__2�__��--�13-/�13l�f---��O---�-� �/�� lostll< ! �

. ( shift .1 , •• t shift

Fig. 202 Right Shift Logic

The logical circuits required to perform the right shift are \ shown in Figure 2.2. The control counter (C6) is advanced by each right

shift, allowing control of the total number of: shiftsi. An. n' bit'�:f'ight shift

"" . n A is equivalent. to divid1ng by 2 •

2.3.2 Left Shift

left shift is similar to the right shift, but the. contents of .the

last regi ster �tage are shifted back to the first . stage of. thli'·. accumulator.

To obtatn aJ.�1eft shift,- the decoder a.ctivates both right and left shift

or4er lines sh�wn on Figure 2.3.

�

.,1 accumulator j J shift

. � ' registe,�' , I ---'1>-.... � 13 I J 21-1 .l�! 13,_,-- �------��----� shift

I� i ;

. ,,'

Fig. 203 Left Shift LogiC 16

An n bit left shift is obtained b.1 shifting the stored number to the right

64-n digits. The number of shifts performed is controlled by the 06.

2.3.3 Addition

Addition is achieved by adding the contents of memory location

UXU to a number stored in the accumulator. The rules of addition are:

If: Incident digit = carry digit (coincidence) Se�d.A32 to Al

Leave carry, digit unchanged

If: Incident digit F carry digit (anti coincidence)

Send the inverse of A32 to Al

Send AJ2 to the carry store

The carry digit must initially be set to zero. Here A n represents the contents of the nth stage of the accumulator.

Fig. 204 Adder Logic

As addition requires shifting data from the memory, the OPe compo pulse

generated b.1 the memory following emission of the thirty-second pulse in-

structs the control that the addition is finished.

r �I ---�-.===------�

17

2.3.4 Subtraction

Subtraction is performed in the M.2 by adding the complemen­ tary form mod. 2 of the incoming number from memory location "X" to the number stored in the accumulator. To obtain the true complement of a binary number, all "l"IS in the number are changed to "O"IS; all "OlliS are changed to "l"IS and "1" is added to the least significant bit of the number. The effect of inverting the incoming digits from the mem­ ory is produced by two "and" gates which invert the output of the coin­ cidence senser. The addition of one to the least significant digit is obtained by setting the carry store to unity prior to the subtraction.

The rules of subtraction for this scheme are:

If: Incident digit = carry digit (coincidence)

Send the inverse of A32 tq Al

Send A32 to the carry store

If: Incident digit 1 carry digit (anti coincidence)

Send A32 to Al

Leave carry digit unchanged.

The carry digit must initially be set to unity. The OPe compo pulse for this operation is generated by the memory following emission of the.thirty-second shift pulse.

2.3.5 Multiplication_

A multiplication order in the �.2 multiplies the number stored in the shift register by the number recorded in all word locations of the

"X" track �n the memory. The product is shovn in the accumulator. The multiplier, shown schematically in Figure 205, follows the rules:

For basic operations 1,to 31:

If: R32 = R33, shift accumulator and register one place right. -==---�--�------��=-��------�

18

If: R32 = "111, R33 = "0", subtract the number stored

�hift accumulator and register one

place right.

If: R32 = nO", R33 = "In, add the :r;:tum�r �r�Q�ed qn the.lIlemqry·:t.

� to the then' ·shift accumu- " . _'.' _ _ ... ._ - - . ... ." _.- - __.. . . accumulator _." - . _,. .,.. , . ,

lator and register one place right •

. above "_ , ...... i .E�c:llly:+ :t�e_� _f!!;�' ��cept. j:,l;J.a1; ,th�_ .s�ift .is d�+�t.�d._

Rn indicates the con- �i

tents of the nth th� __ .�t.!a.g�_�f. Jll:lift r�gister. tt

The multiplication op. compo pulse. is generated by the control

counter. Following the thi���-first basic operation, the control c9unter

switches off g4 �n Figure 205, preventing right shift after the thirty� second operation.

accumulator shi!t� register

accum. shift·

ADDER SUBTRACTER

.!o:I gl til I:) .p Jot IS 0 Jot ..-I ., 0 r-I ., rO H I:) rO oM Jot CH J..t rO t: ,0 .p I'll 1 0 J..t � . ! • � .p ., �5 -o � I:) rO S :s r-I c_) e � as H 0 gg '. ro J..t 0 • g '0 Q)"M ! oM ..-I of-:> a+> .' 0 I:) � � ro I'll '-'> . • s:: � E-4 s:;: ro s:: o· ..-I a g aj H 8t g §

Fig. 2.5

r �.2 Multiplier Schematic ______i------��------�_���_�_=_�======_ �

19 2.3.6 Division

For division, the dividend is placed in the accumulator and

the divisor is recorded on all word locations of one track �n the memor.fo

The divisor must b. negative tor the operation. The divider, shown sche­

matically in Figure 2.6 follows the rules:

Basic operations 1 to 31: Send Al to Rl Store Al in F I

Clear A3.3

Shift accumulator and register one stage left.

If F = lilA Subtract the divisor from the accumulator.

If F = "0" Add the divisor to the accumulator.

The division OPe comp. pulse is generated by the control counter

following the thirty-first basic operation. 1 + 2-31 must be added to the

resulting quotient which is stored in the shift register to obtain the cor-

shift reGis:ter iffi shift rog.

- --- �L 1Shift -----

t 0 � -.-i 0 .p H "'I:::! �p.

Fig. 2.6 M.2 Divider Schematic 20

3. REASONS FOR TRANSISTORIZING THE M.2

When the M.2 was designe� in 1956, electronic tubes were the

best logic element availableo Unfortunately, tubes have several disadvan­

tages; they are expensive, they deteriorate with age and they dissipate

considerable power as heat. To keep M.2 tube requirements to a minimum,

a simplified arithmetio unit is used which replaces a 32 stage immediate

access register required for multiplication and division by a system of

recording a required number on all word locations of one tracko

This reduces cost, power consumption and heat dissipation, but

,.'has several disad:vantages. Recording a number on all word locations of

a track requires one drum revolution, thirty-two times longer than the

time required to shift information into an electronic shift registero

Programming is also more difficult as the M.2 divider assumes that the

divisor, stored on the track of the memory, is negativeo

Tube deterioration is also a problem with the M.2 as a twent7

minute maintenance period is required each�e� to prevent machine errors

due to changing tube characteristics.

The low priced, fast, switcbing transistors available tod� al�

low many of the M.2 problems to be overcome. The additional cost of a

thirty-two stage immediate access register is small. Power supply require­

ments, heat dissipation and ventilation requirements are reduced. Very

little maintenance is required due to the lQng term stability of transis­

tors. The small size of transistors and the reduced ventilation space

allow the transistorized version of the M.2 to occupy a much smaller vol­

ume than the original.

3.1 Modifications to the M.2 Structure

The first modification to the M.2 is the addition of an immediate

access DcycleD register to the arithmetic unit. Prior to multiplication

�:.� l�'i.

� JJl 21 or division, the multipli�r or divisor is shifted into this register.

Then during th� arithmetic operation, each time the stored number is re-_ quired, a group of thirty-two shift pulses are used to cycle the register and to shift data from the thirty-second stage of the register to the arithmetic unit.

The second-modifi�ation to the Mo2 is the replacement of the divider. The original divider, with no direct method to determine the sign of the divisor, assumes it to be negative. However, in the modified

M.2 the sign of th,e divisor can be determined by sampling the most signi­ ficant stage of the cycle register. This permits the use of the non- restoring process of division which places no restrictions on the signs of numbers involved.

cycle register

sets'R32 to "0"

-. sets 'R 2 accumulator to "1ft f/l, .J�tl

0 I ------���-�;'�----t��J-ef�it�s�h��f�t--�====��.-la--+I::I'--=�=-�==�-===--=.-=.��e�f=-=-i=·�t=::=::======::3Z' Resot I . Division ,J_I gg�t�¥ Complete � [.J------Flips vide R.l ----I------�£, ,II

.....

•

that is stored in the _the divi­ Assuming the divisor (C) . cycle regi�ter, _ dend (d) appears in the accumulator and the quotient (b) appears in the shift register; this process is as follows:

Operations 1 to 31: If Cl = AI Add 2-31 to (b)

left shift accumulator and register

one place.

Subtract C from A.

If Cl � AI Add 0 to (b) left shift accumulator and register

one p Lace ,

Add C to A.

Operation 32: Add 1 + 2-31 to (b).

In this A and C the nth of A and Co The logi- scheme, n n represent digit cal schematic of this divider is shown in Figure 3.1.

The 1024 word memory capacity of the M.2 is too small to handle a long program in a single run. To provide memory capacity for 'longer programs as well as space for useful subroutines, a memory with a 8192 word capacity is used in the new computero The new memory contains 64 word locations per revolution and has 128 tracks. As speed of rotation of the new drum and the M.2 drum are equal, the change in words per revolu­ tion increases the basic bit rate from 75 Kc/s to 150 Kc/s. This increases the calculation rate of the new machine by a factor of two over the M.2.

However, access time to a memory location chosen at random remains the same. Thus optimized programming is still essentialo

The increased number of tracks in the memory necessitates a new method of track selection. As 6 bits of the 10 bit memory location ad- dress are used qy the word location, only 4 bits remain to specify a track. To avoid increasing the 32 bit word length to allow direct address- 23 ing of any track, the 128 tracks are divided into 16 blocks� each con­ taining 8 heads. The heads in the first block can be addressed b,y track numbers from 0 to 7. In the remaining fifteen blocks, to address a par­ ticular head, a block must first be switched on by a block switch order.

Then heads in the particular block can be addressed by track location numbers from 8 to 15. Once a block is switched on, it will remain on un­ til a different block is addressed by a block switch instruction.

As this transistorized computer uses a similar logical struo­ ture in control and arithmetic units to the M.2 logic, it will be re­ ferred to in the following chapters as the M.3. 4. DESIGN OF LOGICAL CIRCUITS

A digital comguter is composed of electronic circuits intercon­

nected to produce an operational unit. Only a few basic circuit types

known as logical elements or logical circuits are required for a computer,

though these may be modified to meet special input or output requirements.

The overall layout of interconnected logical elements is known as the logic

of the computer.

In this chapter, the operating characteristios, design and use

of the different logical circuits of the M.3 are described. Variations

from the basic circuits are also described and their purpose is shown.

4.1 Design Technique

The primary requirements in logical circuit design are relia­

bility and acceptabl. speed. Secondar7 requirements of the circuit are

simplicity, low cost and low power consumption. To ensure reliable circuit

operation, switching circuits are designed using a "worst case" design pro-

,cedure. Worst case design implies that a circuit will work when all supply

voltages and active and passive components are simultaneously at those ex­

tremes of their tolerance limits that will tend most to make the circuit

inoperative. Component values and voltage levels are assumed to have �10%

variation. The transistor current gain, which is rated from 60 to 300 by

the manufacturer is assumed to be a minimum of 50. Circuits are designed

to operate within the ambient temperature range from 40°F to 130°F ass�ng

the greatest semiconductor variations with temperature.

Texas Instruments 2N1306(N.P.N.) and 2N1307(P.N.P.) germanium

switching transistors are used in all logical circuits. These transist.ors�

which have a minimum common-base alpha-cutoff frequency of 10 megacycles,

allow switching times in the .1 to .2 microsecond range. 2;

The basic building block of many of the logical circuits used with the M.3 is shown in Figure 401

-12v

-6v Rl IN67A

output

-,

_.�.,.. u _ Os co:t,lector input 2N1307 � mitter

":" R3

+105

Basic Building Block Figo 401

J ' This circuit design allows the 2N1307 transistor only two stable states,_ either conducting or non-conducting. When conducting, sufficient current is drawn from the base to ensure that the transistor remains 'saturated under normal loading. In this state, the emitter to collector voltage drop (VeE) varies from .1 to .2 volts depending upon ambient temperature and transis- tor characteristics. Saturated transistor circuits use fewer components

than unsaturated circuits and produce a stable output voltage for a vari-

able load. When switching a transistor off, a .1 microsecond delay is ob-

served which is partially due to the effects �f saturation. However, this

,delay is not large enough to cause difficulty.

In the non-conducting state-, sufficient current is - passed through

R3 from the +1.5 volt supply to ensure that the- base voltage is positive 'With respect to the emitter voltage. In this "cut off" state, the,collec­

tor voltage_is clamped to a level slightly negative of -6-volts by a

IN67A clamping diode. The clamping diode causes faster switching speeds 26

and produces a stable output voltage for a varying loado

A speed up capacitor Cs is placed in parallel with R2 to obtain the fast switching speeds required. The value of C varies from 50 pt. to s

300 pt. and is chosen empirically in each circuit to produce maximum opera- ting speedo

4.2 The Basic Flip-Flop

In. a digital computer a method must be available to store a digit while another part of the circuit examines it. This logical operation of remembering is performed by the flip-flop, a.two element active circuit which has two stable stateso A circuit diagram of the basic flip-flop used with the M.3 is shown in Figure 402. This circuit is assumed to be in state "I" when Tl is _conducting and T2 is non-conducting (cut off). In this state, output A is -6.3v due to the clamping diode and output B is approxi- mately -.2v due to the voltage drop across the saturated transistoro The flip-flop is assumed to be in the flO" state when Tl is cut off and T2 is conducting. In this case the output voltage levels will be reversedo

To be useful, a method must be available to set the flip-flop to either fll�' or nO". The diode gating network shown in Figure 4.3 is used to perform this task. To shift a "1ft into the flip-flop, C is set to a volts))

D is set to -6 volts and a 6 volt positive going pulse, is applied to Fl and F2 simultaneously. As Dl is initially reverse biased by 6 volts, the pulse has insufficient amplitude to cause current to pass to the base of Tl• However, initially D2 has only enough reverse bias to prevent current flow. The 6 volt pulse causes current flow through D2 to reverse bias the base. to emitter junction of T2• This cuts off T2 which in turn causes Tl to con­ iuct. Thus the flip-flop is set to the "1" state.

To set the flip-flop to the tWO" state, the voltage levels applied

�o C and D are reversed and a positive going 6 volt pulse is applied to Fl

and F 2. 27

,.------..- -12.'1

Output A

T.

IHl101

Fig. 4.2 The Basic Flip "Flop

r------__-.-__ IZV

D c

T300rf Fz Fig. 4.3 Basic Flip Flop Showing Input Gating

�0 �> I � I <�

" @�® ,.Fa. t (a) Single Shift Register Stage ,(b) Stage Shift Register Fig_ 4.4 Symbol ic Flip Flop Representation

Fig. 4'.5 Symbolic Counter Representation 28

Storage for an n bit number is obtained with an n flip-flop shirt register. As data become available from the memory one bit at a tim., serial registers which accept one bit at a time are used. This type of register is constructed by attaching the "lll·output (A).of stage

+. (m) to the "1'1 input (D) of stage. (m l) • Similarly, the "0" output

(B) of stage (m) is COhnected to the "0" input (C) of stage (m-+ 1).

All "F" terminals (Figure 4.3) are connected to a common bus. A posi­ tive going 6 volt pulse is applied to this bus to shift the contents of the register one stage to the right (from stage (m)-to stage (m + 1».

The schematic representation of a single flip-flop is shown in Figure 4.4(a). The flip-flop terminals B, C, .. D, and. F are shown A, F1 2 for clarity, but are normally nQt shown. The schematic of a three stage shift register is shown in Figure·4.4(b).

A flip-flop can accept data from more than on8 source if an addi­ tional pair of diode gates are added to the flip-flop for each additional source. When more than one source is used, the lN67A gating diodes are re­ placed by lN625 diodes which have a much lower reverse leakage current.

The source of information shifted into the flip-flop is determined by the pair of Fl, F2 terminals which receive the 6v positive pulse •

A counter can be made from the in 4.3 . binar,y flip-flop figure by connecting the terminals A to C, B to D, and Fl to F2• When a positive going pulse is applied Fl and F2 the flip-flop is caused to change state.

To make an n stage binary counter, the "1" output of stage m is corrected to F1F2 of stage m + 1. This will cause stage m + 1 to change state each time that stage m changes from the "1" to the "0" state. The schematic representation of a two stage counter is shown in Figure 4.5.

In tests at 500 Kc/s, a four stage shift register constructed with unselected components was found to operate for all voltage and temperature , ------��------

29

variations within design range. Bench tests show that this type of coun­

t.� will operate at frequencies up to 1 megacycle/sec.

The switching time for a flip-flop load,d qy one "and",gate_and

one shift register stage is .2 to .3 microseconds. The flip-flop is de­

signed to supply or accept a 1 milliamp load in either conducting or

cut off state, bu� a large capacitive load results in a definite show­

ing of switching time. In this case, an emitter follower is normally

placed between flip-flop and load to retain switchi� speed.

4.3 Basic "And" Gates

The "and" gate is a logical element which will pass an incident

signal only if all control inputs to the gate are at a particular voltage.

Any one input signal must not arfect the other input signals to the gate.

The gate, when open, must allow an incident signal to pass with minimum

del�J when closed, the gate must not pass any appreciable noise. The

gate output must be sufficient to drive several circuits.

The M.3 uses three different "and" gates; the transistor "and"

gate, the inverting "and" gate, and the diode "and" gate. The signal in­

put and the control inputs on any gate are interchangeable. Th� gate is

turned on when all control inputs are -6v, but is turned off if any control

input is Ov. Each gate has advantages and disadvantages, and the gat.

chosen for any logical operation is determined by the characteristics re­

quired. The circuit diagrams of the basic gates and their logical charac­

teristics are shown in Figure 4.6.

The transistor "and" gate shown in Figure 4.6(a) has a 50KSL

input impedance and approximately lKIL output impedance. This output im­

pedance lim!ts the number of cirouits which the gate can drive. Any number

of transistors m� be placed in p�allel with this basic gate to increase

the number of control inputs. The circuit is simple and causes no inver- 30

Characteristics 1 2 ..... Input Input Input 1 o.��-_

'--- '"v Input 2 IKA. Output

(a) Transistor "And" Gate

- 12,.'1

Characteristics Output Input 1 ..'----..... 1 Input -----,,, Input 2 Input 2

Output I'

(b) Inverting "And" Gate

Input 1 Characteristics

-- Input 2 --[>11---.--­ Output Input 1 0" .HII7A '------10" Input 2 o"U--U::-­ _12. ., Output O�� (c) Diode "And" Gate

Fig. 4.6 M.3 "And" Gates

)' ,

r t Fig. 4.7 Symbolic Representation of an "And" Gate

I •

1:'JII!'

., -,�

�.",,-J 31

sion of input signal. The propagation delay due to the turned on gate

is less than .05 r second, but the fall time of the output signal is de­

pendent upon the load capacitance. When the gate is closed, an incident

pulse on one input causes a noise output with I v peak amplitude. Less

than tv noise is caused on any of the input lineso

The inverting "and" gate shown in Figure 4.6(b) has a low input

impedance (8.2 Kn. in parallel with 200 pro ), but it is valuable as its

output impedance of 50 to 100JL allows the gate to drive several capaci­

tive circuits. Up to four inputs to the gate may be obtained by attach­

ing additional transistors with input biasing circuits in series with the

present transistors. The gate is useful in cases where an inverted out­

put is required, but requires more components than the previous gate.

Propagation delay and output rise time are each less than .1 microsecond.

When turned off, the noise output from an unloaded gate is less than .8

volts for a normal input signal. This signal causes less than 02 volts

noise on other input lines.

The diode "and" gate is shown in Figure 4.6(c). As it contains

no active elements, the gate output is directly dependent upon the input.

A power amplifier is normally required on the output to prevent input cir­

cuit loading. Advantages of the diode gate are low cost, small physical

size and ease of construction.

The schematic representation of an Handa gate is shown in

Figure 4.7. In this figure, the inputs (a) and (b) are represented by

arrows pointed into the circle. The output (c) is represented by an arrow

coming out of the circle.

, 'l;t Nift.\�;··�Gates

The "or" gate is a logical element in which a signal incident

upon any input will cause an output regardless of the state of the other .32

Characteristics l' 2 Input Input Input 1 �--u:- Output Input 2 o'--,r--­ u_."

II< Output

...

II (a) Transistor Or II Gate

-12,,,

1.5" K Characteristics '''10111 1 Output Input 2.Dot'f Input 2 Input 20utput

.. , ... y -----....__,

(b) Inverting "Or" Gate

Characteristics IH6'7A Input 1 Input 1 0..--, r-- 2 ---Di--+--- Input Output U-" .. '''1.7 " Input 2 o"--U=--- Output o.. ... � (c) Diode "Or" Gate

Fig. 4.8 Basic "Or" Gates

1'1 Inputl� ______.-- Ouput 2 . Input

Fig. 4.9 Symbolic Representation of "0r" Gate I

..)

33

inputs. However, an input signal does not affect 8IJY other input signaL

The gate must not cause appreciable delay to the signal and the output

from the gate must be capable of driving several circuitso The three

"or" gates used in the M.3 are shown in Figure 4.8.

The transistor "orll gate in Figure 4.8(s.) is most commonly used

in the M.3. This gate has a 50 Kn.. input impedance, 50 to lOO.a_ output

impedance, and produces a propagation delay of less than .05 microsec­

onds. The circuit causes very little increase in the tall time of the in­

put signal, but does not speed it up either. A signal into one input

of the gate Causes negligible noise on any other input.

The inverting "or" gate shown in Figure 4.8(b) is useful if the

output requires inversion with respect to the inputs. This gate has in-_

put and output characteristics similar to the inverting "and" gate in the

on state. An input signal,.eauses negligible noise on the other input

lines.

The diode "or" gate shown in Figure 4.8(c) is the simplest gate,

but as the gate contains no active elements, the output impedance is deter­

mined by the output impedance of the circuits driving the gate. If heavily

loaded, this gate normally has a power amplifier between the output and the

load.

The number of inputs to any of the "or" gates shown m� be in­

creased by adding more transistors or diodes in parallel with those already

" present. A schematic representation of a two input "or gate is shown in

Figure 4.9.

4.5 One Shot Circuits

The "one shot" or "delay multivibrator" is a logical circuit

which has one stable state and one quasi stable state. The output from the J

34

__ _I2.w � � �....

1.2.KCL

Output Input Characteristics Input 82A 0---u:--

__ __ I,'>v .__ ...._ ..__+ OutPut.�

(a) Negative Pulse Generating One Shot

I.SI

Output

Input Characteristics

-2.' . n Input _I�__J L-- ISI(A 4'lOA Output-,O�

(b) Positive Pulse Generating One Shot

Input � Output (c) Symbol ic Representation of One Shot

Fig. 4.10 Basic One Shots 35 one shot is normally at the long term steady state level, but when trig­ gered, the output changes to the opposite state where it remains for a length of time determined by the discharge time of an R-C circuito

One shots are used in the M.3 to provide timing waveforms with consistent pulse amplitude and width and also to provide adjustable de­ lays. The delay consists of a one shot coupled to an A.C. amplifier to produce an output pulse with leading edge coincident with the trailing edge of the one shot output. The time elapsed between input pulse and out­ put pulse can be adjusted by varying the one shot pulse width.

The one shot shown in 4.10(a) is triggered by a negative going signal at approximately -3 volts. The output transistor is normally con­ ducting, producing a steady state output of 0 volts. However, when the input stage is triggered, the output transistor is switched off for a length of time determined by the time constant �CI. During this time, known as the pulse width, the output voltage is -6 voltso

The one shot shown in Figure 4.l0(b) is triggered by a positive going signal at approximately -8 volts. The output stage of this one shot is a normally conducting transistor with approximately -10 volts collector voltage. When triggered, the output transistor is switched off and the collector voltage changes to approximately -2 volts. The pulse width is determined by R2C2• As this one shot is normally used for delay applica­ tions, the trailing edge switching time is shortened by the use of an oversized speed up capacitor (300 p +. ) in parallel with the 5.6 K..n. biasing resistor. This has.the disadvantage of slowing the leading edge switching, but as this edge is not used, this is of no eonsequence.

D.C. triggering has been used on the input to both one shots.

This produces a fast switching output waveform for a slow input signal.

In order to ensure that the one shot has �wo stable states, one with the output transistor conducting, and the other with this transistor switched off, R should be no more than 56 K.a.. and 0 should be no less than 180 pt..

Both one shots have output impedance greater than 1 Kj2. In cases where the one shot is to be loaded b,y a capacitive load, an emitter follower is usually placed between one shot and load. Otherwise, the

switching time of the leading edge would be considerably slower than de-

sirable.

4.6 The Inverter

The purpose of the inverter in a digital computer is to emit the opposite logical voltage level to the incidendent voltage level. In the M.3 the inverter must emit -6 volts for 0 volts incident and 0 volts for -6 volts incident. A similar circuit to the inverting "and" gate is used to perform this task (Figure 4oll(a».

-/2,.,

'31' I\...; :>

input (b) logical symbol

(a) inverter circuit

Fig. 4.11

4.7 D.C. Delay

It is occasionally necessary to delay a D.O. voltage level change by a short time (< 2 microseconds). In some eases this delay must be obtained without appreciable slowing of the D.C. level switching 37

speed. The one shot A.C. amplifier delay cannot be used in this �pli-

cation as a D.C. level output is required rather than til. pulse. A simple

circuit has been designed to perform this task in the M030 This circuit,

Which delays a Ov to -6v voltage level change for a length of time vari-

able from. to sec , is show. in The time can be 5 2,fA- , Figure 4.120 delay

controlled the size of the 0 0 A or dravbaek by varying capacitor T maj

of the circuit is that a 10% increase in the input voltage change causes

the delay time to be decreased by approximately 10%.

-12.'"

-6..- characteristics 1.2 K.n..

0"

input -I."

• output O�·

6.B KJ1. output (pll input

CT

...

+-I.'r ., 1[!J symbolic representation

Figo 4.12 Short time D.C. delay element

4.8 A.C. Amplifiers

A.C. amplifiers are required in a computer to differentiate

waveforms. Normally, the M.3 uses the basic amplifiers shown in Fig­

ures 4.13(b) and (c). However, in cases where an inverted output is re-

quired and low output power is satisfactory, the amplifier shown in

. - Figure 4.13(a) is used. The input impedance of the amplifiers is approxi­

mately 300 p [ in series with 3.3K.n... The output impedance from ampli­

fiers (b) and (c) is approximately 1.5K..n.. ; thus an emitter follower is

required between amplifier and load for capacitive loads. A 02 micro- )

3B

loK.I1. Characteristics

- Output Input 4"1 '-h Output I lin...

.,.

(a) Inverting A.C. Amplifier (Negative Trigger)

-- �_12.

Characteristics Output Input Input ov''---_ __.I_h

(b) A.C. Amplifier (Negative Trigger, Negative Output)

Characteristics Output 0 Input Input �..... I_�

Output� -IZ. -I � 2 ,,:� . .____._----_.___,2" ....

. \

(d) A.C. Amplifier (Positive Trigger, Positive Output)

Input � Output (d) Symbolic Representation of A. C. Ampl ifier I I

Fig. 4.13 Basic A. C. Ampl ifiers ------

39

second del� is obtained between input voltage change and output pulse,

but this normally is no problemo

4.9 Emitter Followers

The emitter follower is not a logical circuit, but as it has

a high input impedance and a low output impedance, it is very important

in the construction of a digital computero The emitter follower is nor­

mally placed between circuits required to emit fast pulses and their

loads if the load is capacitive or requires a large driving currento

The Mo3 uses three types of emitter followerso In applica­

tions. where both the leading and the trailing edge Qf a pulse are impor­

tant, the "complementary pair" emitter follower (Figure 4.l4(a» is usedo

The output impedance from this circuit, when driven by a logical circuit,

is 50 to 100Jl. This low resistance discharges any capacitive load C

very quickly, preventing slowing of both leading and trailing edges of a

pulse.

In caseS where either the positive or the negative going edge

of a circuit output ia i�o�tant but the opposite edge is not, the emitter

followers shown in FigureSc 4o,�(b) and (c) are used;

The NPN emitter follower has approximately 50JL output impedance

for D.C. conditions and positive going edgeso However, when the input to

the emitter follower goes negative, the transistor is cut off and the

load capacitance C must discharge through the lK!l resistoro This re-

sul,ts in an exponential volt.age decrease. As the leading edge of a pulse

.s usually important, the NPN emitter follower is normally used with cir­

:uits which emit positive going �seso

The PNP emitter follower has the opposite characteristic and ex­

.ibits a 50.!t. output impedance for DoC. and negative edges, but approxi­

ately lK..Cl. output impedance for positive edge s , This emitter follower

___,------40

Characteristics

o· Input Input

OutPUf'--�__1_4¥

(a) Complementary-Pair Emitter Follower

Characteristics Input Q.----� �--� Input Output ,- I Lc." -L I K.n. C I Output I ov_----,\_---_.-j,,,I' ..,j.- -Ih

(b) N.P.N.i Emitter Follower

Characteristics Input Input Output 0", I __l_ c -,- I Output ..L ...

(c) P. N. P. Emitter Follower

Fig. 4. 14 Basic Emitter Followers

. __...... •.-._------,J

is normally used with circuits which emit negative going pulses.

4.10 Neon Driver

In the M.3, neons are used to indicate the contents of the

accumulator, the shift register and the control register. The circuit

shown in Figure 4.15 is used to drive the neons. The input to the driver

is taken directly from the alA side of a register stage. Input impedance

to the driver is appr.oximately 1005 K.Q. One milliamp DoC. is passed

through the turned on neon. When switched off, the transistor leak�g�

current (ICBO) bypasses the neon through the 270 K.J'1.. resistor in paral­

lel with it.

ELDEMA 210 K.D-

input

5".61(4

Fig. 4 .. 15 NeonDriv�·�cuit \jr ;f1iII�-�Q�t ...

4.11 Circuit Layout Techniques

All logical circuits are moun"\:i,d on 3t" x 8", 22 contact, plug ».... ": ;:\:' . ·'i·.�· in Veroboard. The Veroboard card was chosen as it permits easy circuit

and assembly, allows considerable freedom in circuit layout is quit. in� . . I expensive. The card size was chosen mainly for economic reasons.. A 'small

�"� II • __ �

-_._-- ..------_..... I ....��------�...... --....------... _)

card containing one or two logical circuits simplifies construction and

testing, but the expense of the large number of cards and sockets re-

quired is not economically justifiable. The eight i�ch long card used

allows at least four logical circuits to be mounted per card. Card

servicing is simplified by a plug in test jack which permits easy ac-

cess to all components mounted on the cardo

Each card in the M.3 is stamped with a drawing number. This

drawing, which is shown in Appendix A, gives the location and descrip-

tion of all components and wires on the card. The destination and color

of wires connected to any ot the 22 contacts via the plug in socket is

also shown. A small logieal diagram on the top of each drawing shows

the logical circuits and internal connections on the card and also the

socket pin numbers of all accessible input and output points of the logi-

cal circuits.

The logic cards are mounted in a 76 card rack. The drawing num-

ber for each card is stamped on the raek to ease servicing. Card looa-

tions are chosen to keep inter-card wiring to a minimum length. ..J 43

5. THE STORE

The M.3 store consists of a magnetic drum and the circuits re-

quired to read and write information in a specified location. To defini-

tely locate each po�ition on the magnetic drum, timing pulses are genera-

ted from engraved tracks on one end of the drum. The operation of the

M.3 store will be described by considering the following constituent units:

the magnetic drum, the counter and coincidence senser, the head switchp

the block switch and the read-write circuits.

5.1 The Magnetic Drum Memory

The magnetic drum consists of a 9.75 inch diameter aluminum

alloy cylinder which is driven by a small induction motor at 3425 rep.m.

The outside surface of the cylinder is precisely machined and is coated

with a thin homogeneous layer of ferrous oxide and plastic. One hundred

and twenty eight recording heads are spaced on individual tracks along the

side of the cylinder. The recording heads are spaced approximately .0005

inch from the magnetic surface of the drum.

Three engraved soft iron timing tracks are mounted on one end

of the cylinder. The first track is engraved with a single slot. This

slot generates a single "drum marker" pulse in a read head each drum revo- )

lution. The second track is engraved with thirty-two equally spaced slots

to generate thirty-two "word marker" pulses in a read head for each revo-

lution of the drum. The third track is engraved with 1280 equally spaced

slots (40 between each pair of word markers). The output from the read

head on this track is amplif�ed to form the basic 75 Kc/s continuous clock

of the computer. In many �f the basic M.3 operations, groups of 32 pulses are re- I quired. These pulses are gated from the contanuous clock and must occur at

�1'_ a constant location in ea.ch wordr�$tarting approximately 5 ¥croseconds -

...)

44

after the word marker puls••

It was initially planned to gate out groups of 32 pulses from

the continuous clock by placing two recording heads on the word marker

track. With this method, a flip-flop, known as the "emit flip-flop", is

set to unity by a delayed pulse from the leading word marker head, when

a group of pulses is required. When in this state, the emit flip-flop

opens a gate to allow the continuous clock pulses through. The second

word marker head is adjusted so that the word marker engraving passes un­

der this head immediately following emission of the thirty-second pulse

zeros from the gate , The pulse induced in the head the emit flip-flop

and thus turns off the gate after allowing only 32 pulses to pass.

This method could not be used with the M.3 as the word marker

engravings were not milled in a constant position with respect to the con­

, tinuous cloek engravings and the spacing between continuous clock engrav­

ings is not constant. These variations made it impossible to gate out a

set of 32 pulses in each word location.

The system used to generate timing pulses in the M.3 does not

use the word marker engravings, but instead obtains word marker pulses by

counting the clock pulses. This method has the advantage that the word

marker position is always constant with respect to the clock pulses.

Another advantage is that, by generating a 'Word marker pulse after every

twentieth clock pul�,sixty-four 'Word locations are designated per drum

revolution. By doubling the freque�cy of the clock pulses, the capacity

of the memor,y is increased from 4096 to 8192 words and the calculating

speed of the computer is increased by a factor of two. Outputs from the

counter control the opening and closing of the gate which emits groups of

32. pulses, thus giVing reliable operation yet eliminating delicate head

' adjustment: ..J

45

5.2 The Counter and Coincidence 8enser

The counter and coincidence senser, shown schematically in Figure

5.1, is responsible for addressing all word locations and also for the gen-

eration of timing pulses for the computer.

The single pulse per revolution induced in the drum marker head

is amplified by al and is shaped by a one shot to zero the word marker

counter and bit counter. This ensures that the counter always gives memory

locations on the drum the same address each time the computer is switched on.

To ensure reliable operation, the zeroing pulse should occur approximately

three microseconds after a clock pulse. This allows approximately ten

microseconds for completion of the zeroing operation before the arrival of

the next clock pulse.

Pulses induced in the bit marker head are amplified by &2 and shaped by 87 to form the basic clock, a 75 Kc/s array of negative-going,

one microsecond wide. pulses.

The clock pulses are inverted to cause the least significant stage

of the bit counter to count. This counter could count to thirty-one, but

on the arrival of the twentieth pulse, a positive-going word end marker

pulse is generated by g4 which zeros the counter and advances the word mar­

ker counter by one. A del� is placed between the fifth counter stage out-

put and the input to g4 to prevent spurious outputs on the sixteenth. count.

As the word location counter is advanced one by each word marker

pulse, the counter always contains the address of the word location available.

The six stage counter counts from zero to sixty-three and is zeroed by the

sixty-fourth pulse. In normal operations, the counter is zeroed by this

pulse approximately three microseconds before the arrival of the zeroing pulse

from the drum marker head. As the counter is already zero, the zeroing pulse

has no effect.

"1 , I ,J-

46

DRUM MII'UGR HE" III)

5.. ':.12- CDN ITI NUO US c: LO C \(

Figure 5.1 Counter and Coincidence Senser (M.? Unit �)

\ I ,)

47

The 75 KC/s clock supplies only one half the number of bit mar-

ker pulses required per word location. A frequency doubler composed or

85, 88 and an "or" gate is required to generate the required number of bits per word. Inverted clock pulses trigger 85 to generate a set of

positive-going 6.8 microsecond pulses (one half the average period of the

75 KC/S clock). 88 is triggered by the negative-going edge of these

pulses to produce 1 microsecond negative-going pulse similar to the clock

but delayed by one half period. This and the clock are merged by an "orlt

gate to form the 150 Kc/s clock used by the rest of the computer.

In information shifts to or from the store, the address of the

word location involved is stored in a portion of the control register. A

continuous comparison between this address and the address indicated by

the word marker counter is made by the coincidence senser circuit shown

in Figure 5.2. This circuit normally emits a 0 volt level which holds

gl in the switched off state. However, when coincidence occurs, the out­

put voltage switches to -6 volts allowing pulses to pass through gl if an "M.emit" signal-is present.

R e- '"I.1Kn

S � 2,"'1301

output

-Iav

WORO MARK!:R pUl-ses Word Marker Counter

-

_ " _li'i,,,. 5.2 Coincidence 8enser Circuit

L The one shot 81 and A.C. amplifier a3 produce a test pulse Which is delayed from the word marker pulse by a ti�e equal to the output pulse width of 81• The delay is inserted to allow the coincidence senser in­

put to gl to settle down after the counting impulse. Otherwise spurious operation might result.

The test pulse tests gl and g2. If a transfer of information

to or from the store is required, the M.emit line is activated. In

this case a pulse will pass gl only if coincidence is sensed. If 32 pul­

ses are required for multiplication or division, the "instantaneous emit"

line is activated. In this case, as coincidence is not required, the

first test pulse generated will pass through g20 A pulse through either

gl or g2 sets the emit flip-flop to unity. When the emit flip-flop is set to unity, the double frequency

clock pulses are allowed to pass through g50 To ensure that the gate allows only 32 pulses to pass, g3 zeros the emit flip-flop a short time after counting the seventeenth 75 Kc/s clock pulse. The short time d.l�

produced by 82 is required to ensure that gs will not close before the complete emission of the thirty-second pulse. A del� is placed between

the output of the fifth counter stage and the input to g3 to prevent spur­ ious output from g3 when the bit counter changes from fifteen to sixteen. The set of 32 pulses emitted from gs is known as the "32 imme­

diate" or"32 lMM" pul.sea, Their main use is as timing' pulses when writing

information on the magnetic drum. To read recorded information from the

drum, a set of pulses are required which occur approximately three micro­

seconds after the beginning of each of the "32 IMM'pulses. These "strobe"

pulses are generated by triggering the del� one shot 86 by the leading

edge of each "32 ]MMD puls•• n The trailing edge of the 86 output triggers

the A.C. coupled pulse forming one shot, producing the required set of

, _/ _ t

- :-

..;,.,.-.-._-­

.",._ --

l f- 3/'$ DRUK �------MARKeR �. 'PRE,e;I

WORD /'1 I( lEt? n«

A3 OUTPUT �3.�i+-= /"s

- j,JrpUT I I I

. - - EMir FLIP-FLoP

k'C./s IS"O ·C LOCI(' nmnnj

32. IMM

'STROBE

..J ,_ I 2..4/,� -11+1"rs ---, \l 32

nnnnmnmnrnTlflnmnmllfTIlJ. �I- Irs OP. COMPo f'OL.c:,c � -o Figure 5.3 M.3 Timing Pulses ;0

2.5 microsecond pulses.

To shift information from the read circuit to registers within the arithmetic and control units, a set of I microsecond pulses are re­ quired which occur 1 microsecond after the trailing edge of each strobe pulse. These pulses, known as the "delayed 32· or" V 32" pulses, are generated by triggering 811 from the trailing edge of each strobe pulse and by triggering 812 from the trailing edge of the 811 output.

An "operation complete" pulse (opo compo pulse) must be gener­ ated by the store following emission of each set of 32 pulseso This pulse informs the control and arithmetic unit that an order or a por­ tion of an order has been completed. Zeroing of the emit flip-flop triggers the d.l� one shot S90 The trailing edge of the 89 output triggers an A.C. amplifier which produces the required opo compo pulse.

The delay circuit must not emit the opo compo pulse before emission of the thirty-second V 32 pulse. Also the pulse should occur approxima­ tely 3 microseconds after a clock pulse.

In manual operation, the operation complete pulse is generated by operating a lever key. switch. Contact bounce on the output from the switch is removed by a 10 millisecond one shot. The trailing edge ot the one shot output triggers an A.C. amplifier to produce the manual pulse. The outputs from the manual and automatic 0po compo pulse sources are merged by an "or" gate which passes the pulse to the rest of the com- puter.

5.3 The Head Switch

The magnetic drum used with the M.3 has 128 recording heads.

The computer must be able to address any one of these heads to store or receive information. To do this, the heads are divided into 16 blocks, each containing 8 heads. ..

51

Heads in the first block are assigned track numbers from 0000

to 0111. A head in this block may be switched on by placing the track

number of the head in either the "X" or "Y" address of an instruction.

Heads in this block are continuously available, and are independent of

the block switch.

In the remaining fifteen blocks, the heads in each block are

assigned track numbers from 1000 to 1111. To address a head in this

group, the block containing the required head is first switched on by

a block switch instruction. The head can then be addressed by placing

the track number in either the "X" or the "Y" address of the instruc-

tion as usual.

The head switch is composed of three main sections; a storage

register which holds a track number as long as information is required

from that track, a diode matrix which produces a single output for each

combination in the storage register and a transformer-symmetrical tran-

sistor gate array which is controlled by the output from the diode matrix

and which turns on the head or set of heads required.

The storage register must accept inform�tion from either the

"X" or the "Y" track location in the. Control Register. The "X" track

location, stored in Control Register stages 1 to 4 (CoRo 1-4), is shifted

into the storage register by a positive pulse from a4 (Figure 504). This AoC. amplifier �s triggered by the negative change in output voltage of

the control fli�flop (CoFoF.) when the C.F.F. is set to unity. The "I"

track location, stored in C.R. 11-14 is shifted into the storage register

by a IIy diode pulse" from the control.

Complementary pair emitter followers are placed on each storage

register output to prevent register loading by the diode matrix and to

preserve the fast switching time of the register flip-flops.

� I ...

__y _ ,--",

y. DIODE C. F. F PUlSE 1 C.I\'., c.ez.". c: R c.R.1- C .R.II I C.�.IZ. Ie ."..... 13 '1.3 C.R.'" 4 .l...

I CD 0 0.. STOI:A("E ll�G.Ili.T"R., .. S.�.I Teo ... VI �. .... 0 EM ITTE.1it FoL.'-Ow�( •••• :r �

:!] D ..., 0 CO C ..., -. CD ....

OJ ...... -rz» 0 . ..., � I , CD 0 ",,,,0 0.. 0 �8T '; 'r 'r '; --,.1 0 -12.�-AJ\/' I I I I I I I I '\IV'-r--I 0 0 8.Z.K.n.

�,.S''V

----__/ COI.JNE<'Tt:D HJ f"1'\f(ALLEl ""TH Ovrf'UT" FROM OTHEI( HE A 0.5 IN THe: TO 'DIODE 6I1TE� 000' TO 1111 IUOC.�.

\.1l l\) 53

A diode matrix decoder translates the four bit track address into a single output from the sixteen possible. Each output from the matrix is generated by a four input diode nand" gate similar to that shown in Figure 5.4. The output voltage from the "and" gate is nor� mally 0 volts. However, when all inputs to the "��dn gate are -6 voltsg a -6 volt output is produced.

Each output from the matrix is directly connected to an in­ verting amplifier whose output drives the transformer-symmetrical tran­ sistor gates. A 0 volt input to the amplifier holds the 2N1307 transis­ tor in)the switched off state, producing a -12 volt output. Howeverp when the input to the amplifier is -6vg the transistor is saturated, causing the output voltage to switch to approximately 0 volts.

The amplifier outputs are directly connected to the inputs of the transformer-symmetrical transistor gates. The gates consist of a

Ferroxcube 3C pot core transformer with an eight turn primary winding connected to a memory head output and a twenty-six turn centre tapped secondary with the terminals of the centre tap connected to the collec­ tor_and emitter of a 2N594 NPN symmetrical transistor. The secondary outputs from all gates in a block are co��ected in parallel to the pri­

of When a block is turned on a mary winding the block swit.eho_ , -1.5v level is applied to' the centre tap of the block switch primary winding.

To turn on, a particular gate in the block, a 0 volt level is applied to the base of, the symmetrical transistor through a 56!L resistor. This causes the transistor to be forward biased and current passes through the transistor and transformer windings to the -1.5v level. When in this state, an A.C. signal input to the gate from either direction finds a low impedance path (approximately .751L for signals from the head) due to the saturated common base amplifier, and passes through the gate with very --- y

54

little attenuation.

The remaining seven inputs to the gates in a particular block

are held at -12v by the diode matrix decoder. This reverse biases the

symmetrical transistors in the gates by approximately 10.5 volts. In

this state, the transistors appear as approximately a 200 K� resistance

in parallel with a 26 pf capacity. The impedance ratio of a switched

off to switohed on transistor at operating frequencies is approximately

5 x 104: 1. This results in a gate having a very good signal to noise

ra.tio.

504 The B100k Switch

The block switch nust switch on one from a total of fifteen

available blocks. The block switoh instruotion triggers a1 (Figure 5.,5)

to shift the b100k address stored in C.R. 1-4 into the b100k switch stor­

age register. A three microsecond delay on the switch instruotion allows

the positive shift pulse from 8.1 to also be used as an OPe compo pulse. The delay allows the C.FoFo to settle to unity state before being reset

by the OPe compo pulse.

To prevent storage register loading, emitter followers are

placed on all outputs to the block selector diode matrix.

The diode lIlatrix consists of fifteen 4 input "anct" gates. The

output from each gate drives an inverting amplifier similar to that used

in the .head switch. Incorrect combinations into an "andU gate oause an

amplifier output of -12 volts. As this voltage is applied to the base of

a symmetrioa1 transistor with emitter and collector held at approximately

-1.5 volts, the transistor and thus the block input is switohed off.

When a diode "andU gate is turned on by the storage register,

the output voltage from the inverting amplifier switches to 0 volts.

This saturates the transistor in the transformer-symmetrical transistor

, ------.,-----

BL.CI('I< SYI} 'TC-It OROEr: I C.Ii:.2. C.Jt3 C.R.... "l.. C,R, .

� 0 0 7\

Vl � :;: 0 :r EI"I'TTE.r? FOLL.hJE

0 l.3K" 0 -= 0

0 -t/.'S"V

6L.O('k oo o o o vT PI) 1"

To OloDE GATES 0001' TO 1110

\Jl \Jl 56

HI!:AO :lw ITCH AMPLIFIER OVTPU'TS

/ o I " Z '3 -4 5" 7 8 , 10 1/ IZ 13 1+ IS:

I o 11£1'10 Y!C=: 000

o 1i£'''0 OQ' _/� y!c:=: <:ONT'. PrVIl'k. j/"'"" aLoC/(

l o Kt"'O �11c=: ,"I

o ".,,0 �rc::: ,II

�G:�O C.IRCUIT Oil? I) H"E.�I) 000 RE6.n I'r1"� C:llc=� INHII3IT I Q. HEAD 00' _/ _�IIc=�

w II. IrC::: BLoC):' !./" C.,RCU IT 000'0

:I� I) "C;itD -1.5V I �11c=�' 10

c hERO _�IF=T, '"

"""TCH 0":' oc.1< 0000 lr> 1�1I1

o 1If"IID �IF=� 000

o ltell!)

.. , _....("" �11c=� 131..0'K 0001 _,v- .

o Helll) �IF=� 110

o H!:"ftD �llc=� "I

s WITCH ooJ th. OCI( 0001 4> �II� � " ,

cOj,Jf')E:c.rEO INPUT TO ,-0 OUTPUTS F'ROM e i e c x s 0010 0010 TO ilia 1J1..01:.K'S TO 1110

Figure 5.6

Head Switch - Block Switch - Read,,:,Write Interconnections �-- J

57

gate, causing the block to be turned on.

When a block is switched on, -1.5 volts must be applied to the

prim� winding centre tap of the block switch tran.sformer to supply the

biasing level for the head switch gates (Figure 5.6). However, if -1.5

volts was applied to the centre t.p· of all fifteen block inputs� ad- - I'lL;.

dressing a head between 1000 and 1111 would pass a 25 milliamp saturating

current through the head addressed in each of the fifteen blocks. This

would overload the head switch. To prevent overloading, +1.5 volts is

applied to the primary winding centre tap of all unwanted blocks. This

reverse biases all symmetrical transistors in the fourteen blocks by a

minimum of 1.5 volts, sufficient to stop D.C. current flow, but insuffi­

cient to prevent passage of the 16 volt peak to peak write signal which

must be stopped by the transformer-symmetrical transistor gates in the

block switch.

The centre tap voltage level is generated by a 2N1306 inverting :j amplifier (Figure 5.5). When -12 volts is applied to the amplifier as is

the case when a block is switched off, the 2N1306 is cut off, producing

a +1.5 volt output. When a block is turned on, the 0 volts applied passes

sufficient current through the 2.7K resistor to saturate the transistor,

producing a -1.5 volt output.

5. 5 The Write Circuit

Information is stored on the magnetic drum surface in the form

of small magnetized elements. These elements are magnetized by passing_

a current pulse through a head for a length of time less than 1 bit period.

The amplitude of this pulse must be sufficient to allow removal of old

information from the drum by recording. new information over it.

Information is recorded in the M.2 by current pulses which re-

semble the positive portion of a sine wave. The "1" is distinguished 58

from the "0" by passing the current pulse through the head in the oppos­

ite direction. This writing technique was tried on the Mo3, but record­

ing an unbalance of nlfts or no"s resulted in an operating point shift

of the transformer network between the write circuit and the head.

The operating point returns to the normal level, but the return requires

a length of time greater than the recovery time between two word loca-

tionso This prevented reading information immediately after recording.

The use of this system would have made programming more difficult and

reduced operating speedo

The use of double pulse writing was adopted to overcome the

'D.Co shift problemo The current pulse used in this system resembles a

complete cycle or a sine wave and has a peak value of 1 amp in each

directiono Again rillD is distinguished from lion by passing the current

pulse through the head i.� ;the opposite directiono Adjustment of the

current pulse shape allows DoCo level shift in this system to be prac-

tically eliminatedo

The write circuit is· composed of"'three main parts 1)' the write

gate, the pulse shaper and the power amplifier. The write gat. (Figo

507) translates information from the accumulator or the shift register I

into a set of positive pulseso A pulse on one output from the write

gate �ndicates a "1" is to be recorded, a pulse on the other line indi­

cates a "0" is to be recorded.

The write gate is activated by an order to record the infor­

mation stored in the accumulator (A(n) or the information stored in the

shift register (R(n» in_memory location "X"o To record an n bit word,

where n is 32 or less, C6 must in!tially be set to .32·...no

The 32 IMM pulses emitted at the "In word location test g60

This gate, controlled by C6, allows the first n pulses to passo The A(n) 59

ADVANLE

...IIM. .,. A � �'l • '0 "oL '1" �ID"

A('I) __-----( '\.

32. __ \t1t1._-+- " ."...,.

Rl-v --1-_----< 1. WI\I'I'1t "0'

SillFT

"I'sIPC "O"SIPE. R 3Z '''' H 11\11"

(a) Write Gate Loqic

�------__r--_IZ

Write Gate (b) Circuit (96, 97, 9a, 99, 910, 911, 912) Fi9ure 5.7,

Write Gate'· 60

instruction opens g7' allowing the 32 IMM pulses to test g9 and gl00 A "1" stored in the thirty-third stage of the accumulator at the arri-

val time of an IMM pulse causes g9 to emit a positive pulse. A "0" in this stage causes glO to emit a positive pulse. The A(n) instruction

also opens g14 to allo� strobe pulses to pass. These cause 06 to count, shift the accumulator contents to the right and shift A3l to both A32

and A33.

To record information from the shift register, the R(n) in-

struction opens gs and g13. Immediate pulses through gg test gIl and

g12' causing positive pulses to be generated on the appropriate output

lines 0 Strobe pulses passing through g13 shift the shift register to

the right and cause 06 to count.

The outputs from g9 and g12 are merged by an "or" gate to form the write "1" output. SimilarlYll the outputs from glO and gIl are merged

to form the write ItO" outputo

The read amplifier has a low input impedance to the large sig-

nal generated by the write circuit. To prevent write circuit loading,

the presence of a write order generates a -12 volt "rend circuit inhibit"

output. When a write order is not present, the 0 volt output allows nor-

mal read circuit operation.

The positive pulse generated by the write gate must be shaped

to produce a sinusoidal current output from the power amplifier. When

the write gate emits a write "1" pulse, this pulse passes directly through

01 of the pulse shaper (Figure 5.8) to cause current flow from the writ.

"I" power amplifier to the primar,y centre top. The trailing edge of the

pulse from the write gate is differentiated by 8.2 to trigger S2. The output from S2 causes current flow from the write "0" power amplifier to

the centre tap 0

, 61

Pul se Shaper Power Amplifier

1111�-----"" TO .GL.OC" -12v f-- -+1.5'11 "''''TCH

� ..

--���------��--��� j W�IT� ·0'

Figure 5.8 Pulse Shaper and Power Ampl ifier logic

" _� �-I2.v -I�

3Q. "f I •• "

I _ r-0 'N"IIT'

Figure 5.9 Write Circuit Power Ampl ifier

.------62

When the write gate emits a write "0" pulse, the "0" power

amplifier generates the first portion of the current pulse and the "1"

power amplifier generates the second portion.

As both "1" and "0" inputs to the power amplifier cause cur-

rent flow toward the primary centre tap of the output transformer, the

secondar,y current generated b,y the "1" power amplifier flows in the

opposite direction to the current generated by the "0" power amplifier.

As the head is an inductive load, the output current is approximate�

sinusoidal.

Operating point shift is removed by first adjusting the pulse

width of 82 so that no DoC. shift occurs after writing 32 nl"s. Then the pulse width of 81 is adjusted so that no D.Co shift occurs after writing 32 OIS.

The power amplifier aircuit . is shown in Figure 509 � The

2N1999 transistors which supply the write current are normally cut off

by the +1.5 volt output from the complementary pair emitter follower.

The input to the emitter follower. is produced by a normally s�turated

' 2N1307 transistor. A positive-going. input pulse switches the 2N1307 off" I

causing its output voltage to switch to the clamped -6 volt level. This

sa.turates the 2Nl999-:transistor causing current flow through the output. �,' ."

transformer winding to the centre tap.

A -105 volt level is applied to the secondary winding centre

tap_of the output transformer. This supplies the biasing level,for block

switching and for the read amplifier inhibit circuit (Figure 5.6).

, rj)

63

5.6 The Read Circuit

To transfer information, from the store, the small voltage in-

duced in the recording head must be converted to a form acceptable to

the logical circuits. This conversion is performed by the "read circuit";

a high gain amplifier whose output, when sampled by strobe pulses, sets

the incident digit flip-flop (I.FoF.) to the appropriate state

(Figure 5.10).

The signal induced in a recording head contains two basic fre­

quencies, 75 Kc/s for alternate liS and O's and 150 Kc/s for continuous

liS or Olso The signal level from the 1 microhenry head is approximately

350 microvolts peak to peak� however a 1�3.25 transformation at the head

switch and a lslO transformation at the amplifier input transformer ca�ses

the amplifier input to appear as 9 millivolts from a 1 millihenry source.

The tTansformer=symmetrical transistor gate input to the ampli-

fier is switched off during writing to prevent writ. circuit loading and

extreme amplifier saturation.

The. amplifier must not produce a large change in phase shift

between 75 Kc/s and 150 Kc/s or the samp�ing circuit will not operate.

Phase lag due to the inductiv� source impedance (1 K12. at 150 Kc./s)_is

less than 2 degrees as the input impedance to the amplifier is greater

than 50 Kn. Phase change due to �he amplifier in the 75 to l50_ Kc/s

range is reduced by non-linear negative feedback. The effect of power

supply_n9ise is reduced by an R.Co filtered supply used with the pre­

amp�ifier. The amplifiers low 60 cycle/s gain eliminates problems due

to 60 cycle pickup.

The sampling circuit requires tvo inputs; one input the inverted

image of the other. This is obtained by placing equal resistors in series

with the collector and emitter of the output transistor and connecting to

_ -·I . ------.'------!I

'-

PRf. POWE./t AMPLIf'IE� SAMPLIN� I.F.r. r: CIRCUIT.� / \ I·M""'" \ I \ t � �------�-/��

-:-

330n

� 2"'�'i+ ��O.ll. � "'lOOT I _ _ _ 2.N1307 0.. i} ,� --,____C � � looo,.f �IIE., CD () :;. OJ o • - c 0 :;'. IK.n. � J: Is-orf J.9KA � I'r.f 3301l.

�·I./(A < � ..L S'�ktlT 'kyJ "IOrt C 32 C 3Z 2� IS'O.n. '"1' 1'0"

-1'l.1I ;- I.5v �TRO�l!: C3Z-".fF.

�I";

I"'�T". ,.MIT � 1

8 $-

7

6

+-t ±t

- --<+ -t-t-t- � ,

- - + j+I�� >-t-::+-l::++....-H-, :I�:!:t-t±i+j:'++t:�tjm:u:tt.J_tt++:j::'-H'�::+tt�:j:Hrn-+:j:-ltl�+:j::'ti""'+'i:l=1+m+1_l i ;.t-r ,-++-t-H "H-+H

I ' i

l

'0 °0 '0 0 e .., <;I- 11\ ., 0 ,...... , �. lL ?'E 7 " If 66

both collector and emittero

Points A and B of the sampling circuitg which are connected to

the amplifier outputs by 1000 p£ capacitors, are normally clamped to a

slightly positive potential by lN273 diodes and the 2N1306 base to col­

lector strobe from reverse bias junctions. Negative-going pulses g15

the lN273 diodes allowing A or B to follow the input signal to a nega­

tive volta.geo The negative level on A or B a.llows the a.ttached 2N1306

transistor to operage as an emitter follower and set the IoFoFo qy

applying a negative voltage to the direct coupled trigger transistoro

In eases where the �cle register sets the IoFoFo, the insto

emit signal from the arithmetic unit prevents strobe pulses from passing

through g15 and shift pulses from the cycle register (a portion of the arithmetic unit) shift the contents of the thirty-second cycle register

stage into the IoFoFo

'1 I �_ 67

6. OVERALL SYSTEM DESIGN OF THE M.3

The Mo3 consists of two sections, namely control and arithme- tic. Much of the logic is identical with that �f t�e M.2. However, an • additional shift register (the cycle register) has been added_ to the arithmetic unito In the Mo2, division is an operation which requires an entry and an exit subroutine; in the Mo3 this division has been replaced by a unit which is completely automatic and does not itlvolve manipula- tion of the signe of the interacting n�berso

6.1 The Control

The control consists of two units, the control network and the control register. Control is based upon the state of a single flip-flop, the "control flip-flop" (CoF.Fo)o When in the "On state, the C.F.F. causes a new instruction to be shifted into the control register; when in the "I" sta.te, it causes the instruction to be executedo

The control register (Figura 6.1) is a thirty-tvo stage shift register which holds an instruction until it is executedo The composi- tion of the instruction is as follows�

CoRo l-4� "XU track location

CoRo 5-10, "XU word location

C.Ro 11-14, ttyu track location

CoR. 15-209 tty" word location

C�R. 2�-25.p order

C.Ro 26-31, c6 input

C.R. 32, not used.

The "XU address is normally the memory location of a number re- quired in the execution of an order. The"Iu address is normally the memory location of the next instructiono Following execution of an order, the tty'l word location must be shifted to C. R. 5-10 to locate the next in- __./" f '------

r·· � . " TO � C,R.ZI I' r.F. F;

To TD TO TRflt." �t:LetTQIt PAfUtLLf'L "'HIFr lIo)PuT'S CoR, S' To 10 � :l .... -"I -2..,

" {J' INHI81T" (Q C.OUNT -. 61'11"1.-1(" c (., CIl cO· .... C CD ., CD ., FRO""' 0- .-.. C,R .ae � . CAl � UNc.nON - Er-1IT FUNcrtOtJ . TIII3L� .... Ot Tflf3LE '-' e o r Pllr

<:'oNT!t1l L REuIST""C t -..tlIFT

'" 0) --'

69

structiono This shift_is possible as two input shift register stages are

used in CoRo 5-100 A pulse applied to one set of trigger capacitors eau-

ses a normal right shift of data; a pulse applied to the other set causes

a parallel shift of data from CoRo 15-20 to CoRo 5-10.

By decoding the order stored in CoRo 21-25, the "function table"

(Figure 6�2) must activate one or more lines to the arithmetic uni.t , To

prevenb generation of incorrect orders when shifting data into the con-

trol register, an additional function table input from the C.FoFo pre­

vents output while the CoFoF. is in the zero state. The diode "and" gates

used in the function table generate a =6 volt output only when all inputs

are -6 volts. A left shift order produces an output on both 00100 and

00110 lines; a right shift order produces an output on the 00110 lin••

Clear and add is produced by a 10000 input, clear and subtr�ct b.1 a 10010

input 0 A 10100 input causes addition and a 10110 input causes subtraction.

The "control counter" (C6) which controls the number of basic

operations performed in some orders occupies CoR. 26-31 (Figure 6.l). This

portion of the control register operates both as a shift register and as a

counter 0 Each.flip-flop has two shift inputs as described in Chapter 4.2.

One input is connected as a standard shift register stageo The other in-

put shifts the �everse oontents of the stage b�ck into itself when trig-

gered, thus acting as a counter. I The interstage amplifiers Sl to S6 (Figure 6.3) emit a positive

pulse to cause counting when a negative ohange in voltage is applied to

the input. The amplifiers are connected to cause counting in the CoR. 31

to CoR. 26 direction. To prevent counting action during shifting, all in­

terstage amplifiers are switched off by 57 when the CoFoF. is in the "0" state.

The operation of the control network (Figure 6.4) is as follows:

-.r .. , .•)

70

"F�I)M c:.,F. F; "1" '!IIDC

(F"IIHC.TiI>N Th�,"c:. e: MIT)

0000' SWITCH ro SL(.)C:K' ,>I' "EI\O� T"''I(K 'IoIOI(.AT ... IN ':oc' flP"'�e'h

00010 IN pur TI1PCi;

000, I Ty,..'::

00100 PVNCt< 11'1.-,

001 '0 '31{'A 1\,It."4 0"1 Nu"'aE:� ,'''

A..:c;. UM II lATOR

001 , I (JHI'INt.H 0'" ",UMI3:.: I\. IrJ .stl,'T �C::<''''�Te: I<;.

01000 L"I'T SHIFT

o 10,0 r,(lc.lir SHIFT

o 1,110 MULT.IPL'( NU"IGEIt ,� SHIFT r�E'(aI�Tclt �'( 1J

o I I I D''II'DE: NUMI.!>t;:tC, IN Ac.c..u�luLllrOIi:' By tJU/Vl�E( IN C"C,U:' 1i'e:C&''ST'"

'I I' 10_00 FlOD" NIJM I3€'R IN )I. L.OCfiTl.:l'". 'To '1C.C.Uf1ULAT

100_0

10-10 sUer"'Acr ""UHI�E� IN LOCATION ")1," ""II(OM rl t.C.V,..l ULtlT O�

,1000 ·TRIlN�Fcfl NVNS�� IN LOC"fIQN "X· To SHIFT Re:c.'l>re.e

I 100 I T�A'N"'":"e�' NUMfjE.( IN LO<;AfION "x" 1() CI'CL-E. REc.,ISn::r<

I 101 0 RE'<'o·1Il0 CONTE'lVr-r Or 'SI-IIFr Fo:E'c,I:;rE/I! I.., LOC.FlTloN "x,"

"0 10 Rc (OkO C.N rIZNT\ or �I

E'HITr\O;f{ ro ..... o ...... e «; � ----@)-

Figure 6.2

Function Table "..)

71

---I ,--­ ..---1 't--__ ' I �-____ C. e. 27 C.R. 29 C..R.30 .-_-r-o-tO 0 0 0 ...--....-t�

?� �4.7KA toos: � J

I\I'� To '1" SIDE. S,'" S7 : 21\11307 2,71(J.1. OF C.F. F.

2.7/(.[1

+1.$ v

C6 Shift Register-Coun�er

n When in the "0 the F ° F state» Co 0 opens gl and activat� s the

M emit line to the memoryo 'V 32 pulses from the memory pass through

gl to shift a new instruction into the control registero The opo compo

pulse which follows sets the CoFoFo to unity and tests g40 This gate is

zero cut off when the Co F of 0 is in the state and the delay ( v) between

the CoFoF. output and g4 ensures that no brea.kthrough results from the

C.FoFo changing states before the opo compo pulse dies away.

When the CoF.Fo is in the "1" state, the function table is

primed and the "XU track address is shifted to the head switcho The

course of action now followed is determined � the orders -r ______, - f

TO Co .. TItOL P"h.Je:.L.. -6., FQt( c:. ... CI.£ oli? Ope:( ATE:, 0 v FoliC MRt-! LJAI. !.I!TraloJc. I!,R.,2.I, ·1 '( � IDE. ARITHMErlC UNIT I. I . �4 '

I - Op' C otliP. PUL�E .s: �----- . - -�06 ME�QR'" f�Q"" t EMI'­ I FLJ'_'c.rlo� TAl!1.1! '" TO"'...s "'61T C'- "'N PUr 1 :

I Bl,.o,-w: \.... I"fC.1I 01', I co", I' '( PIODe I PER,PHf;l(fll EQUIP, PULI.E. M. E"MI' 0(> Com P I .J- .J... I Co,nlta,­ I �E",'<"T E.g I :'HI�T I

�------_j

r3

,_ -. ..)

73

(1) Add, subtract, clear and add, clear and sub-

tract, record accumulator contents in memory

locatiqn "X", record register contents in

memory location "X", transter'contents ot mem-

ory location "X" to register, transfer con-

tents of memory location "X" to cycle registero

In this ease a transter of data to or trom the store is re­

quiredo The order code is designed so a "1" appears in the moS'tslgDi-

ticant d.igit of each ot these orders. The output from C.R. 21 opens

gs and produces an Mo emit signal from gJ' causing emission of 32 pul­

ses upon coincidence between the "xn word location and the word 10ca-

tion av'ailableo The OPe comp , pulse which follows tests g40 As the

Co1.F. is in the Ifl" state, the pulse passes to the arithmetic unit.

I Here it passes through an "or" after1which it returns-to test , gate I gSo "Y" As gs is open, the pulse resets the C.F.F. to !IOn and passes as a

diode pulse" to shi,ft, the try" track location to the bead swltch and cause

transfer of the t�tI word location to CoRD S-IO (the inverted outputs from

gs' g611 g7' gg and a) ,are-merged by -:the use of a common collector resis­ tor). The transfer_of,the next instruction to the control register ,will

now proceed as before�

(2) Left shift and right shift.

In this case no M. emit is generated. Shifting is performed by

continuous clock pulses, and ,the opo compo pulse is derived trom the out­

put of C6 which generates a pulse in the A.Oo ,coupled g6. This pulse re­

sets the C.F.F. to "0" and passes as a Y diode pulse. The operation is

then as described in (I).

(3) Multiply and divide.

In this case the operation complete pulse from the arithmetic cs to 21 fWdt aft.! each baE»\c operation tests gs and causes count. C.R. .,.,J

74

is not unity in this cas., and gs remains switched off until opened by

C6. To ensure that breakthrough does not take place before the opera-

tion complete pulse has died away, a delay is placed on the C6 input.

The following opo compo pulse passes through gs' generating a positive

pulse which resets the O.FoFo and passes as a Y diode pulse. The opera­

tion is then as described in (1).

(4) Block switch and operations involving peripheral equipment.

In each of the above cases, the OPe compo pulse is generated

within the unit a short time after receiving the instruction. The OPe

compo pulse is merged by g9 and inverted by a3 to reset the O.FoF. and

pass as a Y diode pulse. Operation is then as described in (1).

Branch on accumulator contents and branch on " (S) '- shift register, contents 0

. , For an accumulator branch, when the OoF.F. switches to the

• "r • I ' t j . • .. � j • \ t L1. I�: I. ' r L '. "1" state, the branch instruction applies a -6 volt level to VI. '\ll

.' .. 1. .J.,' _ _ :,1 .'.�. ','; L .�. t1 �.J.)� generates a d.l�ed voltage change which tests gg and is differentiated

to reset th� C.FoF. to non� If AI is emits a Y diode ulrlty, gg pulse

and attempts to reset the CoFoF. to "0". This reset pulse has no effect

as the C.FoF. is already ,"0"0

Following the reset of the CoF.F., the memory shifts the next

instruction into the control register. If the Y diode pulse has not

been generated, this instruction is shifted from the "X" memory location.

However, if the Y diode pulse has been generated, the nyn to nx" word

location shift is performed and the ,�" track location is shifted into the

headswitch. This causes the instruction to be shifted from the Y memory

location.

The same procedure is carried out for the register branch in-

struction except that � 2� '8.2 and g7 are involved.

� I I"--��"------"�"""""""""""""""""""""""""-- ._)

75

When testing computer operation or a portion of a program, it

is useful to instruct the computer to perform one oper�tion and then stop.

This,mode of operation is gained b7 the addition of g2. In no�mal oper�­

tion, -6 volts i� �ppl1ed to the controLinput of g20 However,l) for "one

shottl.operations, 0 volts is applied by operating a switch on the control

panel. This prevents issue of �he M emit or�er to the store when the

CoFoFo is in the zero state and,l) as a result,l) causes operation to stop.

. An instruction can now be set manaally from the control panel into the

control register and can be executed by operation of a manual trigger

switch which sets the CoFoFo to "I".

6.2 The Arithmetic Section

The arithmetic section of the logic is composed of four units;

the arithmetic unit,l) the accumulator, the shift register and the cycle

registero Its.operation for the various orders is as follows:

602.1 Transfer of a Number from Memory Location "Xli to the Shift Register

In transfer operations from t�e memory, each bit emitted from

the �ncident�digit flip-flop (IoF.Fo) arrives approximately 2 microseconds

before the. arrival of a \l 32 pukse , The transfer crder opens glO (Figure 6.5) allowing the V 32 pul.ses to shift information from the

IoF.Fo into the first stage of the shift register and shif� t�e regist�r

contents to the right. To preyent unnecessar,y circuits from operating,

the register shift pulses pass through the "or" gate 01•

60202 Transfer of a Number from Memory Location "X" to the gycle "Register

Here,l) the transfer is performed in a manner similar to that

described in.6.20l. The transfer to cyc�e register ord�r opens g12 on

Figure 606 to allow the V 32 pulses to pass. From g12.11 they shift the IoF.Fo contents into Cl and pass through O2 to cause cycle register shift

,Ii I�"��"""""""""""""""""""""""----""""--�--�""-- _)

76

r yo

oZ ,� Yj ('ft l � � po 01 • .. ... I.: ... C Il: ,.;

Figure 6.5 Shift Register (M.3 Unit 3)

1'" !tII I 77

Figure 6.6

Unit '""'111:::"""i";i""iM-ijll",'ll'lIlIIIiii::_"'I'lII'ii"'l. CIIi':l.llc=:.:!e Register (M.3 4) )

78

to the right.

6.203 Right Shift and Left Shift

Right shift consists of shifting the accumulator and shift

register contents to the right with the least significant stage of the

accumulator shifting into the most significant stage of the shift regis-

ter. The sign bit of the number in the accumulator is propagated across

the accumulator and the shift register �ontents are lost out the least

signifioant stage. Left shift is similar to right shirt but data in the

thirty-second stage of the shift register are shifted back to the first

stage of the accumulator.

The right shift order from the function table opens the in-

verting gate g14 on Figure 607. This allows clock p�ses to shift A33 to Rl, A3l t9 A33 via 04 and to shift the accumulator to the right via 0so Pulses pass through 03 to be counted by the C6, and pass through 01

on Figure 6.S to caus� _right shift of the shift register.

To avoid duplication of equipment, the left shift order opens

both g13 and g140 This causes a right shift to be performed but with pulses from g13 shifti�g the contents of R32 to Al. The number of-shifts are again counted by c6 via °30

To perform a right shift of n bits, c6 is initially set te

(64-n)° To perform a left shift of n bits, c6 is set to n.

6.2.4 Addition and Subtraction

Addition is performed by the following rules:

If: Incident digit = carry digit (coincidence)

Sen� A33 to Al

Carr,y digit is unchanged. I ------�..------.:

79

� ... � "" w co: :1 ... 0

Figure 6.7 Accumulator (M.3 Unit 2)

,,It __)

80

It: Inci�ent digit ¢ carry digit (anti-coincidence)

Send the inver se ot A33 to AI

Send A33 to the carr,y digit storeo

The carT,1 digit is initially set to zero.

The adder-subtractor circuit is complicated somewhat by the

tact that a d� stage, A33� is provided in the accumulator to raoili-

tate left shirt in division. In addition and subtraction� both A32 and

A33 are fed from A31, causing A32 to equal A33. In division, A33 is fed

from A32.

When addition is signalled� -6 volts is applied to the add line

of Figure 608. The negative voltage change triggers the inverting ampli-

fier al causing the carry £lip=flop no" to be set to zero. The add order also opens gi7' glS and one input to g250 As no divide order is present, the inverted divide input opens g250 One.side.ot·g23 is also open, but as

the multiply order is not present9 there is no output from this gateo

j When the digits of the_ addend"; arrive from the memory, the coin­

cidence senser (shown in Figure 6 .. 9) compares each incoming digit with the

corresponding carry digit and emits a �6 volt coincidence or anti-c9incidence ..

levelo Approximately 2 microseconds after the arrival of each digit a

V 32 pulse tests the coincidence senser output via g15 and g16' causing the appropriate shift pulse to be passed through g17 and g180 A33 is shif­

ted to AI if coincidence is sensed and the inverse of A33 to AI if anti-

coincidence is sensedo

When anti-coincidence is sensed9 the shift pulse also shifts

the A33 contents into Co To prevent the change in the carry digit contents

from distorting the output pulse from the circuit, the delay shown in

Figure 6.9 is placed between a and the coincidence sensero , ..

81

'" d ... � �------,.

��a.!lO 10

, .... r-_------_ ....

�:o ��

'.L)J :JIJ.lclI'I HOd':I J:JI� "In",

III� (i,lItv

�----r--�------_'�:� � "-' u � -+__� �� �o :Q ..... ! "

... o.

Figure 6.8 Arithmetic Unit (M.3 Unit '7)

-.f' , "<

l ._J

82

-IZv

I CARRY'

o

-12."

It,�" :� ------+ -4

0, ""'Ds : '11273

coinco

Fig. 6.9 Arithmetic Unit Coincidence Senser

The \J 32 pulses pass through the inverting g25 to shift the the accumulator contents to the right and shift A31 to A33. This clears

Al for the incoming digit of the sum, and advances the next digit to be

added into A33.

is the rulesg Subtraction. performed'- by following ,

If: Incident digit.= carry digit (coincidence)

Send the inverse of A33 to Al

Send A33 to .the carr,y digit store.

If: Incident digit � carry digit (anti-coincidence)

Send A33 to Al

The carry digit 'is unchanged.

'. ) I 83

A subtract order from the decoder switches the subtract line

voltage from 0 to -6 volts. This triggers a2 to set C to unityo Sub­

traction of incoming digits from the number stored in the accumulator

is performed in a manner similar to additiono However, to produce the

effect of inverting the incoming digits, g17 and glS are switehed off while g19 and g20 are opened by the subtract ordero Coincidence now

shifts A33 to the carry store and the inverse of A33 to Al; anti-coin=

cidence shifts A33 to Alo

In both addition and subtraetion9 the operation complete pulse

is generated b,y the memory folleving the thirty-second shift pulseo

60205 Clear Operations

In clear and add, clear and subtract or multiply orders� the

accumulator must be zeroed before the arithmetic operation can be per-

formed 0 In the first two cases, the clear order is generated by a separ-

ate output from the function table. In multiplication, the clear order

is generated by the arithmetic unit immediately following receipt of the

multiply ordero

The clear instruction passes through 07 on Figure 605 to trigger

a DoCo coupled one shoto The 5 microsecond pulse generated by this cir-

cuit the zero accumulator circuit in triggers shown Figure 6.100. The 1-

operation of this zeroing circuit, is as follovss Normally, sufficient

base current is drawn from Sl to cause saturationo In this state, the output voltage of +103 to +104 volts allows normal accumulator operationo

However, a positive pulse applied to the 3000 pi input capacitor switches

Sl off, causing a negative output voltageo The negative voltage draws current from the 802K biasing resistor of. each ac�umulator flip=flop,

in to be turned on - causing the right hand transistor each .... By th�s method,

all flip-flops in the accumulator are zeroed in 2 to 3 microsecondso

� I '------����------...... �= v

Accumulator Stage 1 _------�-IZ.v

Output nO"

�-__,,- -'2'1(

Manual Zero -t/.r"� +I.sv Common Zero Bus To Zero Rest of Accum. Zero Input J +1.5"v

Fig. 6.10 Zero Accumulator Circuit

The manual zero switch shown in Figure 6.10 zeros the accumu-

lator by remoVing the saturating current from Sl. 6.2.6 Multiplication

The rules of multiplication are:

For basic operations 1 to 3lg

If: R33 = R32, shift accumulator and register one place righto

If: R33 = 1, R32 = 0, add C to the .accumulator, then shift the

accumulator and register one place right.

If: R33 = 0, R32 = 1, subtract C from the accumulator, then

shift the accumulator and register on.

place righto

...J 85

For basic operation 32:

This operation is identical to previous 31, but delete right shifto

The accumulator and R33 must be zeroed prior to the calcu1a- tion. The multiplier 0 is stored in the cycle register and the mu1ti-

in plicand tpe shif� registero ,

The multiply order from the function table opens g21 and g22

(Fig. 6.8) so that according to the. contents of &32 and R33, an add or subtract instruction,cap be issued by g33 or g34� If addition or subtraction is required, an inst!' emit signal is sent to the memory by g23 which is primed by the multiply ordero This causes emission of the next available set of 32 pulses f�om the memory and pe�ts emission of data from the cuele register by opening gIl of Figure 606 and inhibing the strobe pulses to the read circuito ,The 32 pulses cause cycling of cycle register contents, and shift, the contents of, ,032 to the I.Fof 0

Fol�owing addi�i9n or subtraction, which. is performed in the normal man­ ner, the 0po compo pulse incident on Og passes to the control and also tests g290 If,g33 � g34 signal neither addition nor subtraction, g24 opens to allo� clock_pulses to pass to Og. From here, the incident pulses pass ,to the c�ntro1 and also test,g290 For _ the .rir�t 31 basic o�rations, g29 ;is h.,ld open by 060, Incident pulses from 0g pass via g29 and g27 (held open by the multip� order) as "X shift" pulses which ca�s. a right shift of accumulator and shift register conten�s and cause 06 to co�t. Following the thirty­ first basic ,operation, 06 switches g29,off, preventing a thirty-�econd right,s�rt, and opens a gate in the control,t9 allow the thirty-second op, coxePo pul.se to signal th,e, end of the mu1tiplicationo 'When program­ ming a multiplication, 06 must be set to 330 r ':\ 86

6.2.7 Division

Division in the M.3 is performed by the non-restoring process as follows:

For basic operations 1 to 31:

If3 Cl = AI add 2-31 to the register, shift accumulator and

register one place left� subtract C from the

accumulator.

Ifg Cl f AI add 0 to the register� shift accumulator and regis-

ter one place left� add C to the aocumulatoro

For basic operation 32&

Add 20 to the register.

In division the divisor C is initially stored in the cycle

. register and the dividend in the accumulatoro The �eft shift required is obtained by interposing the additional stages A33 and �33 in the accumu- lator and register, and causing register shift with end round connection of R33 to Rl. during the addition and subtraction cycles. Sin�. there are only 32 shift pulses, the net result after each addition or subtraction is one left shift in the accumulator and register.

The divide order from the decoder activates the insto,e�it line� switches off opens g26.to produce. left shift, opens g28' primes . g2S·and .

c g36. and �3l and. is differentia.ted by 8.6 to generate a- pul.se which passes

•. In heLd until through 08 (Figure 6.8) divisit:m,. g29 ,is .. open by C6 the first thirty-one pulses, paaa, The P"Ul:-se from Os tests th� control and passes through g28 and.g29 to cause C6 to count, �ero A33, shift.the coin­ cidence senser 112 output into R32 and the I8F�.flip-flop and to switch off g3l and g32 f�r 2 microseconds. The latter operation is necessar,y to set the carry flip-flop prior to each addition or subtraction. __)

If coincidence is sensed R32 and F are set to unity and the F output

issues a subtract instruction via g3lo If.anti-coincidence is sensed, R32 and F are set to zero and an add instruction is Lasued via g30. The

inst. emit signal to the memory causes emission of 32 pulses and the

number stored in the cycle register is added to or subtracted from the

accumulator. The opo compo pulse which follows is incident on Os ca.using

the operation to be repeatedo The opo compo pulse following the thir­

tieth addition or subtraction causes 06 to switch g29 off and prime a. gate in the control. The �ulse following the next addition or subtrac­

tion sets the C.F.F. to zero, ending the division. fhe function table

output change to � �lts is differentiated b.1 a; to produce a pulse. which

changes Rl to a "011 if initially a. "1" or to a "1" if initially a "0".

-, $8

REFERENCES

Baxandall, Do', Catalogue of the Collections of the Science Museum, South

Kensington, HoMo Stationery Office, London (1926).

Berkeley, E.C., "Giant Brains", Wiley, New York (1949).

Booth, A.Do and B,ooth, x.a.v., ','Automatic Digital Calculators", Butterworths, London (1953)0

Ii Track for a Drum Store Booth, A.Do, "High Speed Selecti�n �...agnetic ,

Electronic Engineering, � (386) (April 1960) 2090

Booth, KoH. Vo, "Programming for an Automatic Digital Calculator",

Butterworths, London (1958)0

Dewitt, Do and Rossoff, AoLo,o "Transistor Electronics", McGraw-Hill,

New York (1956)0

Millman, J 0 and Taub� Ho, "Pulse and Digital Circuits", McGraw-Hill,

New York (1956)0

Montgomerie, G.Ao, "Digital Calculating Machines", Blackie and Son,

London (1956) 0

Pressman, Aolo, "Design of Transistorized Circuits for Digital Computers", Rider, New York (1959)0

Texas Instruments Incorporated Staff, "Transistor Circuit Design"

McGraw-Hi�l, New York (1963).

Ware, WoH., "Digital Computer Technology and DeSign", Volumes 1 and 2,

Wiley, New York (1963).

Williams, SoB., "Digital Computing Systems", McGraw-Hill, New York (1959). M. 3 ORDER CODE

Number Function 06 Description

o S

1 H Block head switch. This enables the block of heads specified in "XII track location to be shifted into the working store.

2 I Input. The 6 digits currently under the" tape reader fingers are transferred into the 6 most significant digits of R. Next order in location ny".

4 p Punch. The digits contained in the 6 most significant places of R are punched onto the output tape. The digits are not lost from R in so doing. Next order in loca.tion ny".

5 o Type. The symbol represented by the digits in the 6 most significant places of R is typed. The digits are not lost from R in so doing. Next order in location ny".

6 Branch (accumUlator). If the contents of A are < 0 take next order from location ttyn, but if � 0 from location IIX".

7 Branch (shift register). If the contents of R are <. 0 take next order from location "Y", but if � 0 from" location "X".

8 1 n Left shift. Shift the contents of A and R n left n places. Next order in loca.tion l�n.

10 64-n Right shift. Shift the contents of A and R right n places. Next order in location 1�".

x 64-n Multiply the number in the cycle register by the last n digits of the number in R, sending the 32 most significant digits of the product to A and the 31 least significant to R. Next order in location ny".

15 33 Divide the number stored in A by the number stored in the cycle register. The quotient is set into the shift register. Next order It in location 1� •

16 +c Send the contents of location "XII to the cleared accumulator. The next order is in location "Y". Number Function C6 �escription

18 -e Subtra.ct the contents of location ItX" from the cleared accumulator. The next order is in location "Y".

20 + Add the contents of location "X" to the accumulator. The next order is in location "Y".

22 Subtract the contents of location ItX" from the accumulator. The next order is in location "ylt.

T Transfer contents of location "Xn to R. R is automatically cleared by the transfer. The next order is in location llyn.

25 c Transfer contents of location "Y" to the cycle register. The next order is in loca­ tion "yn.

26 (R 32-n Record either the first or the last of the n digits in R in Lecatd.on "X". The (R n remaining ( n-32 digits of "X" are unaf'fected, but the con­ tents of R are replaced by OIS or lIs accord­ ing as the original contents were positive or negative. The next order is in location "Y ".

28 32-n As for 26 except that the recording takes (An ( place from A and the contents of A are un­ A n ( n-32 changed after recording.

'\ I 91

APPENDIX A

�he drawi�gs used to construct the M.3 computer are shown on

the following pages� Unless otherwise stated, resistors are one-half

watt, .:t. 5%. Capacitors smaller than 2000 pf are .:!: 5% type CM-15 minia­

ture silver mica. Larger capacitors are electrolytic. A crossed circle

( � ) indicates the location of required breaks in·the copper busses

of the vero cardsv

Wiring conventions used are as follows·:

-100 v Blue wire·

-12 v Red wire

-6 v Orange wire

+1.5 v Yellow wire

Black wire

Pulse Carrying White/Green wire

Flip-Flop level White/Red wire

Units are numbered as follows:

1 Counter and Coincidence Senser

2 Accumulator

3 Shift Register·

4 Cycle Register

5 Control Register

6 Control

7 Arithmetic Unit

8 Read, Write Circuit

9 Track Selector

10 Block Selector

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