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Intely Xeon Phitm Coprocessor H Igh- Performance Programming

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Intely Xeon Phitm Coprocessor H Igh- Performance Programming Intl n hM Cprr h rfrn rrn ffr ndr AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO M<MOGA KAUMA ESEIE Morgan Kaufmann is an imprint of Elsevier Cntnt oewo iii eace ii Ackowegemes i CAE Intrdtn 1 e moe aaeism 1 Wy eo iM coocessos ae eee 2 aoms wi coocessos 5 e is Ie R eo i coocesso 6 Keeig e "ia Ga" ue coo 9 asomig-a-uig oue aaage 1 We o use a IeR eo coocesso 11 Maimiig eomace a ocessos is 11 Wy scaig as oe ue eas is so imoa 1 Maimiig aae ogam eomace 15 Measuig eaiess o igy aae eecuio 15 Wa aou GUs? 1 eyo e ease o oig o icease eomace 1 asomaio o eomace 17 ye-eaig esus muieaig 17 Coocesso mao usage moe MI esus ooa 1 Comie a ogammig moes 19 Cace oimiaios 20 Eames e eais 1 o moe iomaio 1 CAE 2 h rfrn Cld r t rv 3 ookig ue e oo coocesso seciicaios 24 Saig e ca commuicaig wi e coocesso 26 akig i ou easy uig ou is coe 28 Saig o acceeae uig moe a oe ea 3 ea o e mea iig u see usig a coes 3 Easig i o e is cue accessig memoy awi 9 ig see ake cue maimiig memoy awi 5 ack o e i a summay 57 CAE A rndl Cntr d 59 eaig o ou couy oa i cae ocus 59 Geig a ee o e oa e 9-oi seci agoim 60 A e saig ie e aseie 9-oi seci imemeaio 1 oug oa aea uig e aseie seci coe 68 V v Cntnt Cobblestone street ride: vectors but not yet scaling 70 Open road all-out race: vectors plus scaling 72 Some grease and wrenches!: a bit of tuning 75 Adjusting the "Alignment" 76 Using streaming stores 77 Using huge 2-MB memory pages 79 Summary 81 For more information 81 CAE 4 rvn Arnd n: Optzn A lWrld Cd Expl 83 Choosing the direction: the basic diffusion calculation 84 Turn ahead: accounting for boundary effects 84 Finding a wide boulevard: scaling the code 91 Thunder road: ensuring vectorization 93 Peeling out: peeling code from the inner loop 97 Trying higher octane fuel: improving speed using data locality and tiling 100 High speed driver certificate: summary of our high speed tour 105 CAE t f t (tr 107 Why vectorize? 107 How to vectorize 108 Five approaches to achieving vectorization 108 Six step vectorization methodology 110 Step 1. Measure baseline release build performance 111 Step 2. Determine hotspots using Intel" VTuneTM amplifier XE 111 Step 3. Determine loop candidates using Intel compiler vec-report 111 Step 4. Get advice using the Intel Compiler GAP report and toolkit resources 112 Step 5. Implement GAP advice and other suggestions (such as using elemental functions and/or array notations) 112 Step 6: Repeat! 112 Streaming through caches: data layout, alignment, prefetching, and so an 112 Why data layout affects vectorization performance 113 Data alignment 114 Prefetchin g 116 Streaming stores 121 Compiler tips 123 Avoid manual loop unrolling 123 Requirements for a loop to vectorize (Intel" Compiler) 124 Importance of inlining, interference with simple profiling 126 Compiler options 126 Memory disambiguätion inside vector-loops 127 Compiler directives 128 SIMD directives 129 Cntnt v The VECTOR and NOVECTOR directives 134 The IVDEP directive 135 Random number function vectorization 137 Utilizing full vectors, -opt-assume-safe-padding 138 Option -opt-assume-safe-padding 142 Data alignment to assist vectorization 142 Tradeoffs in array notations due to vector lengths 146 Use array sections to encourage vectorization 150 Fortran array sections 150 Cilk Plus array sections and elemental functions 152 Look at what the compiler created: assembly code inspection 156 How to find the assembly code 157 Quick inspection of assembly code 158 Numerical result variations with vectorization 163 Summary 163 For more information 163 CAE 6 t f (nt hrd 165 OpenMP, Fortran 2008, Intel" TBB, Intel Cilk'" Plus, Intel" MKL 166 Task creation needs to happen on the coprocessor 166 Importance of thread pools 168 OpenMP 168 Parallel processing model 168 Directives 169 Significant controls over OpenMP 169 Nesting 170 Fortran 2008 171 DO CONCURRENT 171 DO CONCURRENT and DATA RACES 171 DO CONCURRENT definition 172 DO CONCURRENT vs. FOR ALL 173 DO CONCURRENT vs. OpenMP "Parallel" 173 Intel' TBB 174 History 175 Using TBB 177 parallel_for 177 blocked_range 177 Partitioners 178 parallel_reduce 179 parallel_invoke 180 Notes on C ++11 180 TBB summary 181 Cilk Plus 181 History 183 v Cntnt Borrowing components from TBB 183 Loaning components to TBB 184 Keyword spelling 184 cilk_for 184 cilk_spawn and cilk_sync 185 Reducers (Hyperobjects) 187 Array notation and elemental functions 187 Cilk Plus summary 187 Summary 187 For more information 188 CAE Offld 189 Two offload models 190 Choosing offload vs. native execution 191 Non-shared memory model: using offload pragmas/directives 191 Shared virtual memory model: using offload with shared VM 191 Intel' Math Kernel Library (Intel MKL) automatic offload 192 Language extensions for offload 192 Compiler options and environment variables for offload 193 Sharing environment variables for offload 195 Offloading to multiple coprocessors 195 Using pragma/directive offload 195 Placing variables and functions on the coprocessor 198 Managing memory allocation for pointer variables 200 Optimization for time: another reason to persist allocations 206 Target-specific code using a pragma in C/C++ 206 Target-specific code using a directive in fortran 209 Code that should not be built for processor-only execution 209 Predefined macros for Intel' MIC architecture 211 Fortran arrays 211 Allocating memory for parts of C/C++ arrays 212 Allocating memory for parts of fortran arrays 213 Moving data from one variable to another 214 Restrictions on offloaded code using a pragma 215 Using offload with shared virtual memory 217 Using shared memory and shared variables 217 About shared functions 219 Shared memory management functions 219 Synchronous and asynchronous function execution: _cilk_offload 219 Sharing variables and functions: _cilk_shared 220 Rules for using _cilk_shared and _cilk_offload 222 Synchronization between the processor and the target 222 Writing target-specific code with _cilk_offload 223 Restrictions on offloaded code using shared virtual memory 224 Cntnt x esise aa we usig sae iua memoy 5 C + + ecaaios o esise aa wi sae iua memoy 7 Aou asycoous comuaio 228 Aou asycoous aa ase 9 Asycoous aa ase om e ocesso o e coocesso 9 Ayig e age aiue o muie ecaaios 3 ec-eo oio use wi ooas 35 Measuig imig a aa i ooa egios 3 _Ooa_eo 3 Usig iaies i ooae coe 37 Aou ceaig ooa iaies wi ia a i 37 eomig ie a e coocesso 3 oggig sou a se om ooae coe 240 Summay 1 o moe iomaio 1 CAE 8 Cprr Arhttr 3 e Ie eo iM coocesso amiy 244 Coocesso ca esig 5 Ie eo i coocesso siico oeiew 246 Iiiua coocesso coe aciecue 7 Isucio a muiea ocessig 9 Cace ogaiaio a memoy access cosieaios 51 eecig 5 eco ocessig ui aciecue 53 eco isucios 5 Coocesso CIe sysem ieace a MA 57 MA caaiiies 5 Coocesso owe maageme caaiiies eiaiiy aaiaiiy a seiceaiiy (AS 3 Macie ceck aciecue (MCA 264 Coocesso sysem maageme cooe (SMC 5 Sesos 5 ema esig owe moioig a coo 266 a see coo 266 oeia aicaio imac 266 ecmaks 7 Summay 7 o moe iomaio 7 CAE Cprr St Sftr 9 Coocesso sowae aciecue oeiew 9 Symmey 71 ig ees use a kee 71 x Cntnt Coocesso ogammig moes a oios 71 ea a e 73 Coocesso MI ogammig moes 7 Coocesso sowae aciecue comoes 7 eeome oos a aicaio aye 7 Ie maycoe aom sowae sack 77 MYO mie yous ous 77 COI coocesso ooa iasucue 7 SCI symmeic commuicaios ieace 7 iua ewokig (ee C/I a sockes 7 Coocesso sysem maageme 79 Coocesso comoes o MI aicaios 282 iu suo o Ie eo coocessos 7 uig memoy aocaio eomace 288 Cooig e ume o M ages 288 Moioig e ume o M ages a e coocesso 288 A same meo o aocaig M ages 9 Summay 9 o moe iomaio 91 CAE 0 nx n th Cprr 93 Coocesso iu aseie 93 Ioucio o coocesso iu oosa a coiguaio 9 eau coocesso iu coiguaio 95 Se 1 Esue oo access 9 Se Geeae e eau coiguaio 9 Se 3 Cage coiguaio 9 Se Sa e Ie MSS seice 9 Cagig coocesso coiguaio 97 Coiguae comoes 97 Coiguaio ies 9 Coiguig oo aamees 9 Coocesso oo ie sysem 3 e micc uiiy 35 Coocesso sae coo 3 ooig coocessos 3 Suig ow coocessos 3 eooig e coocessos 3 eseig coocessos 37 Coocesso coiguaio iiiaiaio a oagaio 3 ee ucios o coiguaio aamees 39 Oe ie sysem ee ucios 311 Aig sowae 31 Aig ies o e oo ie sysem 313 Cntnt x Example: Adding a new global file set 314 Coprocessor Linux boot process 315 Booting the coprocessor 315 Coprocessors in a Linux cluster 318 Intel' Cluster Ready 319 How Inter Cluster Checker works 319 Intel' Cluster Checker support for coprocessors 320 Summary 322 For more information 323 CAE Mth brr 325 Intel Math Kernel Library overview 326 Intel MKL differences on the coprocessor 327 Intel MKL and Intel compiler 327 Coprocessor support overview 327 Control functions for automatic offload 328 Examples of how to set the environment variables 330 Using the coprocessor in native mode 330 Tips for using native mode 332 Using automatic offload mode 332 How to enable automatic offload 333 Examples of using control work division 333 Tips for effective use of automatic offload 333 Some tips for effective use of Intel MKL with or without offload 336 Using compiler-assisted offload 337 Tips for using compiler assisted offload 338 Precision choices and variations 339 Fast transcendentals and mathematics 339 Understanding the potential for floating-point arithmetic variations 339 Summary 342 For more information 342 CAE 2 MI 343 MPI overview 343 Using MPI on Intel' Xeon coprocessors 345 Heterogeneity (and why it matters) 345 Prerequisites (batteries not included) 348 Offload from an MPI rank 349 Hello world 350 Trapezoidal rule 350 Using MPI natively on the coprocessor 354 Hello world (again) 354
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