An Example MPC8540-Based Compactpci Reference Design by NCSD Applications Freescale Semiconductor, Inc

Freescale Semiconductor MPC8540cPCIWP White Paper Rev. 1, 11/2004

An Example MPC8540-Based CompactPCI Reference Design by NCSD Applications Freescale Semiconductor, Inc. East Kilbride, Scotland

CompactPCI™ is a very high performance industrial bus based on Contents the standard PCI electrical specification in a rugged 3U or 6U 1. Introduction ...... 1 Eurocard packaging.Compared to standard desktop PCI, 2. Example Reference CompactPCI Design ...... 3 3. Block Diagram of Example Reference Design ...... 4 CompactPCI supports twice as many PCI slots (8 versus 4) and 4. Example Interface Schematics ...... 6 offers a packaging scheme that is much better suited for use in 5. Document Revision History ...... 28 industrial applications.Due to its extremely high bandwidth, the CompactPCI bus is particularly well suited for many high speed data communication applications such as servers, routers, converters and switches. Full CompactPCI specifications are available from the PCI Industrial Computer Manufacturers Group at www.picmg.org. This White Paper describes an example design of a compact PCI reference system based on the latest MPC8540 integrated PowerPC™ processor.

1 Introduction The MPC8540 is a member of the latest PowerPC processor based family of integrated devices. It is based on a 32-bit implementation of the “new” Book E Embedded PowerPC processor core. This core is known as the e500 core and supports the features detailed in the PowerPC Book E architecture definition. This core has several features that differ from other PowerPC cores which are known as “Classic PowerPC.” Details of the differences are described in a separate Application Note.

The key features of the MPC8540 are described in the MPC8540 User’s Manual and therefore will not be repeated here. The device consists of the following components in a 783-ball FC-PBGA package • Embedded e500 Book E-compatible core • 256 Kbytes of on-chip memory • DDR memory controller • Local Bus Controller • 2 x Three-speed (10/100/1000) Ethernet controllers (TSEC) • RapidIO interface unit • PCI/PCI-X functional unit • Integrated DMA controller • Programmable Interrupt Controller (PIC) • DUART •I2C Controller • Boot sequencer • Address translation and mapping unit (ATMU) • System performance monitor • System access port • Power management • IEEE 1149.1-compliant, JTAG boundary scan A block diagram of the main functional units within the MPC8540 is shown in Figure 1.

CompactPCI Reference Design, Rev. 1

2 Freescale Semiconductor Example Reference CompactPCI Design

Figure 1. MPC8540 Functional Block Diagram

2 Example Reference CompactPCI Design This example reference design utilises the on chip PCI Controller in the MPC8540 to interface to the CompactPCI bus. It contains a block of DDR SDRAM memory which is controlled directly by the device and a small amount of Flash memory used to hold power on reset boot code. One of the TSEC ethernet interfaces is brought out to a standard RJ-45 socket via a Gb Ethernet PHY device and associated interface logic. Separate debug interface ports are provided via the on-chip DUART interface. The RapidIO Trade Association have defined a standard interface connector for a parallel RapidIO interface. This forms part of the specification for a Hardware Implementation Platform (HIP) which allows standard PCI to RapidIO inter operability. This HIP platform is not defined for CompactPCI systems. For reference purposes the schematics for this example design show this standard RapidIO connector as an optional extra connector. Full details are available at www.rapidio.org.

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 3 Block Diagram of Example Reference Design 3 Block Diagram of Example Reference Design A block diagram of the example system is shown in Figure 2.

Power Supply

DDR SDRAM Gb Ethernet 128MBytes PHY etc

MPC8540 Boot FLASH DUART 8MBytes RS232 Interface

CompactPCI Optional RapidIO Connector Connector

Clocking,Configuration and Reset Logic

Figure 2. Block Diagram of Reference Design

3.1 MPC8540 The MPC8540 is the processing element of this design. It contains a 32-bit embedded PowerPC processor core and interfaces to each of the other blocks of this example reference design.

3.2 DDR SDRAM The main memory array is built from 5 x MT46V16M16 DDR SDRAM devices. These are configured to provide 128MBytes of 64-bit wide memory along with one parity bit for each memory byte. The control of the DDR memory system is handled by the DDR memory controller implemented within the MPC8540 device.

3.3 Boot Flash The boot Flash is implemented by a single 8MByte AMD29L_V641D device configured to be 16-bits wide. Since the local bus of the MPC8540 is a multiplexed address and data bus, an external latch using 74LVT16373 devices is implemented and controlled by the Local Address Latch Enable (LALE) signal from the MPC8540.

CompactPCI Reference Design, Rev. 1

4 Freescale Semiconductor Block Diagram of Example Reference Design 3.4 Compact PCI Connectors The MPC8540 device contains an on-chip PCI/PCI-X interface which handles all the defined protocol for these buses. The PCI bus is brought out to two separate edge connectors on the board which conform to the Compact PCI interface specification. These are the connectors defined as J1 and J2 in the CompactPCI specification. Note the MPC8540 only supports 3.3V I/O. If a 5V interface is to be supported then level shifting logic will be required between the MPC8540 and the connectors.

3.5 Gb Ethernet PHY The MPC8540 contains a two separate triple speed ethernet controllers which support speeds of 10Mbps, 100Mbps and 1Gbps. One of these controllers is brought out to an RJ45 edge connector via a Marvell 88E1011Gb Ethernet physical transceiver device

3.6 DUART The MPC8540 also contains a dual UART interface that supports simple serial interfaces. These channels are brought out to 9-way D type RS232 connectors. These ports would be typically be used for debug and maintenance work

3.7 Clocking, Configuration and Reset Logic The MPC8540 uses the input 66MHz PCI clock as a reference and makes use of on-chip PLLs to multiply this clock frequency to drive the memory interface bus and processor core. A diagram of the clock structure is shown in Figure 3.

Figure 3. Clock sub-system Block Diagram

Many of the features of the MPC8540 are configured by sampling a series of pins during reset. In this reference design the configuration pins are all implemented as a series of small DIP switches that are configured by hand before the device is reset. For a design where the final configuration is known at the design stage then these DIP

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 5 Example Interface Schematics switches can be omitted and replaced by pull-up or pull-down resistors to achieve the desired value on the configuration pins.

3.8 Power Supply Assuming this board will be supplied with +5V and +3.3V from the CompactPCI backplane then all the other voltages required on the board are generated by the various power convertor circuits on the card. This includes 2.5V for the DDR memory and Ethernet PHY. The 1.2V cpu core voltage and the 1.5V for the Ethernet PHY. The 1.25V reference voltage for the DDR memory is produced by the LP2995 DDR voltage regulator device.

4 Example Interface Schematics A full set of interface schematics are shown below. These were created using OrCad version 9.2 available from Cadence Design Systems™. The schematics are laid out in a hierarchical sequence of sheets. The following pages give a full set of example schematics for an MPC8540 Compact PCI Reference design. They also include an optional RapidIO connector. The schematics are laid out in a hierarchical fashion as follows: Table 1. Top Level System Interconnection

Figure 4 Top Level System Interconnection Figure 5 Top Level view of MPC8540 and memory systems Figure 6 DDR SDRAM Memory Array Figure 7 MPC8540 Top Level Figure 8 Boot FLASH Memory Figure 9 MPC8540 CPU and Local Bus Interface Figure 10 MPC8540 DDR SDRAM Interface Figure 11 DDR SDRAM Termination Figure 12 MPC8540 Gb Ethernet Interface Figure 13 MPC8540 RapidIO Interface Figure 14 MPC8540 Power on Configuration Logic Figure 15 MPC8540 PCI/PCI-X Interface Figure 16 MPC8540 Parallel I/O and DUART Interface Figure 17 MPC8540 Power Connections Figure 18 Compact PCI J1 and J2 Connectors Figure 19 Clock and Reset Logic Figure 20 Local Power Supply Logic Figure 21 Gb Ethernet Transceiver Figure 22 RS232 Interface Logic Figure 23 Optional RapidIO Connector Figure 24 MPC8540 COP Debug Connector

CompactPCI Reference Design, Rev. 1

6 Freescale Semiconductor Example Interface Schematics PCI[0:86] PCI_Connectors P15_PCI_Connectors

PCI[0:86]

DEBUG[0:8] DEBUG[0:8] DEBUG[0:8] PCI[0:86]

Debug P21_Debug_Connector

RIO[0:39] RIO[0:39]

RIO[0:39]

SYSCLK SYS_HRESET* SYSCLKA ETHERA[0:24] GTX_CLK125 MDIO MDC SIN0 SOUT0 SIN1 SOUT1

RapidIO_Connector P20_RapidIO_Connector Top_Level P02_Top_Level_View SYS_HRESET* ETHERA[0:24] Clocks+Reset P16_Clocks_+_Reset SIN0 SIN1 MDC MDIO SOUT0 SOUT1

GTX_CLK125

ETHERA[0:24] SYS_HRESET* Ethernet+RS232 P18/19_Ethernet_+_RS232 Power_Supply P17_Power_Supply

Figure 4. Top Level System Interconnection

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 7 Example Interface Schematics DEBUG[0:8] SYS_HRESET* MDQ[0:63] MDM[0:8] MDQS[0:8] MECC[0:7] MA[0:12] MBA[0:1] MCS0* RAS* CAS* MWE* MCKE MCK MCK* Memory_Block P03_Memory_System MDQ[0:63] MDM[0:8] MDQS[0:8] MECC[0:7] MA[0:12] DEBUG5 MBA[0:1] TCKTDITDOTMSTRST DEBUG0 DEBUG1 SRESET* DEBUG2 DEBUG3 DEBUG4 CKSTP_IN* DEBUG6 CKSTP_OUT* DEBUG7 DEBUG8 HRESET* TDI TCK TDO TMS MCK RAS* CAS* TRST MCK* MWE* MCKE MCS0* MA[0:12] MBA[0:1] MDM[0:8] HRESET* SRESET* MDQ[0:63] MECC[0:7] MDQS[0:8] CKSTP_IN* CKSTP_OUT* LAD[0:31] LCS0* LALE LWR* LBOE* SDA SCL ETHERA[0:24] GTX_CLK125 MDIO MDC SYSCLK RIO[0:39] PCI[0:86] SIN0 SOUT0 SIN1 SOUT1 MPC8540 P04_MPC8540_Top_level LAD[0:31] SDA SCL LALE LWR* LCS0* LBOE* LAD[0:31] HRESET* SIN0 SIN1 MDIO MDC SOUT0 SOUT1 Boot_Flash P05_Boot_Flash SYSCLK RIO[0:39] PCI[0:86] GTX_CLK125 ETHERA[0:24]

Figure 5. Top Level view of MPC8540 and memory systems

CompactPCI Reference Design, Rev. 1

8 Freescale Semiconductor Example Interface Schematics C5 0.1uF C10 0.1uF C15 0.1uF C4 0.1uF C9 0.1uF C14 0.1uF VREF_+1.25V MDQ48 MDQ49 MDQ50 MDQ54 MDQ55 MDQ63 MDQ61 MDQ52 MDQ59 MDQ51 MDQ53 MDQ56 MDQ57 MDQ58 MDQ62 MDQ60 C3 0.1uF C8 0.1uF C13 0.1uF 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 14 17 25 43 53 19 50 49 34 48 66 64 58 52 12 6 NC NC NC NC NC VSS VSS VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DNU DNU DQ13 DQ14 DQ15 DQ10 DQ11 DQ12 VREF VSSQ VSSQ VSSQ VSSQ VSSQ C2 0.1uF C7 0.1uF C12 0.1uF CLK VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS CS UDQS LDQS A0 A10/AP A11 A12 BA0 BA1 CLK CKE UDM LDM WE U4 MT46V16M16_TSOP66 C1 0.1uF C6 0.1uF C11 0.1uF 1 3 9 29 30 31 32 35 36 37 38 39 40 28 41 42 26 27 45 46 44 47 20 51 16 23 22 21 24 18 33 15 55 61 7 6 6 7 MA7 MA5 MBA0 MCK* MA3 MA6 MA2 MA9 MBA1 MA8 MA12 MCK MA11 MA4 MCKE MA1 MA0 MA10 MCS0* MDQS MDM MDM MDQS MWE* CAS* RAS* +2.5V +2.5V +2.5V C16 220uF + VTT_+1.25V +2.5V C18 50uF + VREF_+1.25V MDQ46 MDQ32 MDQ40 MDQ41 MDQ44 MDQ34 MDQ35 MDQ42 MDQ43 MDQ45 MDQ33 MDQ37 MDQ38 MDQ39 MDQ47 MDQ36 8 7 6 5 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 14 17 25 43 53 19 50 49 34 48 66 64 58 52 12 6 VTT AVIN PVIN NC NC NC NC NC VSS VSS VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DNU DNU DQ13 DQ14 DQ15 DQ10 DQ11 DQ12 VREF VSSQ VSSQ VSSQ VSSQ VSSQ MECC[0:7] CLK VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS CS UDQS LDQS A0 A10/AP A11 A12 BA0 BA1 CLK CKE UDM LDM WE U3 MT46V16M16_TSOP66 LP2995 1 3 9 LP2995 U6 NC GND VSENSE VREF VDDQ 29 30 31 32 35 36 37 38 39 40 28 41 42 26 27 45 46 44 47 20 51 16 23 22 21 24 18 33 15 55 61 1 2 3 4 5 4 5 4 MA4 MA5 MA6 MA1 MBA1 MCK* MA12 MA8 MCK MA10 MA11 MA2 MA0 MBA0 MA7 MA9 MA3 MCKE MCS0* MWE* MDQS MDQS CAS* MDM RAS* MDM +2.5V +2.5V DDR Memory Termination Regulator C17 0.1uF + VREF_+1.25V VREF_+1.25V MDQ25 MDQ16 MDQ17 MDQ20 MDQ23 MDQ28 MDQ31 MDQ21 MDQ26 MDQ22 MDQ27 MDQ19 MDQ29 MDQ24 MDQ18 MDQ30 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 14 17 25 43 53 19 50 49 34 48 66 64 58 52 12 6 VREF_+1.25V NC NC NC NC NC MECC0 MECC7 MECC1 MECC4 MECC6 MECC6 MECC1 MECC2 MECC2 MECC5 MECC7 MECC0 MECC3 MECC4 MECC5 MECC3 VSS VSS VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DNU DNU DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VREF VSSQ VSSQ VSSQ VSSQ VSSQ 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 14 17 25 43 53 19 50 49 34 48 66 64 58 52 12 6 CLK VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ A0 A10/AP A11 A12 BA0 BA1 CLK CKE UDM LDM WE A1 A2 A3 A4 A5 A6 A7 A8 A9 UDQS LDQS RAS CAS CS NC NC NC NC NC U2 MT46V16M16_TSOP66 VSS VSS VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DNU DNU DQ13 DQ14 DQ15 DQ10 DQ11 DQ12 VREF VSSQ VSSQ VSSQ VSSQ VSSQ 1 3 9 29 30 31 32 35 36 37 38 39 40 28 41 42 26 27 45 46 44 47 20 51 16 23 22 21 24 18 33 15 55 61 2 3 3 2 CLK VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ A1 A2 A3 A4 A5 A6 A7 A8 A9 UDQS LDQS RAS CAS CS A0 A10/AP A11 A12 BA0 BA1 CLK CKE UDM LDM WE MA4 MA12 MBA1 MCK U5 MT46V16M16_TSOP66 MBA0 MCK* MA5 MA7 MA2 MA3 MCKE MA11 MA10 MA8 MA9 MA0 MA1 MA6 MWE* MDQS MCS0* RAS* MDQS MDM MDM CAS* 1 3 9 29 30 31 32 35 36 37 38 39 40 28 41 42 26 27 45 46 44 47 20 51 16 23 22 21 24 18 33 15 55 61 +2.5V +2.5V MA11 MBA0 MA4 MA9 MA3 MA6 MA10 MA0 MA8 MCK MA7 MCKE MBA1 MA12 MCK* MA2 MA5 MA1 MDM8 MDQS8 MCS0* RAS* MWE* CAS* +2.5V +2.5V VREF_+1.25V MDQ1 MDQ5 MDQ13 MDQ2 MDQ3 MDQ6 MDQ8 MDQ9 MDQ10 MDQ11 MDQ0 MDQ7 MDQ14 MDQ15 MDQ4 MDQ12 2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65 14 17 25 43 53 19 50 49 34 48 66 64 58 52 12 6 NC NC NC NC NC VSS VSS VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DNU DNU DQ13 DQ14 DQ15 DQ10 DQ11 DQ12 VREF VSSQ VSSQ VSSQ VSSQ VSSQ CLK VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ A1 A2 A3 A4 A5 A6 A7 A8 A9 RAS CAS CS UDQS LDQS A0 A10/AP A11 A12 BA0 BA1 CLK CKE UDM LDM WE U1 MT46V16M16_TSOP66 1 3 9 29 30 31 32 35 36 37 38 39 40 28 41 42 26 27 45 46 44 47 20 51 16 23 22 21 24 18 33 15 55 61 1 0 1 0 MA3 MA8 MA10 MA4 MA5 MCK* MA9 MA2 MA6 MA11 MA1 MCK MCKE MBA0 MBA1 MA0 MA12 MA7 MDM MWE* MDM RAS* MDQS MDQS CAS* MCS0* +2.5V +2.5V MCONTROL[0:3] MCLKS[0:2] MCS0* MCONTROL3 MDQS[0:8] RAS* MCONTROL0 MDM[0:8] MWE* MCONTROL2 CAS* MCONTROL1 RAS* CAS* MWE* MCS0* MCKE MCLKS2 MCK* MCLKS1 MCK MCLKS0 MDM[0:8] MDQS[0:8] MCK MCK* MCKE MA[0:12] MBA[0:1] MDQ[0:63]

Figure 6. DDR SDRAM Memory Array

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 9 Example Interface Schematics PCI[0:86] MDQ[0:63] MECC[0:7] MDQS[0:8] MDM[0:8] MWE* CAS* RAS* MA[0:12] MBA[0:1] MCS0* MCK MCK* MCKE PCI[0:86] CFG[1:32] MPC8540_Power P14_MPC8540_Power MCK CAS* RAS* MCK* MWE* MCKE MCS0* MA[0:12] MBA[0:1] MDM[0:8] SYSCLK MDQ[0:63] MECC[0:7] MDQS[0:8] MPC8540_PCI/PCIX_Interface P12_MPC8540_PCI_Interface MPC8540 _Memory Interface _Memory MPC8540 P07/08_MPC8540_DDR_Mem_I/F LAD[0:31] LCS0* LALE LWR* LBOE* TCK TDI TMS TRST TDO CKSTP_IN* CKSTP_OUT* CFG[1:32] TDI TCK TDO TMS LALE TRST LWR* LCS0* LBOE* LAD[0:31] CFG[1:32] CKSTP_IN* CKSTP_OUT* CFG[1:32] HRESET MPC8540_CONFIG P11_MPC8540_Configuration_logic SYSCLK SRESET* HRESET* SDA SCL MDC MDIO MPC8540_CPU P06_MPC8540_CPU SDA SCL MDC MDIO SRESET* HRESET* SYSCLK RIO[0:39] MPC8540_RapidIO_Interface P10_ MPC8540_RapidIO_Interface CFG[1:32] SIN0 SOUT0 SIN1 SOUT1 MPC8560_CPM_Interface P13_MPC8540_CPM_Interface ETHERA[0:24] GTX_CLK125 MPC8540_Comms_Interface P09_MPC8540_Comms_Interface SIN0 SIN1 SOUT0 SOUT1 ETHERA[0:24] GTX_CLK125 RIO[0:39]

Figure 7. MPC8540 Top Level

CompactPCI Reference Design, Rev. 1

10 Freescale Semiconductor Example Interface Schematics LA30 LA29 LA28 LA27 LA26 LA25 LA24 LA23 LA22 LA21 LA20 LA19 LA18 LA17 LA16 LA15 LA14 LA13 LA12 LA11 LA10 LA9 +3.3V 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 10 9 47 27 46

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9

VIO A19 A20 A21 A10 A11 A12 A13 A14 A15 A16 A17 A18 VSS VSS 4M x 16 FLASH 16 x 4M AM29LV641D U9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 OE ACC WP VCC CE WE RESET 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 28 26 11 12 13 14 37 R7 10K LAD15 LAD14 LAD13 LAD12 LAD11 LAD10 LAD9 LAD8 LAD7 LAD6 LAD5 LAD4 LAD3 LAD2 LAD1 LAD0 R6 10K +3.3V LA[9:30] LWR* LBOE* LCS0* HRESET* SDA SCL R5 4K7 LA18 LA22 LA9 LA10 LA11 LA12 LA13 LA14 LA15 LA16 LA17 LA19 LA20 LA21 LA23 LA24 LA25 LA26 LA27 LA28 LA29 LA30 R4 4K7 R2 10K R3 4K7 +3.3V R1 10K 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 4 10 15 21 28 34 39 45 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 4 10 15 21 28 34 39 45 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 5 6 7 3 2 1 A2 A1 A0 WP SCL SDA VCC VCC VCC VCC VCC VCC VCC VCC VCC GND 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1LE 2LE 2OE 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 1LE 2LE 2OE 1OE 1OE U7 EEPROM U8 74LVT16373/SO U10 74LVT16373/SO 8 4 1 7 1 7 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 48 25 24 18 31 42 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 48 25 24 18 31 42 C19 0.1uF +3.3V +3.3V +3.3V +3.3V LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 LAD23 LAD24 LAD25 LAD26 LAD27 LAD28 LAD29 LAD30 LAD31 LALE LAD[0:31]

Figure 8. Boot FLASH Memory

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 11 Example Interface Schematics LAD[0:31] LWR* LBOE* LCS0* 10K R29 R31 10K CFG6 +3.3V +3.3V +3.3V LALE R30 10K R34 10K CFG19 +3.3V CFG5 LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 LAD23 LAD24 LAD25 LAD26 LAD27 LAD28 LAD29 LAD30 LAD31 CFG1 CFG2 CFG3 CFG4 CFG12 CFG29 CFG30 CFG18 CFG13 CFG14 CFG7 CFG8 AD26 AD27 AD28 AC26 AC27 AC28 AA22 AA23 AA26 Y21 Y22 Y26 W20 W22 W26 V19 T22 R24 R23 R22 R21 R18 P26 P25 P20 P19 P18 N22 N23 N24 N25 N26 AA27 AA28 T26 P21 T27 T28 U19 U22 V28 V27 V23 V22 AB28 AB27 T23 P24 U18 T18 T19 T20 T21 Y27 Y28 W27 W28 R27 R28 P27 P28 U23 U27 U28 V18 V21 V20 LA27 LA28 LA29 LA30 LA31 LALE LAD0 LAD1 LAD2 LAD3 LAD4 LAD5 LAD6 LAD7 LAD8 LAD9 LDP0 LDP1 LDP2 LDP3 LCS0 LCS1 LCS2 LCS3 LCS4 LCKE LAD10 LAD11 LAD12 LAD13 LAD14 LAD15 LAD16 LAD17 LAD18 LAD19 LAD20 LAD21 LAD22 LAD23 LAD24 LAD25 LAD26 LAD27 LAD28 LAD29 LAD30 LAD31 LCLK0 LCLK1 LCLK2 LBCTL LGPL5 LSYNC_IN MPC8540 U11F LWE1/LBS1 LWE2/LBS2 LWE3/LBS3 LWE0/LBS0 LSYNC_OUT LGPL1/LSDWE LGPL0/LSDA10 LGPL3/LSDCAS LCS6/DMA_DACK2 LCS5/DMA_DREQ2 LGPL2/LOE/LSDRAS LCS7/DMA_DDONE2 LOCAL BUS LGPL4/LGTA/LUPWAIT/LPBSE R19 10K R18 10K +3.3V R17 10K R28 10K R16 10K R27 10K R15 10K R26 10K TDO TRST TMS TDI TCK R14 10K +3.3V R25 10K R13 10K R24 10K R12 10K SCL SDA R23 10K SYSCLK R11 10K R22 10K R10 10K R21 10K R9 10K R20 10K R8 10K

AG17 AG16 AA18 Y18 AB18 AG24 AA21 Y19 AA19 AG25 AB20 Y20 AF26 AH24 AB21 H5 G4 H6 G5 H7 G6 AF19 AG23 AF23 AG21 AF21 T11 U11 AF1 C1 AB23 AH21 AH23 AH22 DEBUG TDI TCK RTC TMS TDO UDE MCP IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 TRST IIC_SCL IIC_SDA SPARE1 SPARE2 SPARE3 SPARE4 SYSCLK IRQ_OUT DFT PWR Mng. DMA_DACK0 DMA_DACK1 DMA_DREQ0 DMA_DREQ1

DMA_DDONE0 DMA_DDONE1 DMA ANALOG I2C IRQ9/DMA_DREQ3 IRQ10/DMA_DACK3

JTAG SYS. CNTRL

IRQ11/DMA_DDONE3 Eth.MI SPARES CLOCKING PIC AUXILIARY FUNCTION MPC8540 U11D CKSTP_IN NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 EC_MDC EC_MDIO L1_TSTCLK CLK_OUT CLKOUT_DIFF CLKOUT_DIFF THERM0 THERM1 L2_TSTCLK TRIG_IN TRIG_OUT/READY/QUIESCE MSRCID0 MSRCID1 MSRCID2 MSRCID3 MSRCID4 MDVAL LSSD_MODE TEST_SEL(Draco/Dracom) ASLEEP CKSTP_OUT SRESET HRESET_REQ HRESET J9 F1 F3 F5 F2 F4 A2 A3 B1 B2 E1 G2 G3 G1 N12 AH1 AH2 AH3 M11 AG1 AG2 AF28 AF22 AF20 AE28 AB22 AH25 AH26 AH27 AH28 AH20 AH16 AG28 AG22 AG19 AG18 AG20 R35 10K +3.3V CFG27 CFG28 CFG15 RED D1 R33 160R Reset Configuration +3.3V R37 10K Sys_PLL Ratio bit 0 Sys_PLL Ratio bit 1 Sys_PLL Ratio bit 2 Sys_PLL Ratio bit 3 Core_PLL Ratio bit 0 Core_PLL Ratio bit 1 Host/Agent Select bit 0 Host/Agent Select bit 1 CPU Boot Configuration CPU Boot Sequence bit 0 CPU Boot Sequence bit 1 TSEC Width RIO Tx CLK Source bit 0 RIO Tx CLK Source bit 1 Memory Debug Config DDR Debug Config PCI/PCI-X Output Hold bit 0 PCI/PCI-X Output Hold bit 1 +3.3V MDC MDIO CKSTP_IN* CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG12 CFG13 CFG14 CFG15 CFG18 CFG19 CFG27 CFG28 CFG29 CFG30 R32 10K CKSTP_OUT* +3.3V RED D2 R36 160R +3.3V HRESET* SRESET* CFG[1:32]

Figure 9. MPC8540 CPU and Local Bus Interface

CompactPCI Reference Design, Rev. 1

12 Freescale Semiconductor Example Interface Schematics C29 0.1uF C28 0.1uF C27 0.1uF PMDQ[0:63] C32 10uF C26 0.1uF C25 0.1uF C31 10uF C24 0.1uF C23 0.1uF C30 10uF C22 0.1uF C21 0.1uF C20 0.1uF +2.5V PMDQ0 PMDQ1 PMDQ2 PMDQ3 PMDQ4 PMDQ5 PMDQ6 PMDQ7 PMDQ8 PMDQ9 PMDQ10 PMDQ11 PMDQ12 PMDQ13 PMDQ14 PMDQ15 PMDQ16 PMDQ17 PMDQ18 PMDQ19 PMDQ20 PMDQ21 PMDQ22 PMDQ23 PMDQ24 PMDQ25 PMDQ26 PMDQ27 PMDQ28 PMDQ29 PMDQ30 PMDQ31 PMDQ32 PMDQ33 PMDQ34 PMDQ35 PMDQ36 PMDQ37 PMDQ38 PMDQ39 PMDQ40 PMDQ41 PMDQ42 PMDQ43 PMDQ44 PMDQ45 PMDQ46 PMDQ47 PMDQ48 PMDQ49 PMDQ50 PMDQ51 PMDQ52 PMDQ53 PMDQ54 PMDQ55 PMDQ56 PMDQ57 PMDQ58 PMDQ59 PMDQ60 PMDQ61 PMDQ62 PMDQ63 M26 L27 L22 K24 M24 M23 K27 K26 K22 J28 F26 E27 J26 J23 H26 G26 C26 E25 C24 E23 D26 C25 A24 D23 B23 F22 J21 G21 G22 D22 H21 E21 N18 J18 D18 L17 M18 L18 C18 A18 K17 K16 C16 B16 G17 L16 A16 L15 G15 E15 C14 K13 C15 D15 E14 D14 D13 E13 D12 A11 F13 H13 A13 B12 J12 F12 C12 L13 G13 A14 K15 F15 D16 J17 E17 B17 G18 H19 F19 D19 K20 G20 A20 N21 D21 J22 E22 B22 L23 G23 H24 D24 M25 K25 F25 A25 A26 J27 A27 L28 G28 D28 C28 B28 A28 MDQ0 MDQ1 MDQ2 MDQ3 MDQ4 MDQ5 MDQ6 MDQ7 MDQ8 MDQ9 GVdd2 GVdd3 GVdd4 GVdd5 GVdd6 GVdd7 GVdd8 GVdd9 MDQ10 MDQ11 MDQ12 MDQ13 MDQ14 MDQ15 MDQ16 MDQ17 MDQ18 MDQ19 MDQ20 MDQ21 MDQ22 MDQ23 MDQ24 MDQ25 MDQ26 MDQ27 MDQ28 MDQ29 MDQ30 MDQ31 MDQ32 MDQ33 MDQ34 MDQ35 MDQ36 MDQ37 MDQ38 MDQ39 MDQ40 MDQ41 MDQ42 MDQ43 MDQ44 MDQ45 MDQ46 MDQ47 MDQ48 MDQ49 MDQ50 MDQ51 MDQ52 MDQ53 MDQ54 MDQ55 MDQ56 MDQ57 MDQ58 MDQ59 MDQ60 MDQ61 MDQ62 MDQ63 GVdd10 GVdd11 GVdd12 GVdd13 GVdd14 GVdd15 GVdd16 GVdd17 GVdd18 GVdd19 GVdd20 GVdd21 GVdd22 GVdd23 GVdd24 GVdd25 GVdd26 GVdd27 GVdd28 GVdd29 GVdd30 GVdd31 GVdd32 GVdd33 GVdd34 GVdd35 GVdd36 GVdd37 GVdd38 GVdd39 GVdd40 GVdd41 DRAM DDR S MPC8540 U11B MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7 MDM0 MDM1 MDM2 MDM3 MDM4 MDM5 MDM6 MDM7 MDM8 MDQS0 MDQS1 MDQS2 MDQS3 MDQS4 MDQS5 MDQS6 MDQS7 MDQS8 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MBA0 MBA1 MWE- MRAS- MCAS- MCS0- MCS1- MCS2- MCS3- MCKE0 MCKE1 MCK0 MCK0- MCK1 MCK1- MCK2 MCK2- MCK3 MCK3- MCK4 MCK4- MCK5 MCK5- MSYNC_OUT MSYNC_INMVREF(GVdd/2) GVdd1 J25 J14 J13 J16 J15 J20 L19 L24 L21 L26 L14 F24 F16 F14 F21 F17 F20 F28 F27 A21 A19 A22 A23 A15 E19 E18 E16 B13 B21 K21 B24 K19 B25 B18 B19 E26 E28 B15 E20 K14 N20 C21 H28 D25 H18 C13 C20 N19 C23 H23 D27 D17 H16 H15 H25 D20 N28 N27 G19 G14 G24 G16 G27 M20 M19 M21 M28 CAS* RAS* MWE* MCS0* MCK* MCKE MCK PMECC0 PMECC1 PMECC2 PMECC3 PMECC4 PMECC5 PMECC6 PMECC7 PMDM0 PMDM1 PMDM2 PMDM3 PMDM4 PMDM5 PMDM6 PMDM7 PMDM8 PMDQS0 PMDQS1 PMDQS2 PMDQS3 PMDQS4 PMDQS5 PMDQS6 PMDQS7 PMDQS8 PMA0 PMA6 PMA7 PMA11 PMA2 PMA3 PMA4 PMA5 PMA8 PMA9 PMA10 PMA12 PMA1 VREF_+1.25V PMBA0 PMBA1 MCK MCK* PCAS* PMDM[0:8] PMA[0:12] PMBA[0:1] PMDQS[0:8] PMECC[0:7] PRAS* PMWE* MCKE MCS0* R40 10K R39 10K +2.5V R38 10K

Figure 10. MPC8540 DDR SDRAM Interface

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 13 Example Interface Schematics VTT_+1.25V VTT_+1.25V VTT_+1.25V MDM[0:8] MECC[0:7] RAS* CAS* MWE* VTT_+1.25V VTT_+1.25V R48 25R R56 25R R64 25R R72 25R R80 25R R88 25R R96 25R R104 25R R112 25R R142 25R R148 25R R154 25R R160 25R R168 25R R176 25R R182 25R R188 25R R240 25R R254 25R R256 25R MDM2 MDM8 MECC0 MECC7 MDM6 MDM1 MECC6 MECC2 MDM3 MECC1 MDM0 MDM4 MDM7 MECC3 MECC4 MDM5 MECC5 MDM4 MECC6 MDM3 MECC2 MDM6 MECC3 MECC0 MDM2 MECC4 MECC1 MDM5 MDM7 MECC5 MDM1 MDM8 MDM0 MECC7 R47 22R R55 22R R63 22R R71 22R R79 22R R87 22R R95 22R R103 22R R111 22R R141 22R R147 22R R153 22R R159 22R R167 22R R175 22R R181 22R R187 22R R239 22R R253 22R R255 22R PMDM5 PMDM0 PMDM7 PMECC1 PMECC7 PMDM1 PMECC3 PMECC6 PMDM4 PMECC0 PMECC2 PMDM3 PMECC5 PMDM2 PMECC4 PMDM6 PMDM8 PRAS* PCAS* PMWE* PMDM[0:8] PMECC[0:7] MA[0:12] MBA[0:1] MDQS[0:8] VTT_+1.25V VTT_+1.25V VTT_+1.25V R46 25R R54 25R R62 25R R70 25R R78 25R R86 25R R94 25R R102 25R R110 25R R118 25R R124 25R R130 25R R136 25R R166 25R R174 25R R202 25R R208 25R R214 25R R220 25R R226 25R R232 25R R238 25R R246 25R R252 25R MA5 MA7 MA2 MBA0 MDQS8 MA12 MA3 MDQS1 MDQS0 MDQS7 MDQS5 MDQS6 MA9 MA1 MA8 MA11 MA6 MDQS4 MDQS2 MDQS3 MA4 MBA1 MA10 MA0 MA5 MA3 MDQS7 MBA0 MBA1 MA1 MDQS5 MA4 MA9 MDQS8 MDQS1 MDQS6 MA10 MA0 MA2 MA11 MDQS0 MA12 MA6 MA7 MDQS4 MDQS2 MA8 MDQS3 R45 22R R53 22R R61 22R R69 22R R77 22R R85 22R R93 22R R101 22R R109 22R R117 22R R123 22R R129 22R R135 22R R165 22R R173 22R R201 22R R207 22R R213 22R R219 22R R225 22R R231 22R R237 22R R245 22R R251 22R PMA2 PMA9 PMA12 PMA4 PMA10 PMA11 PMA3 PMA6 PMA8 PMA7 PMA1 PMA5 PMA0 PMDQS1 PMDQS6 PMDQS8 PMDQS5 PMBA0 PMDQS7 PMDQS0 PMDQS4 PMBA1 PMDQS3 PMDQS2 PMA[0:12] PMBA[0:1] PMDQS[0:8] MDQ[0:63] VTT_+1.25V R44 25R R52 25R R60 25R R68 25R R76 25R R84 25R R92 25R R100 25R R108 25R R116 25R R122 25R R128 25R R134 25R R140 25R R146 25R R152 25R R158 25R R164 25R R172 25R R180 25R R186 25R R192 25R R196 25R R200 25R R206 25R R212 25R R218 25R R224 25R R230 25R R236 25R R244 25R R250 25R MDQ52 MDQ36 MDQ61 MDQ63 MDQ48 MDQ33 MDQ53 MDQ44 MDQ38 MDQ58 MDQ34 MDQ40 MDQ39 MDQ45 MDQ55 MDQ51 MDQ47 MDQ60 MDQ59 MDQ43 MDQ54 MDQ49 MDQ50 MDQ37 MDQ32 MDQ56 MDQ42 MDQ57 MDQ46 MDQ41 MDQ35 MDQ62 MDQ43 MDQ44 MDQ50 MDQ58 MDQ55 MDQ52 MDQ53 MDQ51 MDQ38 MDQ54 MDQ42 MDQ39 MDQ41 MDQ45 MDQ59 MDQ47 MDQ46 MDQ40 MDQ60 MDQ57 MDQ61 MDQ49 MDQ48 MDQ36 MDQ63 MDQ62 MDQ56 MDQ32 MDQ37 MDQ35 MDQ34 R43 22R R51 22R R59 22R R67 22R R75 22R R83 22R R91 22R R99 22R R107 22R R115 22R R121 22R R127 22R R133 22R R139 22R R145 22R R151 22R R157 22R R163 22R R171 22R R179 22R R185 22R R191 22R R195 22R R199 22R R205 22R R211 22R R217 22R R223 22R R229 22R R235 22R R243 22R R249 22R PMDQ49 PMDQ46 PMDQ42 PMDQ38 PMDQ61 PMDQ56 PMDQ54 PMDQ52 PMDQ51 PMDQ35 PMDQ37 PMDQ32 PMDQ41 PMDQ48 PMDQ40 PMDQ34 PMDQ60 PMDQ62 PMDQ57 PMDQ43 PMDQ39 PMDQ53 PMDQ47 PMDQ59 PMDQ50 PMDQ55 PMDQ63 PMDQ44 PMDQ45 PMDQ58 PMDQ33 MDQ33 PMDQ36 VTT_+1.25V R42 25R R50 25R R58 25R R66 25R R74 25R R82 25R R90 25R R98 25R R106 25R R114 25R R120 25R R126 25R R132 25R R138 25R R144 25R R150 25R R156 25R R162 25R R170 25R R178 25R R184 25R R190 25R R194 25R R198 25R R204 25R R210 25R R216 25R R222 25R R228 25R R234 25R R242 25R R248 25R MDQ25 MDQ7 MDQ9 MDQ29 MDQ6 MDQ27 MDQ11 MDQ31 MDQ12 MDQ17 MDQ20 MDQ22 MDQ14 MDQ30 MDQ3 MDQ26 MDQ18 MDQ15 MDQ24 MDQ1 MDQ8 MDQ0 MDQ2 MDQ19 MDQ5 MDQ10 MDQ23 MDQ4 MDQ16 MDQ28 MDQ13 MDQ21 MDQ2 MDQ14 MDQ13 MDQ4 MDQ7 MDQ11 MDQ17 MDQ8 MDQ1 MDQ19 MDQ20 MDQ16 MDQ25 MDQ30 MDQ31 MDQ26 MDQ15 MDQ12 MDQ21 MDQ9 MDQ18 MDQ3 MDQ6 MDQ24 MDQ22 MDQ0 MDQ23 MDQ10 MDQ5 MDQ28 MDQ29 MDQ27 R41 22R R49 22R R57 22R R65 22R R73 22R R81 22R R89 22R R97 22R R105 22R R113 22R R119 22R R125 22R R131 22R R137 22R R143 22R R149 22R R155 22R R161 22R R169 22R R177 22R R183 22R R189 22R R193 22R R197 22R R203 22R R209 22R R215 22R R221 22R R227 22R R233 22R R241 22R R247 22R PMDQ12 PMDQ21 PMDQ11 PMDQ22 PMDQ25 PMDQ19 PMDQ26 PMDQ29 PMDQ14 PMDQ18 PMDQ27 PMDQ23 PMDQ8 PMDQ13 PMDQ3 PMDQ7 PMDQ17 PMDQ1 PMDQ15 PMDQ5 PMDQ4 PMDQ31 PMDQ24 PMDQ28 PMDQ9 PMDQ20 PMDQ10 PMDQ6 PMDQ16 PMDQ2 PMDQ0 PMDQ30 PMDQ[0:63]

Figure 11. DDR SDRAM Termination

CompactPCI Reference Design, Rev. 1

14 Freescale Semiconductor Example Interface Schematics ETHERA[0:24] GTX_CLK125 ETHERA7 CFG16 ETHERA4ETHERA5ETHERA6 CFG11 CFG10 CFG9 ETHERA11 TXD12TXD13TXD15TXD16TXD17 CFG21 CFG22 CFG32 CFG31 CFG17 TXD02TX_EN0 ETHERA2 RXD04RXD06 ETHERA8 RXD07RX_DV0 ETHERA18 ETHERA20 ETHERA21 ETHERA22 TXD00TXD01TXD03TXD04TXD05TXD06TXD07TX_ER0TX_CLK0GTX_CLK0 ETHERA0 ETHERA1 RXD00RXD01 ETHERA3 RXD02 ETHERA4 RXD03 ETHERA5 ETHERA6 RXD05 ETHERA7 ETHERA9 ETHERA10 RX_ER0RX_CLK0 ETHERA14 CRS0 ETHERA15 COL0 ETHERA16 ETHERA17 ETHERA19 ETHERA23 ETHERA24 ETHERA12 ETHERA13 E8 G8 A7 B7 C7 D7 F7 A6 C8 B8 C6 B6 E6 F6 A5 B5 D5 D3 B4 D4 D2 E5 D6 C3 G7 E11 G11 H11 J11 K11 J10 A10 B10 B11 D11 D10 C10 F10 G10 H9 A9 B9 C9 E9 F9 H8 A8 E10 D9 F8 E2 TSEC2_COL TSEC1_COL TSEC2_CRS TSEC1_CRS TSEC2_TXD0 TSEC2_TXD1 TSEC2_TXD2 TSEC2_TXD3 TSEC2_TXD4 TSEC2_TXD5 TSEC2_TXD6 TSEC2_TXD7 TSEC1_TXD0 TSEC1_TXD1 TSEC1_TXD2 TSEC1_TXD3 TSEC1_TXD4 TSEC1_TXD5 TSEC1_TXD6 TSEC1_TXD7 TSEC2_RXD0 TSEC2_RXD1 TSEC2_RXD2 TSEC2_RXD3 TSEC2_RXD4 TSEC2_RXD5 TSEC2_RXD6 TSEC2_RXD7 TSEC1_RXD0 TSEC1_RXD1 TSEC1_RXD2 TSEC1_RXD3 TSEC1_RXD4 TSEC1_RXD5 TSEC1_RXD6 TSEC1_RXD7 TSEC2_TX_EN TSEC2_TX_ER TSEC1_TX_EN TSEC1_TX_ER TSEC2_RX_DV TSEC2_RX_ER TSEC1_RX_DV TSEC1_RX_ER TSEC2_TX_CLK TSEC1_TX_CLK TSEC2_RX_CLK TSEC1_RX_CLK EC_GTX_CLK125 TSEC2_GTX_CLK TSEC1_GTX_CLK MPC8540 U11G TSEC1 TSEC2 Clocking GbE LVdd1 LVdd2 LVdd3 LVdd4 A4 E7 C5 H10 +3.3V Reset Configuration Boot ROM Location bit 0 Boot ROM Location bit 1 Boot ROM Location bit 2 TSEC1 Protocol TSEC2 Protocol RIO Device ID bit 6 RIO Device ID bit 7 Local Bus Output Hold bit 0 Local Bus Output Hold bit 1 CFG17 CFG9 CFG10 CFG11 CFG16 CFG21 CFG22 CFG31 CFG32 CFG[1:32]

Figure 12. MPC8540 Gb Ethernet Interface

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 15 Example Interface Schematics RIO[0:39] RIO0 RIO1 RIO2 RIO3 RIO4 RIO5 RIO6 RIO7 RIO8 RIO9 RIO10 RIO11 RIO12 RIO13 RIO14 RIO15 RIO16 RIO17 RIO18 RIO19 RIO20 RIO21 RIO22 RIO23 RIO24 RIO25 RIO26 RIO27 RIO28 RIO29 RIO30 RIO31 RIO32 RIO33 RIO34 RIO35 RIO36 RIO37 RIO38 RIO39 RIO_TCLK RIO_TCLK* RIO_TFRAME RIO_TFRAME* RIO_TD0 RIO_TD0* RIO_TD1 RIO_TD1* RIO_TD2 RIO_TD2* RIO_TD3 RIO_TD3* RIO_TD4 RIO_TD4* RIO_TD5 RIO_TD5* RIO_TD6 RIO_TD6* RIO_TD7 RIO_TD7* RIO_RCLK RIO_RCLK* RIO_RFRAME RIO_RFRAME* RIO_RD0 RIO_RD0* RIO_RD1 RIO_RD1* RIO_RD2 RIO_RD2* RIO_RD3 RIO_RD3* RIO_RD4 RIO_RD4* RIO_RD5 RIO_RD5* RIO_RD6 RIO_RD6* RIO_RD7 RIO_RD7* AC20 AE21 AE24 AE25 AE18 AD18 AC18 AE19 AD19 AC19 AE20 AD20 AD21 AC21 AE22 AD22 AC22 AE23 AD23 AC23 Y25 Y24 AE27 AE26 T25 T24 U25 U24 V25 V24 W25 W24 AA25 AA24 AB25 AB24 AC25 AC24 AD25 AD24 RIO_TD0 RIO_TD1 RIO_TD2 RIO_TD3 RIO_TD4 RIO_TD5 RIO_TD6 RIO_TD7 RIO_RD0 RIO_RD1 RIO_RD2 RIO_RD3 RIO_RD4 RIO_RD5 RIO_RD6 RIO_RD7 RIO_TD0- RIO_TD1- RIO_TD2- RIO_TD3- RIO_TD4- RIO_TD5- RIO_TD6- RIO_TD7- RIO_RD0- RIO_RD1- RIO_RD2- RIO_RD3- RIO_RD4- RIO_RD5- RIO_RD6- RIO_RD7- RIO_TCLK RIO_RCLK RIO_TCLK- RIO_RCLK- RIO_TFRAME RIO_RFRAME RIO_TFRAME- RIO_RFRAME- MPC8540 U11C RIO_TXCLK_IN RIO_TXCLK_IN- AF24 AF25

Figure 13. MPC8540 RapidIO Interface

CompactPCI Reference Design, Rev. 1

16 Freescale Semiconductor Example Interface Schematics CFG[1:32] CFG17 CFG18 CFG19 CFG20 CFG21 CFG22 CFG23 CFG24 CFG25 CFG26 CFG27 CFG28 CFG29 CFG30 CFG31 CFG32 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 45 39 34 28 21 15 10 4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND

+3.3V

VCC

VCC 7 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1OE 2OE 3OE 4OE U13 IDT54FCT162244/FP 1 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 48 25 24

10K,5%

RN4

1 2

2 3 +3.3V

3 4 5

5 4 6 10

10 6 +3.3V 7

7 8

8 9 9 RN2 10K,5% 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 S2 SW DIP-8 S4 SW DIP-8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 2 7 10 15 3 6 11 14 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 MRST D0 D1 D2 D3 CLK U14 74LV175 4 5 9 1 12 13 Reset Configuration TSEC2 Protocol RIO Tx CLK Source bit 0 RIO Tx CLK Source bit 1 PCI Width (32/64) RIO Device ID bit 6 RIO Device ID bit 7 PCI I/O Impedance PCI Arbiter PCI Debug PCI Mode Config Memory Debug Config DDR Debug Config PCI/PCI-X Output Hold bit 0 PCI/PCI-X Output Hold bit 1 Local Bus Output Hold bit 0 Local Bus Output Hold bit 1 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 R257 10K +3.3V 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 45 39 34 28 21 15 10 4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 GND GND GND GND GND GND GND GND HRESET

+3.3V

VCC

VCC 7 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1OE 2OE 3OE 4OE U12 IDT54FCT162244/FP 1 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 48 25 24 SYSCLK

10K,5%

RN3

1 2

2 3 +3.3V

3 4 5

5 4 6 10

10 6 +3.3V 7

7 8

8 9 9 RN1 10K,5% 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 S1 SW DIP-8 S3 SW DIP-8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Reset Configuration Sys_PLL Ratio bit 1 Sys_PLL Ratio bit 3 Core_PLL Ratio bit 0 Host/Agent Select bit 0 Host/Agent Select bit 1 Boot ROM location bit 0 Boot ROM location bit 1 Boot ROM location bit 2 CPU Boot Sequence bit 0 CPU Boot Sequence bit 1 Sys_PLL Ratio bit 0 Sys_PLL Ratio bit 2 Core_PLL Ratio bit 1 CPU Boot Configuration TSEC Width TSEC1 Protocol

Figure 14. MPC8540 Power on Configuration Logic

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 17 Example Interface Schematics PCI[0:86] PCI28 PCI36 PCI37 PCI39 PCI46 PCI47 PCI0 PCI11 PCI15 PCI18 PCI19 PCI23 PCI29 PCI30 PCI33 PCI34 PCI1 PCI21 PCI38 PCI45 PCI58 PCI59 PCI2 PCI3 PCI4 PCI5 PCI6 PCI7 PCI8 PCI9 PCI10 PCI12 PCI13 PCI17 PCI20 PCI24 PCI25 PCI26 PCI27 PCI31 PCI32 PCI35 PCI40 PCI41 PCI42 PCI43 PCI44 PCI14 PCI16 PCI22 AD36 AD37 AD39 AD46 AD47 AD63 PCI63 AD0 AD11 AD15 AD18 AD19 AD23 AD29 AD30 AD33 AD34 AD54AD60AD62 PCI54 PCI60 PCI62 AD1 AD21 AD28 AD38 AD45 AD48AD49AD50AD52AD53AD56AD58 AD59 PCI48 PCI49 AD61 PCI50 PCI52 PCI53 PCI56 PCI61 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD12 AD13 AD17 AD20 AD24 AD25 AD26 AD27 AD31 AD32 AD35 AD40 AD41 AD42 AD43 AD44 AD51AD55AD57 PCI51 PCI55 PCI57 AD14 AD16 AD22 AC13 AB13 Y13 V13 AH12 AG12 AE12 AD12 AB12 Y12 W12 V12 AH11 AG11 AF11 AE11 AA10 Y10 W10 AH9 AG9 AF9 AE9 AD9 AG8 AF8 AC8 AB8 AH7 AE7 AD7 AH6 AF18 AF17 AE17 AB17 AA17 Y17 W17 V17 AF16 AE16 AD16 AC16 AB16 W16 V16 AH15 AG15 AD15 AC15 AB15 AA15 Y15 W15 V15 AH14 AG14 AF14 AE14 AD14 AC14 AB14 AA14 PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_AD32 PCI_AD33 PCI_AD34 PCI_AD35 PCI_AD36 PCI_AD37 PCI_AD38 PCI_AD39 PCI_AD40 PCI_AD41 PCI_AD42 PCI_AD43 PCI_AD44 PCI_AD45 PCI_AD46 PCI_AD47 PCI_AD48 PCI_AD49 PCI_AD50 PCI_AD51 PCI_AD52 PCI_AD53 PCI_AD54 PCI_AD55 PCI_AD56 PCI_AD57 PCI_AD58 PCI_AD59 PCI_AD60 PCI_AD61 PCI_AD62 PCI_AD63 PCIX/PCI MPC8540 U11A PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_REQ64 PCI_ACK64 PCI_PERR PCI_SERR PCI_REQ0 PCI_REQ1 PCI_REQ2 PCI_REQ3 PCI_REQ4 PCI_GNT0 PCI_GNT1 PCI_GNT2 PCI_GNT3 PCI_GNT4 PCI_PAR PCI_PAR64 PCI_FRAME PCI_C_BE0 PCI_C_BE1 PCI_C_BE2 PCI_C_BE3 PCI_C_BE4 PCI_C_BE5 PCI_C_BE6 PCI_C_BE7 Y14 Y11 V14 V11 AF5 AF3 AF6 AA9 AE4 AE5 AE6 AH8 AH5 AG4 AG5 AG6 W14 W11 AA11 AB10 AE13 AC12 AD11 AH13 AC10 AD10 AH10 AD13 AG13 AG10 C_BE2 REQ0 PCI_GNT1 PCI_GNT2 PCI_GNT3 PCI_GNT4 PCI76 IRDY* PCI72 PAR PCI85 GNT0 PCI64 C_BE0 PCI75 TRDY* PCI74 FRAME* PCI65PCI66 PCI67PCI68PCI69PCI70PCI71 C_BE1 PCI73 C_BE3 C_BE4 C_BE5 PCI77 C_BE6 PCI78 C_BE7 PCI79PCI80PCI81 PAR64 PCI83PCI84 STOP* DEVSEL* IDSEL* REQ64* ACK64* SERR* PCI82 PERR* PCI86 PCICLK PCI_REQ64 PCI80 Reset Configuration PCI I/O Impedance PCI Arbiter PCI Debug PCI Mode Config PCI Width (32/64) SYSCLK CFG23CFG24 PCI_GNT1 CFG25 PCI_GNT2 CFG26 PCI_GNT3 CFG20 PCI_GNT4 PCI_REQ64 CFG[1:32]

Figure 15. MPC8540 PCI/PCI-X Interface

CompactPCI Reference Design, Rev. 1

18 Freescale Semiconductor Example Interface Schematics SOUT1 SIN1 SOUT0 SIN0 R8 R9 R10 R11 T9 T6 T5 T4 T1 U1 U2 U3 U4 U7 U8 U9 U10 V9 V6 V5 V4 V3 V2 V1 W1 W2 W3 W6 W7 W8 W9 Y9 Y1 Y2 Y3 Y4 Y5 Y6 AA8 AA7 AA4 AA3 AA2 AA1 AB1 AB2 AB3 AB5 AB6 AC7 AC4 AC3 AC2 AC1 AD1 AD2 AD5 AD6 AE3 AE2 PD4 PD5 PD6 PD7 PD8 PD9 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PC10 PC11 PC12 PC14 PC16

PD28/UART_SIN1 PD31/UART_SIN0 Alt. 10/100 Eth. 10/100 Alt. PD26/UART_RTS1 PC13/UART_CTS1 PC15/UART_CTS0 PD29/UART_RTS0

PC18/FEC_TX_CLK PC17/FEC_RX_CLK PD27/UART_SOUT1 PD30/UART_SOUT0

Alt. DUART Alt. Eth. 10/100 Alt.

CPM Alt. DUART Alt. MPC8540 U11H PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB4/FEC_TXD3 PB5/FEC_TXD2 PB6/FEC_TXD1 PB7/FEC_TXD0 PB8/FEC_RXD0 PB9/FEC_RXD1 PB10/FEC_RXD2 PB11/FEC_RXD3 PB12/FEC_CRS PB13/FEC_COL PB14/FEC_TX_EN PB15/FEC_TX_ER PB16/FEC_RX_ER PB17/FEC_RX_DV PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 J1 J2 J3 J4 J5 J6 J7 J8 L1 L2 L3 L4 L5 L8 L9 K8 K7 K6 K3 K2 K1 P9 P8 P7 P6 P5 P4 P3 P2 P1 H1 H2 N1 N4 N5 N6 N7 N8 N9 R1 R2 R3 R4 R5 R6 R7 M9 M8 M7 M6 M3 M2 M1 L10 L11 P11 P10 N10 N11 M10

Figure 16. MPC8540 Parallel I/O and DUART Interface

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 19 Example Interface Schematics E12 A12 AF13 AA13 U13 R13 N13 T14 P14 M14 H14 B14 AF15 U15 R15 N15 Y16 U16 T16 P16 M16 AD17 U17 R17 N17 H17 C17 A17 W18 K18 F18 AB19 J19 C19 R20 L20 H20 B20 U21 M22 H22 C22 W23 P23 K23 F23 J24 E24 L25 G25 AG26 V26 R26 B26 AF27 M27 H27 C27 B27 K28 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64 GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 GND81 GND82 GND83 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97 GND98 GND99 POWER MPC8540 U11I OVdd1 OVdd2 OVdd3 OVdd4 OVdd5 OVdd6 OVdd7 OVdd8 OVdd9 OVdd10 OVdd11 OVdd12 OVdd13 OVdd14 OVdd15 OVdd16 OVdd17 OVdd18 OVdd19 OVdd20 OVdd21 OVdd22 OVdd23 OVdd24 OVdd25 OVdd26 OVdd27 OVdd28 OVdd29 OVdd30 OVdd31 OVdd32 OVdd33 OVdd34 OVdd35 OVdd36 OVdd37 OVdd38 OVdd39 OVdd40 OVdd41 OVdd42 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 L7 L6 T2 T7 T3 T8 Y7 Y8 K4 E4 V8 E3 B3 K5 V7 K9 D1 N3 H3 U5 N2 C2 H4 C4 U6 D8 G9 M5 M4 W4 W5 T10 T12 F11 Y23 K10 P22 V10 P12 AF7 AF2 AF4 AA5 R19 U20 R25 U26 AA6 C11 H12 AE1 AB7 AE8 AB9 AB4 G12 AH4 AD4 AC5 AD3 AC6 AD8 AC9 M12 AG3 AG7 W13 W19 W21 AF12 AF10 AA12 AA16 AA20 AE10 AE15 AB26 AB11 AC11 AC17 AG27 +3.3V 0.1uF 0.1uF C42 C52 0.1uF 0.1uF AH19 AH18 AH17 L12 K12 C41 C51 10uF C58 AVdd1 AVdd2 AVdd3 0.1uF 0.1uF C40 C50 SENSE_VSS SENSE_VDD 10uF C57 0.1uF 0.1uF CORE &PLL CORE Supply C39 C49 MPC8540 U11E VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 10uF C56 0.1uF 0.1uF T13 T15 T17 P13 P15 P17 U12 R12 U14 R14 N14 R16 N16 M13 M15 M17 C38 C48 10uF C55 0.1uF 0.1uF C37 C47 10uF C54 +1.2V 0.1uF 0.1uF C68 0.1uF C36 C46 10uF C53 0.1uF 0.1uF C67 0.1uF C35 C45 C71 10uF 0.1uF 0.1uF C66 0.1uF C34 C44 0.1uF 0.1uF C65 0.1uF C33 C43 C70 10uF C64 0.1uF C63 0.1uF C62 0.1uF C69 10uF C61 0.1uF C60 0.1uF C59 0.1uF

Figure 17. MPC8540 Power Connections

CompactPCI Reference Design, Rev. 1

20 Freescale Semiconductor Example Interface Schematics F25 F24 F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 J1F CONN6x25 J2F CONN6x22 PCI39 PCI19 PCI64 PCI24 PCI85 PCI46 PCI75 PCI13 PCI31 PCI32 PCI10 PCI5 PCI82 +5V +5V AD39 PAR64 PCI73 AD19 C_BE0 AD50 PCI50 C_BE1 PCI65 AD2 PCI2 AD24 C_BE2 PCI66 AD60 PCI60 AD36 PCI36 GNT0 C_BE6 PCI70 AD46 AD22 PCI22 TRDY* AD13 AD31 AD57 PCI57 AD32 AD53 PCI53 AD43 PCI43 AD10 AD27 PCI27 ACK64* PCI81 AD5 PERR* E22 E21 E20 E19 E18 E17 E16 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16 E15 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 J2E J1E CONN6x22 CONN6x25 PCI51 PCI20 PCI37 PCI6 +5V +5V +3.3V AD51 AD20 PAR PCI72 AD44 PCI44 C_BE4 PCI68 PCICLK PCI86 AD11 PCI11 AD0 PCI0 AD37 STOP* PCI77 AD6 AD58 PCI58 AD25 PCI25 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 J2D J1D CONN6x22 CONN6x25 PCI76 PCI28 PCI23 PCI47 PCI8 PCI61 PCI16 PCI33 PCI3 +3.3V +3.3V IRDY* AD54 PCI54 AD28 AD23 AD47 C_BE7 PCI71 AD14 PCI14 AD8 AD61 AD40 PCI40 AD16 AD33 AD3 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 J2C J1C CONN6x22 CONN6x25 Connector J1 Connector J2 PCI9 PCI48 PCI29 PCI74 PCI4 PCI62 PCI34 PCI15 PCI79 PCI80 PCI17 +5V +5V AD9 AD48 AD29 FRAME* AD4 AD41 PCI41 AD62 AD34 AD15 IDSEL* AD55 PCI55 REQ64* AD17 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B25 B24 B23 B22 B21 B20 B19 B18 B17 B16 B15 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 J2B J1B CONN6x22 CONN6x25 +5V +5V PCI12 PCI21 PCI84 PCI52 PCI1 PCI38 PCI59 PCI67 PCI7 PCI83 PCI26 PCI78 PCI45 PCI18 PCI30 +3.3V +3.3V AD63 PCI63 AD56 PCI56 AD42 PCI42 REQ0 AD52 AD38 AD59 AD49 PCI49 AD35 PCI35 C_BE5 PCI69 AD45 AD12 AD21 AD1 C_BE3 AD7 SERR* AD26 DEVSEL* AD18 AD30 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 J2A CONN6x22 J1A CONN6x25 PCI[0:86]

Figure 18. Compact PCI J1 and J2 Connectors

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 21 Example Interface Schematics SYSCLKA SYS_HRESET* R258 1K SYS_HRESET_N +3.3V 31 29 27 25 23 21 19 17 15 13 11 9 8 12 16 20 24 28 32 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9

Q10 Q11

2 GND GND GND GND GND GND GND

GND 1 RESET MPC9448 U15 VDD MR MAX6314 4 3 MPC9448 U14 PCLK PCLK CCLK CLK_SEL CLK_STOP OE VCC VCC VCC VCC VCC VCC VCC 3 4 2 1 5 6 7 10 14 18 22 26 30 +3.3V C72 0.1uF +3.3V R257 1K +3.3V S5 Reset Switch 5 OUT VDD GND Y1 66MHz 8 4 +3.3V

Figure 19. Clock and Reset Logic

CompactPCI Reference Design, Rev. 1

22 Freescale Semiconductor Example Interface Schematics +1.2V 3.6mF C87 + 2 +2.5V 300uF C80 +5V L2 79nH + 1 CMPSH-3 C86 0.1uF D4 C77 150uF + Q1 MTB50N06VL Q2 MTB50N06VL R265 1.7m L1 2.5A 10uH, C83 4.7uF +

D3 R266 39R

1 2 R264 39R C82 0.1uF C84 4.7nF 1N5820 C78 0.1uF C85 4.7nF R260 9K1

5 6 7 8 4 3 1 24 23 21 22 18 19 12 11

S2 LX

D1 D2 D3 D4 FB DL

3 BST CSL S1 CSH

2 PDRV NDRV AGND PGND

VDD 20 G N/C MMSF3P02HD 4 1 U17

R261 10K R262 100K

VCC 9 MAX1624 6 7 2 U18 PWROK D0 D1 D2 D3 D4 LG FREQ CC2 CC1 REF MAX1624 C79 4.7uF FB CS EXT 2 7 6 5 8 + 17 16 15 14 13 10 C81 0.1uF R259 R047 MAX1627 C88 0.56uF U16 V+ REF OUT SHDN GND C89 0.6nF C90 CERAMIC 1.0uF 5 4 1 3 8 R267 40.1K R268 2K R263 100K C76 0.1uF +5V SW1 SW2 SW3 SW4 SW SPDT SW SPDT SW SPDT SW SPDT C75 0.47uF C74 68uF + +5V C73 68uF + This sets 1.2V +3.3V Note :- Default settings for Switchs D4 D3 D2 D1 D0 0 1

Figure 20. Local Power Supply Logic

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 23 Example Interface Schematics C98 10uF +

+1.5V LED_GREEN CLK25 0.01uF C99 D10 R274 332

DD_M DD_P DB_M DC_M DC_P DB_P DA_M DA_P

CON1 RJ45 LNK_10 8 7 6 5 4 3 2 1 R278 22R VDDO_3_3V

AVDDH_3_3V Local 1.5V supply for PHY

1 2 4 3 LED_GREEN 5 D9 R273 332 +3.3V +3.3V BYP GND VOUT

SENSE

1000P/3KV OUT LNK_100 C100

VDD GND

Y2 25MHz LED_GREEN LT1763CS8-1.5 LT1763CS8 8 4 U20 D8 GND GND VIN SHDN R272 332

8 5 6 7 LNK_1000 VDDO_3_3V R285 75 R288 75 R291 75 C91 0.1uF

VDDO_3_3V +3.3V

R282 75 LED_GREEN

R271 332 24 23 22 21 20 19 18 17 16 15 14 13

DPLX VSSC

MCT1 MCT2 MCT3 MCT4

GND_L7 MX1_P MX2_P MX3_P MX4_P MX1_M MX2_M MX3_M MX4_M

GND_L6

GND_L5

GND_L4

LED_GREEN C92 0.1uF GND_L3

R270 332 GND_K6

GND_K5 AVDDH_N5

GND_K4

RX GND_K3

AVDDH_3_3V GND_J6

GND_J5

GND_J4

GND_H6

LED_GREEN

D5 GND_H5

R269 332 GND_H4

GND_G6

GND_G5

GND_G4 GND_F6

LED_LINK_100A LED_LINK_10A LED_LINK_1000A LED_DUPLEXA LED_TXA LED_RXA GND_F5

1:1 1:1 1:1 1:1 GND_F4 1:1 1:1 1:1 1:1

GND_E6

GND_E5

GND_E4 GND_D6

Pulse H5007 Pulse GND_D5

GND_D4

GND_C7 GND_C4 TCT1 TD1_P TD1_M TCT2 TD2_P TD2_M TCT3 TD3_P TD3_M TCT4 TD4_P TD4_M U21 1 2 3 4 5 6 7 8 9 10 11 12 0.1uF 0.1uF 0.1uF 0.1uF R277 49.9 R279 49.9 C106 C108 C115 C117 MDI3_MA MDI0_MA MDI3_PA MDI2_PA MDI2_MA GND_L5 AVDDH_N5 GND_L6 AVDDL_M3 GND_J5 GND_K5 GND_K6 GND_L7 AVDDL_M7 AVDDL_M8 GND_L4 HDAC_PA HDAC_NA MDI1_PA MDI1_MA N2 M3 N3 L4 M4 N4 J5 K5 L5 M5 N5 K6 L6 M6 N6 L7 M7 N7 M8 N8 N9 AVDDL_2_5V AVDDL_2_5V AVDDL_2_5V AVDDL_2_5V R286 49.9 R287 49.9 R289 49.9 R290 49.9 R292 49.9 R293 49.9 R283 49.9 R284 49.9 GND GND GND GND GND GND GND AVDDL AVDDL AVDDL AVDDH

MDI1_P MDI2_P MDI3_P

MDI0_M MDI1_M MDI2_M MDI3_M

R280 4.7K

HDAC_P HDAC_N CTRL_25

TDI MDI0_P

N1 M9 MDI0_PA

0.01uF 0.01uF

CONFIG_4 VDDO_3_3V RST

M2 L9 R276 2.49K 1% 2.49K R276 0.01uF 0.01uF CONFIG_4

TDO TRST

M1 L8 254.7K R275 C116 C118

C107 C114

CONFIG_3 GND

L3 K9 GND_L3 LED_LINK_10A

MDI3_PA MDI2_MA MDI2_PA

MDI3_MA

CONFIG_2 VDDO_3_3V AVDDL MDI0_MA MDI1_MA MDI1_PA MDI0_PA

L2 K8 AVDDL_L2 CONFIG_2

CONFIG_6 TMS

L1 K7 LED_RXA

CONFIG_1 GND

K4 J9 LED_LINK_1000A GND_K3

CONFIG_0 VSSC

K3 J8 VSSC

CONFIG_5 RESET

K2 J7 LED_LINK_100A

GND TCK

K1 J6 GND_J6

LED_TX GND

J4 H9 GND_J4 LED_TXA

LED_RX VDDO

J3 H8 VDDO_J3 LED_RXA

VDDO XTAL1

J2 H7 CLK25 VDDO_H7

GND XTAL2

J1 H6 GND_H6

LED_DPLX GND

H5 G9 GND_H5 LED_DUPLEXA

LED_LINK1000 GND

H4 G8 GND_H4 LED_LINK_1000A

DVDDL DVDDL

H3 G7 DVDDL_H3A DVDDL_G7A

GND TXD_7

H2 G6

TXD7

GND_G6 INTERFACE

LED_LINK100 TXD_6

H1 F9 TXD6 LED_LINK_100A

LED_LINK10 GND

F8 G5 NOTE: TIED PIN SEL_2_5V TO GND 3.3V FOR I/O GND_G5 LED_LINK_10A

SEL_2_5V GND

G4 F7 GND_G4

GND DVDDH

G3 F6 GND_F6

GND

TXD_5 MDC G2 F5 GND_F5 TXD5

M88E1011

INT

TXD_4 TIES HIGH

G1 E9 2110K R281 TXD4

MDC GND

F4 E8 GND_F4

VDDO DVDDH

F3 E7 VDDO_E7

GND TXD_3

F2 E6 TXD3 GND_E6

MDIO

GND TXD_2

E5 F1 DESCRIPTION TXD2 GND_E5

MDIO GND

E4 D9 GND_E4

CLK125 DVDDL

E3 D8 DVDDL_E3A

DVDDL CTRL_15

E2 D7 DVDDL_D7A

ENABLE PAUSE 0 PHYADR[4] = 0 PHYADR[3] = AUTO-NEGOTIATION ADVERTISE ALL CAPABILI PREFER SLAVE ENABLE 125 MHZ CLOCK ENABLE MDI CROSSOVER ENABLE AUTO NEGOTIATION MODE GMII TO COPPER MDC/MDIO INTERFACE INT SIGNAL IS ACTIVE 50 OHM TERMINATION

GND TXD_1

D6 E1 PHYADR[2] = 0, PHYADR[1] = 0, PHYADR[0] 0 DISABLE AUTO SELECTION OF FIBER/COPPER ENABLE ENERGY DETECT GMII TO COPPER TXD1 GND_D6

RXD_7 SCLK_P

D3 C9 RXD7

RXD_6 SCLK_M

C3 C8 RXD6

GND SOUT_P

D2 C7 GND_C7

RXD_5 SOUT_M

C2 B9 RXD5

RXD_4 SIN_P

D1 A9 RXD4

GND

RXD_3 SIN_M

B8 C1 LED_RX LED_LINK10 VDDO_3_3V VDDO_3_3V RXD3 CONNECTION LED_LINK100 LED_LINK1000 COMA TX_EN TXD_0 TX_ER GTX_CLK AVDDL CRS TX_CLK GND GND COL RX_ER VDDO GND RX_DV RX_CLK VDDO RXD_0 RXD_1 RXD_2 U19 A1 A2 B2 A3 B3 B1 A4 B4 A5 B5 A6 B6 A7 B7 A8 C4 D4 C5 D5 C6 111 111 110 101 010 000 BIT[2:0] MDC MDIO AVDDL_B1 TXD0 TX_ER GTX_CLK CRS TX_CLK COL RX_ER RX_DV RX_CLK RXD0 RXD1 RXD2 TX_EN GND_C4 VDDO_C6 GND_D4 VDDO_C5 GND_D5 Pin To Configuration Constant Mapping Configuration To Pin SYS_HRESET* GTX_CLK125 PIN CONFIG5 CONFIG0 CONFIG6 +3.3V CONFIG1CONFIG2 100 CONFIG3 CONFIG4 C93 4.7UF + TXD0

VDDO_3_3V C113 0.1uF

+1.5V C105 0.1uF AVDDL_M8 C97 0.01uF VDDO_J3

C112 0.01uF DVDDL_H3A AVDDL_M7

ETHERA10 TX_CLK ETHERA7ETHERA6ETHERA5 TXD7 TXD6 ETHERA3 TXD5 ETHERA2ETHERA1 TXD3 ETHERA0 TXD2 ETHERA24 TXD1 ETHERA23 RX_CLK ETHERA21ETHERA20 RX_ER ETHERA19 RXD7 ETHERA18 RXD6 ETHERA17 RXD5 ETHERA16 RXD4 RXD3 ETHERA14 RXD2 ETHERA12ETHERA13 RXD0 CRS COL C104 0.01uF ETHERA9 TX_ER ETHERA22 RX_DV ETHERA8 TX_EN ETHERA4 TXD4 ETHERA11 GTX_CLK ETHERA15 RXD1 C96 0.1uF VDDO_H7

DVDDL_1_5V C111 0.1uF

DVDDL_G7A AVDDL_M3

VDDO_3_3V C103 0.1uF VDDO_E7

DVDDL_1_5V C110 0.01uF C95 0.01uF AVDDL_L2

C102 0.01uF +2.5V DVDDL_E3A VDDO_C6

C109 0.1uF C94 0.1uF AVDDL_B1

C101 0.1uF

VDDO_C5 DVDDL_D7A AVDDL_2_5V AVDDL_2_5V ETHERA[0:24]

Figure 21. Gb Ethernet Transceiver

CompactPCI Reference Design, Rev. 1

24 Freescale Semiconductor Example Interface Schematics Note Polarity Note SIN0 SOUT0 SIN1 SOUT1 0.1uF C121 + +3.3V C123 0.1uF + 0.1uF C120 + 4 5 12 11 9 10 6 16 V- C2- C2+ T1IN T2IN VCC R1OUT R2OUT MAX3232 U22 C1+ C1- R1IN T1OUT R2IN T2OUT V+ GND 1 3 8 7 2 13 14 15 C119 0.1uF + C122 0.1uF + 5 9 4 8 3 7 2 6 1 5 9 4 8 3 7 2 6 1 P1 D9 Connector P2 D9 Connector

Figure 22. RS232 Interface Logic

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 25 Example Interface Schematics B A B A C C

223956-1

1 223956-1 J3 J7 1 223955-2 223955-2 Guide Pin J5 J6 Guide Pin A4 A3 A2 A1 A4 A3 A2 A1 B4 B3 B2 B1 B4 B3 B2 B1 C4 C3 C2 C1 C4 C3 C2 C1 +3.3V +5V RIO_TD3 RIO_TD4 RIO_TD6 RIO_TCLK RIO_TCLK* RIO_TD2 RIO_TD2* RIO_TD1 RIO_TD0 RIO_TD0* RIO_TD7* RIO_TD4* RIO_TD1* RIO_TD7 RIO_TD5* RIO_TD3* RIO_TD5 RIO_TD6* RIO_TFRAME* RIO_TFRAME H1 G1 HG1 F1 E1 FG1 H2 G2 HG2 F2 E2 FG2 H3 G3 HG3 F3 E3 FG3 H4 G4 HG4 F4 E4 FG4 H5 G5 HG5 F5 E5 FG5 H6 G6 HG6 F6 E6 FG6 H7 G7 HG7 F7 E7 FG7 H8 G8 HG8 F8 E8 FG8 H9 G9 HG9 F9 E9 FG9 H10 G10 HG10 F10 E10 FG10 F1 F2 F3 F4 F5 F6 F7 F8 F9 E1 E2 E3 E4 E5 E6 E7 E8 E9 H1 H2 H3 H4 H5 H6 H7 H8 H9 G1 G2 G3 G4 G5 G6 G7 G8 G9 F10 E10 H10 G10 FG1 FG2 FG3 FG4 FG5 FG6 FG7 FG8 FG9 HG1 HG2 HG3 HG4 HG5 HG6 HG7 HG8 HG9 FG10 HG10 EF GH 1460902-2 BG DG FG HG J4 AB CD AB CD EF GH A1 B1 BG1 C1 D1 DG1 A2 B2 BG2 C2 D2 DG2 A3 B3 BG3 C3 D3 DG3 A4 B4 BG4 C4 D4 DG4 A5 B5 BG5 C5 D5 DG5 A6 B6 BG6 C6 D6 DG6 A7 B7 BG7 C7 D7 DG7 A8 B8 BG8 C8 D8 DG8 A9 B9 BG9 C9 D9 DG9 A10 B10 BG10 C10 D10 DG10 A1 A2 A3 A4 A5 A6 A7 A8 A9 B1 B2 B3 B4 B5 B6 B7 B8 B9 C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 A10 B10 C10 D10 BG1 BG2 BG3 BG4 BG5 BG6 BG7 BG8 BG9 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DG8 DG9 BG10 DG10 RIO_RD3 RIO_RD6 RIO_RD5* RIO_RD6* RIO_RD0* RIO_RD3* RIO_RCLK* RIO_RD5 RIO_RD1* RIO_RD0 RIO_RD1 RIO_RD2* RIO_RCLK RIO_RD4* RIO_RD7 RIO_RD7* RIO_RD2 RIO_RD4 RIO_RFRAME RIO_RFRAME* RIO7 RIO_TD1* RIO1 RIO_TCLK* RIO9 RIO_TD2* RIO5 RIO_TD0* RIO8 RIO_TD2 RIO3 RIO_TFRAME* RIO0RIO2 RIO_TCLK RIO_TFRAME RIO4RIO6 RIO_TD0 RIO_TD1 RIO13 RIO_TD4* RIO12 RIO_TD4 RIO21 RIO_RCLK* RIO35 RIO_RD5* RIO15 RIO_TD5* RIO25 RIO_RD0* RIO27 RIO_RD1* RIO30 RIO_RD3 RIO32RIO34 RIO_RD4 RIO_RD5 RIO37RIO38 RIO_RD6* RIO_RD7 RIO19RIO20 RIO_TD7* RIO_RCLK RIO31 RIO_RD3* RIO11 RIO_TD3* RIO39 RIO_RD7* RIO33 RIO_RD4* RIO23 RIO_RFRAME* RIO10 RIO_TD3 RIO16RIO17RIO18 RIO_TD6 RIO_TD6* RIO_TD7 RIO22 RIO_RFRAME RIO29 RIO_RD2* RIO36 RIO_RD6 RIO14 RIO_TD5 RIO24RIO26 RIO_RD0 RIO28 RIO_RD1 RIO_RD2 RIO[0:39]

Figure 23. Optional RapidIO Connector

CompactPCI Reference Design, Rev. 1

26 Freescale Semiconductor Example Interface Schematics COP_TRST COP_CKSTP_IN* R300 10K +3.3V R299 2K R298 10K KEY 2 4 6 8 10 12 14 16 J8 COPCONN 1 3 5 7 9 11 13 15 R297 10K R296 10K +3.3V R295 10K R294 10K COP_TDO COP_TDI COP_TCK COP_TMS COP_SRESET COP_HRESET COP_CKSTP_OUT* DEBUG0DEBUG1 COP_TCK DEBUG2 COP_TDI DEBUG3 COP_TDO DEBUG4 COP_TMS DEBUG5 COP_TRST DEBUG6 COP_HRESET DEBUG7 COP_SRESET DEBUG8 COP_CKSTP_IN* COP_CKSTP_OUT* DEBUG[0:8]

Figure 24. MPC8540 COP Debug Connector

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 27 Document Revision History 5 Document Revision History Table 2 provides a revision history for this white paper. Table 2. Document Revision History

Revision Date Change(s)

1 11/2004 Template update. Updated schematics related to DDR hook-up. 0 8/2003 Initial release.

CompactPCI Reference Design, Rev. 1

28 Freescale Semiconductor Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 29 Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

CompactPCI Reference Design, Rev. 1

30 Freescale Semiconductor Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

CompactPCI Reference Design, Rev. 1

Freescale Semiconductor 31 How to Reach Us: Home Page: www.freescale.com email: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 Information in this document is provided solely to enable system and software implementers to [email protected] use Freescale Semiconductor products. There are no express or implied copyright licenses Europe, Middle East, and Africa: granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the Freescale Halbleiter Deutschland GmbH information in this document. Technical Information Center Freescale Semiconductor reserves the right to make changes without further notice to any Schatzbogen 7 81829 Muenchen, Germany products herein. Freescale Semiconductor makes no warranty, representation or guarantee +44 1296 380 456 (English) regarding the suitability of its products for any particular purpose, nor does Freescale

+46 8 52200080 (English) Semiconductor assume any liability arising out of the application or use of any product or circuit, +49 89 92103 559 (German) and specifically disclaims any and all liability, including without limitation consequential or +33 1 69 35 48 48 (French) [email protected] incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor Japan: data sheets and/or specifications can and do vary in different applications and actual performance Freescale Semiconductor Japan Ltd. may vary over time. All operating parameters, including “Typicals” must be validated for each Technical Information Center customer application by customer’s technical experts. Freescale Semiconductor does not convey

3-20-1, Minami-Azabu, Minato-ku any license under its patent rights nor the rights of others. Freescale Semiconductor products are Tokyo 106-0047 Japan 0120 191014 not designed, intended, or authorized for use as components in systems intended for surgical +81 3 3440 3569 implant into the body, or other applications intended to support or sustain life, or for any other [email protected] application in which the failure of the Freescale Semiconductor product could create a situation Asia/Pacific: where personal injury or death may occur. Should Buyer purchase or use Freescale Freescale Semiconductor Hong Kong Ltd. Semiconductor products for any such unintended or unauthorized application, Buyer shall

Technical Information Center indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, 2 Dai King Street Tai Po Industrial Estate, and distributors harmless against all claims, costs, damages, and expenses, and reasonable Tai Po, N.T., Hong Kong attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated +800 2666 8080 with such unintended or unauthorized use, even if such claim alleges that Freescale [email protected] Semiconductor was negligent regarding the design or manufacture of the part. For Literature Requests Only: Freescale Semiconductor Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. The Literature Distribution Center PowerPC name is a trademark of IBM Corp. and is used under license. All other product or service P.O. Box 5405 names are the property of their respective owners. Denver, Colorado 80217 (800) 441-2447 © Freescale Semiconductor, Inc. 2004. 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@ hibbertgroup.com

MPC8540PCIWP Rev. 1 11/2004