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Serial Rapidio (SRIO)

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Serial Rapidio (SRIO) KeyStone Architecture Serial Rapid IO (SRIO) User's Guide Literature Number: SPRUGW1C November 2010–Revised April 2019 Contents Preface....................................................................................................................................... 19 1 Introduction ....................................................................................................................... 20 1.1 General RapidIO System.................................................................................................. 21 1.1.1 RapidIO Architectural Hierarchy................................................................................. 21 1.1.2 RapidIO Interconnect Architecture .............................................................................. 22 1.1.3 Physical Layer 1x/4x LP-Serial Specification .................................................................. 22 1.2 RapidIO Feature Support in SRIO ....................................................................................... 23 1.3 Standards ................................................................................................................... 24 1.4 External Devices Requirements .......................................................................................... 24 2 SRIO Functional Description................................................................................................ 25 2.1 Overview..................................................................................................................... 26 2.1.1 Peripheral Data Flow ............................................................................................. 26 2.1.2 Clock Summary.................................................................................................... 29 2.1.3 SRIO Packets...................................................................................................... 30 2.1.3.1 Operation Sequence........................................................................................ 30 2.1.3.2 Example Packet—Streaming Write....................................................................... 31 2.1.3.3 Control Symbols............................................................................................. 31 2.1.3.4 SRIO Packet Type .......................................................................................... 32 2.2 SRIO Pins ................................................................................................................... 33 2.3 Functional Operation....................................................................................................... 33 2.3.1 SerDes Macro and its Configurations .......................................................................... 33 2.3.1.1 Enabling the PLL............................................................................................ 34 2.3.1.2 Enabling the Receiver ...................................................................................... 34 2.3.1.3 Enabling the Transmitter ................................................................................... 35 2.3.1.4 SerDes Configuration Example ........................................................................... 35 2.3.2 Direct I/O Operation............................................................................................... 38 2.3.2.1 Writing to LSU_SETUP_REG0............................................................................ 42 2.3.2.2 Full Bit ........................................................................................................ 44 2.3.2.3 Busy Bit....................................................................................................... 44 2.3.2.4 Detailed Data Path Description ........................................................................... 48 2.3.2.5 TX Operation ................................................................................................ 50 2.3.2.6 RX Operation ................................................................................................ 52 2.3.2.7 Reset and Powerdown ..................................................................................... 53 2.3.2.8 Special Conditions .......................................................................................... 53 2.3.2.9 Scheduling ................................................................................................... 54 2.3.2.10 Error Handling ............................................................................................... 55 2.3.2.11 DirectIO Programming Considerations................................................................... 56 2.3.3 Message Passing ................................................................................................. 57 2.3.3.1 RX Operation ................................................................................................ 58 2.3.3.2 TX Operation ................................................................................................ 63 2.3.3.3 Message Passing Software Requirements .............................................................. 67 2.3.4 Maintenance ....................................................................................................... 71 2.3.5 Doorbell Operation ................................................................................................ 71 2.3.6 Atomic Operations................................................................................................. 73 2.3.7 Congestion Control................................................................................................ 73 2 Contents SPRUGW1C–November 2010–Revised April 2019 Submit Documentation Feedback Copyright © 2010–2019, Texas Instruments Incorporated www.ti.com 2.3.7.1 Detailed Description ........................................................................................ 73 2.3.8 Endianness......................................................................................................... 76 2.3.8.1 Translation for Memory-Mapped Register Space....................................................... 76 2.3.8.2 Translation for Payload Data .............................................................................. 77 2.3.9 Interrupt Operation ................................................................................................ 78 2.3.9.1 General Description ........................................................................................ 78 2.3.9.2 Interrupt Registers .......................................................................................... 81 2.3.9.3 Interrupt Handling ........................................................................................... 81 2.3.9.4 Interrupt Pacing ............................................................................................. 81 2.3.10 Reset and Powerdown .......................................................................................... 82 2.3.10.1 Reset and Powerdown Summary ......................................................................... 83 2.3.10.2 Software Shutdown Details ................................................................................ 83 2.3.11 Reset Isolation for RapidIO ..................................................................................... 84 2.3.11.1 Device Reset with Continued RapidIO Operation ...................................................... 84 2.3.11.2 RapidIO Reset with Continued Device Operation ...................................................... 86 2.3.12 RX Multicast and Multiple DestID Support.................................................................... 86 2.3.12.1 Discrete Multicast ID Support ............................................................................. 88 2.3.12.2 Promiscuous ID and DestID Support..................................................................... 88 2.3.13 Daisy-Chain Operation and Packet Forwarding.............................................................. 88 2.3.14 Error Handling and Logging..................................................................................... 91 2.3.15 Initialization Example ............................................................................................ 98 2.3.15.1 Enabling SRIO Peripheral ................................................................................. 98 2.3.15.2 PLL, Ports, Device ID and Data Rate Initialization ..................................................... 98 2.3.15.3 Peripheral Initializations .................................................................................... 98 2.3.16 Optimization Techniques ...................................................................................... 100 2.3.16.1 Overview.................................................................................................... 100 2.3.16.2 Packet Segmentation ..................................................................................... 100 2.3.16.3 Packet DMA Channel Configuration .................................................................... 101 2.3.16.4 Context Allocation ......................................................................................... 101 2.3.16.5 Receive Flow Configuration .............................................................................. 101 2.3.16.6 Priority Scheduling ........................................................................................ 101 2.3.16.7 Transmit and Receive Operations......................................................................
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