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Signal Processing Software and Firmware Strategy

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Signal Processing Software and Firmware Strategy SIGNAL PROCESSING SOFTWARE AND FIRMWARE STRATEGY Document number ................................................................. WP2‐040.200.012‐PLA‐001 Revision ........................................................................................................................... 1 Author ............................................................................................................... W. Turner Date ................................................................................................................. 2011‐01‐29 Status ............................................................................................... Approved for release Name Designation Affiliation Date Signature Submitted by: W. Turner Signal Processing SPDO 2011‐03‐26 Domain Specialist Accepted by: Approved by: K.Cloete Project Engineer SPDO 2011‐03‐29 WP2‐040.200.012‐PLA‐001 Revision : 1 DOCUMENT HISTORY Revision Date Of Issue Engineering Change Comments Number C 2009‐12‐08 ‐ First draft release for internal review DOCUMENT SOFTWARE Package Version Filename Wordprocessor MsWord Word 2007 32‐WP2‐040.200.012‐PLA‐001‐1_SW_FW_Strategy Block diagrams Other ORGANISATION DETAILS Name SKA Program Development Office Physical/Postal Jodrell Bank Centre for Astrophysics Address Alan Turing Building The University of Manchester Oxford Road Manchester, UK M13 9PL Fax. +44 (0)161 275 4049 Website www.skatelescope.org 2011‐01‐29 Page 2 of 24 WP2‐040.200.012‐PLA‐001 Revision : 1 TABLE OF CONTENTS 1 INTRODUCTION ............................................................................................. 6 1.1 Purpose of the document ....................................................................................................... 6 2 REFERENCES ................................................................................................ 6 3 OVERVIEW .................................................................................................. 8 4 DESIGN PROCESS .......................................................................................... 8 4.1 Functional Specification ........................................................................................................ 11 4.2 Verification Plan .................................................................................................................... 12 4.3 Packaging Specification ......................................................................................................... 13 4.4 Development Plan ................................................................................................................. 13 5 BUILT IN SELF TEST AND POWER ON SELF TEST ................................................... 13 6 CONFIGURATION MANAGEMENT .................................................................... 14 7 CHANGE CONTROL ...................................................................................... 15 7.1 Change procedure ................................................................................................................. 16 7.1.1 Request change ............................................................................................................. 16 7.1.2 Screen request .............................................................................................................. 19 7.1.3 Investigate impact ......................................................................................................... 19 7.1.4 Review ........................................................................................................................... 21 7.1.5 Implement ..................................................................................................................... 22 7.1.6 Verification .................................................................................................................... 22 7.1.7 Closure .......................................................................................................................... 22 7.2 Notes on the change management procedure ..................................................................... 22 8 APPENDIX CONFIGURATION MANAGEMENT TOOLS ............................................. 24 LIST OF FIGURES Figure 1 Heirarchical Development ........................................................................................................ 8 Figure 2 ASIC Spiral Development .......................................................................................................... 9 Figure 3 ASIC Design Methodology ....................................................................................................... 10 Figure 4: Change Management Procedure. .......................................................................................... 16 2011‐01‐29 Page 3 of 24 WP2‐040.200.012‐PLA‐001 Revision : 1 LIST OF TABLES No table of figures entries found. LIST OF ABREVIATIONS AA .................................. Aperture Array ASIC .............................. Application-Specific Integrated Circuit ASKAP .......................... Australian SKA Pathfinder ASTRON ....................... Netherlands Foundation for Research in Astronomy CAD ............................... Computer Aided Design CDR ............................... Critical Design Review CISRO ........................... (Australian) Commonwealth Scientific and Research Organisation CoDR ............................. Conceptual Design Review DRM .............................. Design Reference Mission EMC .............................. Electro Magnetic Compatibility EX .................................. Example FFT ................................ Fast Fourier Transform FoV ................................ Field of View FPGA ............................. Field Programmable Gate Array GNU .............................. GNU’s Not Unix INAF .............................. National Institute for Astrophysics IP ................................... Intellectual Property JIVE ............................... Joint Institute for VLBI in Europe JPL ................................ Jet Propulsion Labs KASI .............................. Korea Astronomy Space-Science Institute LEMP ............................. Logistic Engineering Management Plan MPIfR ............................ Max Planck Institute for Radio Astronomy MTBF ............................. Mean Time Before Failure MTTR ............................ Mean Time To Replacement NCRA ............................ National Centre for Radio Astrophysics NRC-HIA ....................... National Research Council Herzberg Institute of Astrophysics NRF ............................... National Research Foundation OPAR ............................ Observatorie de Paris OS ................................. Operating System PAF ............................... Phased Array Feed PDR ............................... Preliminary Design Phase PSU ............................... Power Supply Voltages RFI ................................. Radio Frequency Interferance 2011‐01‐29 Page 4 of 24 WP2‐040.200.012‐PLA‐001 Revision : 1 RMON ........................... Remote Monitoring RMP .............................. Risk Management Plan SEMP ............................ System Engineering Management Plan SRS ............................... (Sub) Systems Requirement Specification SRR ............................... (Sub) Systems Requirement Review SKA ............................... Square Kilometre Array SNMP ............................ Simple Network Management Protocol SPDO ............................ SKA Program Development Office TDP ............................... Technology Development Program TIFR .............................. Tata Institute of Fundamental Research UCAM ............................ University of Cambridge UMAN ............................ University of Manchester UORL ............................ University of Orleans UOXF ............................ University of Oxford VLBI ............................... Very Long Baseline Interferometry WBSPF .......................... Wide Band Single Pixel Feed 2011‐01‐29 Page 5 of 24 WP2‐040.200.012‐PLA‐001 Revision : 1 1 Introduction The aim of this document is to provide a strategy for the handling of embedded software and firmware within the Signal Processing domain of the SKA. This document is complimentary to the software strategies documented in both the System’s Strategy and Philosophy document [1] and the WP2.6 Strategy for Development of – and Cost Estimation for – Software and Computing Architectures [2]. This document covers the strategies for the embedded software and firmware associated with FPGA and ASIC development. This document is part of a series generated in support of the Signal Processing CoDR which includes the following: Signal Processing High Level Description Technology Roadmap Design Concept Descriptions Signal Processing Requirements Signal Processing Costs Signal Processing Risk Register Signal Processing Strategy to Proceed to the Next Phase Signal Processing Co DR Review Plan Software & Firmware Strategy 1.1 Purpose of the document The overall purpose of this document is to Provide a first pass of the design process for FPGAs and ASICs Identify the need for configuration control of FPGA and ASIC software, firmware and supporting scripts and test harnesses. Identify the need for change control of FPGA and ASIC software Identify commonly used change control tools. 2 References [1] K Cloete et al, Strategies and Philosophies WP2‐005.010.030‐TR‐001
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