SEMI and VLSI Research Unveil End-To-End Generations That Have Been Critical to the Semiconductor Semiconductor Manufacturing Industry Report Industry

2019

MEPTECA Quarterly Publication of The Microelectronics Packaging & Test EngineeringRe Council portVolume 23, Number 4 WINTER

POST-LAYOUT VERIFICATION, ANALYSIS AND TEST CONSIDERATIONS FOR 2.5/3D HETEROGENEOUS ADVANCED PACKAGES page 24

+ Packaging & Assembly for High-Temperature Electronics Part V – Reliability and Testing page 20

INSIDE THIS ISSUE

FPGA makers need The demand for greater They won’t replace Binghamton University to take the lead in cost performance and silicon, but GaN and Professor of Chemistry initiating the qualifica- differentiation has fueled SiC are becoming much and Materials Science tion of alternative the development of more attractive as wins Nobel Prize in 4 subcontractors. 14 advanced packaging. 15 prices drop. 28 Chemistry.

Mark LaPedusSEMICONDUCTOR ENGINEERING Tel:Email: [email protected] 714-1570 (650) MEPTEC Report MEPTEC Report Vol. 23, No. by 4. MEPCOMLLC, 141 HewittStreet, Published quarterly SC29486. Summerville, 2020 by Copyright MEPCOM LLC. reserved. may not All rights Materials Dr. K. Kirschman Randall Kevin Mentor Rinebold of the isaPublicationThe MEPTECReport ofthe be reproduced in whole or in part without written permission. MEPTEC Report is sent without charge to members ofMEPTEC. tomembers issentwithoutcharge For non-members, permission. without written MEPTECReport yearlybe reproducedinwhole orinpart subscriptions are available for Feldman Engineering Corp.IraEngineering Feldman Feldman 141 Hewitt Street,Hewitt 141 29486 Summerville,SC Ron Jones Art Director/Designer Brown Gary Ron JonesN-AbleGroup International Benson Chan BinghamptonUniversityBenson Chan Nick Leonardi SMARTMicrosystems MEPTEC ExecutiveDirectorMEPTEC Booz Allen Hamilton Demmin Booz Allen Jeff Martin Hart Microelectronics Packaging & Test Herb Reiter 360 BC Group DixonBC Douglass 360 Jack Belani IndiumCorporation Belani Jack Elle Anna Gualtieri Technology MEPTEC Board Advisory Phil Marcoux Sales Manager Sales Manager Calvin Cheung MEPCOM LLC Publisher MEPCOM Joel Camarda Altierre Honorary Advisors Editor BetteCooper Engineering Council Engineering Council Ivor Barber Special Advisors Seth Alavi Sunsil Board Members In Memoriam Contributors Mary Olsson Mary Ira Feldman Bance Hom Bance Gary Catlin Gary N-Able Group International Skip Fehr Rob Cole $75 inthe United States, $80USinCanada andMexico, contactGinaEdwards at and information 408-858-5493. rates and $95USelsewhere. Foradvertising eda 2 asic Consulting asic 2 eda TopLineCorporation PPM Associates Gina Edwards Gina ASE (US) Inc. (US) ASE ® , Business Siemens A AMD R&D Consultant R&D 15 24 DEPARTMENTS MENTOR KEVIN RINEBOLD ronment isessentialtomanageall oftheseprocesses. performance. To ensure consistency and automation a single envi physical,for sign-off electrical,mated thermal,manufacturing and SEMICONDUCTOR ENGINEERING MARK LAPEDUS The growth of these designs demands an efficient, auto proven an demands designs these of growth The traditional silicon-baseddevices inthemarket. silicon carbide(SiC), setting thestagefor ashowdown against power semiconductorsbasedongalliumnitride (GaN)and prices drop. Several vendors are rolling outthenextwave of 20 temperatures. absolute are equations in temperatures *All be thepredominant one. ture isnottheonlyfactor, andmightnot rimental processes. However, tempera- and chemical interactions, and otherdet- decomposition, migration,metallurgical thermal energyenable restructuring, to more degraded reliabilitybecause thereis with fasteraging,shorterlifetimes, and I PART 4 drically shapedpinsthatmustbeheld cylin are columns Solder market. COTS attaching solderballsthatdominatethe packages issubstantiallydifferent from balls. solder of billions suming Off-The-Shelf (COTS)FPGA devicescon when comparedtovolumesofCommercial per wrappedsoldercolumnsareminuscule Total annualvolumesof70millioncop annually.produced are packages outline FPGA devicesspreadover100different individual 75,000 around such, as ment; in alow-volumemanufacturingenviron packages withsoldercolumnsareproduced FPGAStates”. United the of Resiliency Defense IndustrialBaseandSupplyChain and StrengtheningtheManufacturing Industrial Policyreporttitled,“Assessing 13806) Order Executive (Presidential as describedintheDepartmentofDefense manufacturing baseandafragilemarket devices includeadiminishingdomestic a robustandresilientproductionofFPGA Supply ChainResiliency requirements. temperatures inordertosatisfymission to withstandintenseradiationandhigh Hardened FPGA packagesareconstructed Radiation warfighters. of delivery for commitments fulfill to industry defense devices couldresultinthefailureof A productionstoppageofcriticalFPGA (QML-38535). List Manufacturer Qualified rized toassembleFPGA devicesinthe a listofsupplychainsubcontractorsautho Defense Logistics Agency (DLA)publishes The step. production final their as columns tractor toattachcopperwrappedsolder (FPGA) relyonasinglesourcesubcon ers ofFieldProgrammableGate Arrays addressed aconcernthatthemainproduc 2019 PREVIOUSLY, PART IOF THE FALL TopLine Corporation Hart Martin FacePeril? Pt. II Does the FPGAIndustry ≈200–250°C temperatures above at ability concerns reli- polymeric packagingmaterialsraise high-temperature electronics,because typically apply onlytothelowerendof and molding. (Although thelatter three underfill, encapsulation, wirebonds, form ofdieandsubstrateattachments, assembly alsoplayacritical role, inthe ated testing. However, packaging and acceler reliability and connection with passive components spring tomindin previous Parts. few aspectshavebeentoucheduponin a high-temperature electronics,and for tion assembly forhigh-temperature opera- electronics packagingand relation to accelerated testing,in reliability and presents afewbasicobservationson raised. temperature is packaging materialsas and assembly by variations of thebasicproperties of and high-temperature operation.PartsII,III materials and technology in regardto a glimpse of assemblyandpackaging plus techniques, packaging materialsand must beaccommodated by assemblyand their high-temperaturecapabilitiesthat introduced semiconductordevicesand R&D ConsultantforElectronics Technology Dr. RandallK.Kirschman V–ReliabilityandTestingPart Electronics Packaging &AssemblyforHigh-Temperature

CALL TOCALL ACTION | MEPTEC REPORT Attaching soldercolumnstoFPGA Several riskarchetypesforachieving alarmed. be to reason have Stakeholders www.binghamton.edu/s3ip/index.html. http:// at: Site IEEC requestthroughthe upon available is text Full “Flashes.” S3IP University Binghamton fromthe Technology articles Art contains Briefs University.State-of-the- Binghampton The (IEEC), Center ElectronicsEngineering Director,Associate Chan, Integrated Benson by us broughtto featureis This Science Daily,Science 7/8/19) #11257,file using anypoweratall.(IEEC glass couldrecognizeyourfacewithout it withfaceID.Inthefuture,onepieceof time youglanceatyourphonetounlock substantial computationalresourcesevery low-power electronics. AI gobblesup a conceptcouldopennewfrontiersfor is objects inert inside (AI) intelligence artificial Embedding glass. thin of piece and deepneuralnetworksintoasingle the normalsetupofcameras,sensors sources. They useopticstocondense requiring anysensors,circuitsorpower glass thatcanrecognizeimageswithout a methodtocreatepiecesof“smart” CNFETs thatperformsthesametasks microprocessor withmorethan14,000 16-bit a demonstrated They practical. carbon nanotubemicroprocessorsmore representing amajorsteptowardmaking tional silicon-chipfabricationprocesses, processor ,whichcanbebuiltusingtradi tional siliconcounterparts. The micro faster, greeneralternativetotheirtradi transistors, whicharewidelyseenasa microprocessor fromcarbonnanotube MIT researchers havebuiltamodern of Wisconsin-Madison Researchers from theUniversity 28 ofBinghamtonUniversity A specialfeature courtesy TechnologyState-of-the-Art Briefs Increasing temperature is associated Certainly, semiconductor devices and This [1] | IV exploredthechallenges presented MEPTEC REPORT MEPTEC REPORT “Callto Action” . Reliability is aseriouschallenge | PACKAGING OF THIS SERIESOF ARTICLES MEPTEC REPORT Part, concluding this series, TECH BRIEFS MEPTECRe [2] . (See PartsIandII) WINTER 2019 WINTER 2019 havedevised WINTER 2019

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MARKET TRENDS – MARKET TRENDS

GaN andSiCare becomingmuch more attractive as

- A QuarterlyPublicationofTheMicroelectronicsPackaging&TestEngineeringCouncil three activationenergies,E Figure 1.ComparisonofArrheniusratesfor for threeE Figure 1isalogR-versus-TplotofEq. 0.52 between roughly and range eV to of theactivationenergy, E is the Arrhenius relation: ture onelectroniccomponentfailurerates via extrapolation—theeffect oftempera- Arrhenius Model whether itisapplicableornot. The ques- plicated guideforreliabilityprediction— lines ofthe Arrhenius relation. as astraightlineincontrasttothecurved included forcomparison,whichappears nential relationship(describedbelow)is attachment services. attachment process ofattainingQML statusforcolumn tive subcontractorstoundergo thearduous scratch, itcouldtake24monthsforalterna delay.without from However,starting readily availabletodayinthesupplychain tured copperwrappedsoldercolumnsare chain areready, willingandabletoprovide microelectronic subcontractorsinthesupply Multiple source. second a qualifying not for is mostoftencitedastheprimaryreason A lackoffundingbyFPGA manufacturing products. their to columns solder wrapped multiple subcontractorstoattachcopper- are notrequiredtovoluntarilyqualify Monetary Considerations process. artisan non-automated, a tally columns toFPGA packagesisfundamen solder wrapped packages. copper Attaching the processofattachingcolumnstoFPGA must beemployedduringeverystepin Talentedallowed. skills are operator defects manufacturing No column. single a aging dam without planarized be columns 1752 requires thattheentirematrixarrayofupto process. step reflow assembly and final A at anytimeduringtheentireattachment over falling or slanting without fixtures vertically inplacebyprecisionmachined Producers ofFPGAdeviceswithsoldercolumns(inAlphabeticalorder). at −100°C). at for-10°C line(dashedgrayline,arbitrarilysetto1 prefactors, plustheexponentialdoubling- k is Boltzmann’s constant (0.862e−4 eV/K), eV/K), Boltzmann’s(0.862e−4 is constant k

Rate, R= A Companies thatproduceFPGA devices manufac Fortunately,U.S. royalty-free, Daily,7/24/19) #11280,file Science be improved.(IEEC cesses forthemateriallayersstillneedto computer chipsasthemanufacturingpro can beusedforcommerciallyavailable a fewmoreyearsbeforethetechnology semiconductors workbest.Itmaytake which combinationsofinsulatorsand out find to wants team the Now models. cal propertiesoutshinesallprevious The prototypewithitssuperiorelectri to producethenewultra-thintransistor. fluoride, calcium of made insulator novel a used They materials. (2D) dimensional ics isbecomingpossible--withtwo- onto thebasicmaterialcoatedwithsilver powder underhighatmosphericpressure spray aconductivemetalintheformof lization, aplasmasprayheadisusedto framework ofthisspecialtypemetal with electroniccomponents. Within the not suitablepreviouslyforanassembly solderable printedcircuitboardsthatwere materials intoelectricallyconductingand The noveltechnologyturnsapluralityof cuit boardswithelectroniccomponents. ing Lumitronix hassucceededinintegrat of Technology Researchers attheViennaUniversity 8/29/19) #11328,News, Nanowerk file open-source chiparchitecture.(IEEC microprocessor isbasedontheRISC-V as commercialmicroprocessors. The miniaturization stepinmicroelectron an extremelysmallsize. This nextbig properties andcanbeminiaturizedto thin transistor, withexcellentelectrical For packaging and assembly, values A widespreadapproachtopredict— It iscomfortingtohavesomeuncom- and T is and T plasma-metallized flexible printed cir printed flexible plasma-metallized Where prefactor A isaconstant, E tive impact on traditional design and verification methods. PACKAGING – a called theactivationenergy, isanassociatedenergy (eV) a valuesinthisrange. An expo- temperature (K).* temperature absolute • exp(−E havecreatedanultra- a /kT) Eq. 1 ® a a , are reported , arereported , withadjusted , A SIEMENS BUSINESS [3][4] - - . ------R isafunctionofE treatment forhighoperatingtemperatures? tion thenishoweffective isan Arrhenius high-temperature electronics an extendedtemperaturerangetypicalof perature dependencies,particularlyover tion energies, andthusarangeoftem- range—or evena“spectrum”—ofactiva- mechanisms (processes)representedbya likely haveamenagerieofdegradation electronic assembly(e.g.Figure3)will out, amulti-material,multi-component to failureratevia Arrhenius. metallic growth—asanexample—relates inter how unclear is it Besides, difficult. parisons betweendifferent temperatures the Arrhenius treatmentandmakescom- at aconstanttemperature,whichmuddies at aconstanttemperature rate decreasingconsiderablywithtime growth inan Au-Al wirebondshowthe intermetallic for 2 Figure in data mental temperature. As anexample,theexperi- a high temperatures,manyprocessesexhibit function oftime.However, especiallyat Data from [5] from Data wirebond) ataconstanttemperature (200°C) ing withtime(intermetallicgrowth inAu-Al Figure 2.Exampleofaprocess ratechang something as “simple” as a wirebond can something as“simple”awirebondcan peace in the Worldthe in Order.peace readiness, possiblytippingthebalanceof ponents couldultimatelydiminishmarket production stoppageofcriticalFPGA com dollars. of Amillions of hundreds industry to strike,potentiallycostingthedefense risk ofwaitingforanunexpecteddisaster prudent investmenttodaycanmitigatethe FPGAfor packages. services Aattachment critical processofcopperwrappedcolumn who arereadyandwillingtoprovidethe multiple microelectronicsubcontractors qualify to is step next The available. copper wrappedsoldercolumnsisalready of manufacturing FPGADomestic devices. resilient andsustainablesupplychainfor initiate asharedvisiontoensurerobust, Conclusion out the support of the FPGAthe maker.of support the out independently applyforQML statuswith As apracticalmattersubcontractorscannot subcontractors. alternative of qualification makers needtotaketheleadininitiating FPGAcolumns. solder wrapped copper qualify multiplesubcontractorstoattach tive byFPGA makerstomitigateriskand be requiredtosupportanacceleratedinitia qualification. would investment sizable A ing isavailabletopayforthecostofQML implies anE column attachmentservicesaslongfund rate changeovertimeataconstant It’s timeforadvocacystakeholdersto MLE combineshigh-resolutionpattern printed circuitboardapplications. The ing, MEMS,biomedicalandhigh-density lithography needsforadvancedpackag ogy developedtoaddressfutureback-end ary next-generationlithographytechnol (IEEC file #11148,file (IEEC 4/15/19) R&D, roles oflightandmatterarereversed. the laserismade.Inphonon are controlledbythematerialfromwhich laser, thepropertiesoflightoutput in alldirections.Inastandardoptical travel alongdistancewithoutspreading a laserpointerareinsync,thebeamcan sync. Becausethewavesemerging from tions becomeintenseandfellintoperfect cal laserbeam. The mechanicalvibra force ofradiationatthefocusanopti which islevitatedagainstgravitybythe mechanical vibrationsofthenanoparticle, nanoparticle. The researchersstudiedthe phonon laserusinganopticallylevitated laser forsound.bydemonstratinga MLE The EVGroup (EVG)hasunveiled Daily,7/10/19) heat toenergy. #11258,file (IEEC Science radiant converting at efficient more much and cellphones,solarpanelsthatare life indevicessuchaslaptopcomputers This couldleadtomuchlongerbattery a 100nanometersgapbetweenthem. by-5mm chipoftwosiliconwaferswith electricity. The teamproduceda5mm- that convertsthermalradiationinto Field RadiativeHeat Transfer Device,’ creating asiliconchip,knownas‘Near- tricity fromheatthanthoughtpossibleby discovered awaytoproducemoreelec University ofUtahengineershave tute ofTechnology Researchers attheRochesterInsti 7/12/19) #11260, Electronicsfile Printed World, silver substrateisbeingformed.(IEEC 50,000°C wherebyaconnectionwiththe by averyhotplasmabeamof10,000- paste. Simultaneously, thecopperisfused One difficulty is that Eq. 1 states that that states 1 Eq. that is difficulty One Furthermore, as has often been pointed Furthermore, ashasoftenbeenpointed . ™ (Maskless Exposure), a revolution a Exposure), (Maskless a that is changing with time thatischangingwithtime a and T; butnota havecreateda Data from [5] from Data ◆ [6][7][8] meptec.org meptec.org . This . This . Even . Even meptec.org

------500°C (Table 1, bottom row). row). (Tablebottom 500°C 1, at eV 3.6 and 300°C, at eV 2 but 22°C, at E gate,” “average,”“effective” or“global” brushed asidebyusingasingle“aggre- ΔT of 10°C needs an E an needs 10°C of ΔT row). (Tablesecond 37°C 1, of ΔT a 500°C at and 20°C, of ΔT a require would it 300°C at but 5.3°C, only of ΔT a require would 22°C at rate of bling meptec.org 22°C.be to taken is temperature **Room increase 10°C every for rate in doubles process Doubling-for-10°C formation rosion, interdiffusion, andintermetallic each withadifferent rate:annealing,cor have severaldegradationmechanisms, about other temperatures? Keeping E Keeping temperatures? other about meptec.org ExecutiveDirector, MEPTEC IraFeldman Fall Ahead exposure canevenremove damage by vibrationorshock.Hightemperature or byacombination)andexacerbated ronmental temperature,byinternalpower, temperature variations(drivenbyenvi- these aremorelikelytofailasaresultof influence, major a be would temperature and assembly). Although constanthigh items particularlyapplicabletopackaging and by otherfactors.Considersolderjoints dependence offailureisovershadowed But forotherprocessesthetemperature filaments), and tion, orgrowthofwhiskers,dendrites tion, outgassing,electrochemicalmigra- pound formation,oxidation,decomposi- cesses, (e.g.diffusion, intermetalliccom- range considered. commonly usedE 125°C, around Arrhenius the and toanextendedtemperaturerange? basis forthisdoubling-for-10°C “rule”— nius—which mightbesupposedisthe tion, underfill, and molding materials. materials. molding and underfill, tion, Similar considerationsapplytoencapsula- holidays’ andcatchingupwithindustry Beyond wishingeveryone‘happy luncheon. Series Speaker Industry tor be tolditwastheDecemberSemiconduc- truth Okay gathering. holiday MEPTEC friends. and family with spent but Ienjoythewarmthofholidays dreary, year of time this find Some rain. hopefully accompaniedbymuchneeded air the in is chill However,the peratures. Valley weareblessedwithmoderatetem- Silicon in here It’sthat America. true here. to casualvisitors,wearegladyou MEPTEC TIME LONG FROM WELCOME! angles: Again keepingE row). first (Table2x 1, than rather 500°C, at 1.2x only but 22°C**, at 3.6x be would below) increase inrate(oraccelerationfactorsee corresponding the 10°C, = ΔT and eV 1 a for all processes over the temperature forallprocessesoverthetemperature Microelectronic Packaging&AssemblySolutions • Wafer Preparation Services • • • • • • MEMS andsensorapplications 1.858.674.4676 |[email protected] |www.icproto.com (OmPP Cavity PlasticQFN/SOICPackages Open-molded/Pre-molded Air A DivisionofPromex Industries We hadaverywellattendedannual North in started has winter of cold The #11303,University,Binghamton 8/15/19) file feature vocalinteraction.(IEEC that numberisgrowingasmoredevices are madearoundtheworldeachyear, and issue. Morethan2billionmicrophones noise fromtheelectronicsisnolongeran boosted highenoughthatthebackground because withthisdesignthesignalcanbe tionary formicrophonemanufacturing, revolu be could findings These own. its that neitherofthosesystemsoffered on actuators –ledtoapredictablelinearity actuation –parallel-plateandlevitation combining twomethodsforelectrostatic control MEMS. The teamfoundthat more reliablewaytouseactuatorsthat mance oftinysensorsbydevelopinga have foundawaytoimprovetheperfor gaining significant momentum and poised and momentum significant gaining (STT-MRAM)RAM magnetoresistive is NVM technologies,spintransfertorque beyond eFlash.. Among variousemerging over thisperiod.MRAMpromiseslife 2024, growingwitha295%CAGR the potentialtoreach$1.2billionby The embeddedmemorymarkethas nia Engineers attheUniversityofCalifor Binghamton Universityresearchers 7/2/19) #11240, Digest, file Semiconductor (IEEC packaging, MEMSandPCBmarkets. development, impactingtheadvanced increasing drivingforceinsemiconductor masks. Heterogeneousintegrationisan eliminating theoverheadcostsofphoto ing withhighthroughputandyield,while MARKET TRENDS 8/12/19) Digest, Semiconductor #11300,file a photoniccrystal.(IEEC with anarrayofnanosizedholesforming silicon frame. The monolayerispatterned layers ofsulfuratoms)suspendedona tungsten atomssandwichedbetweentwo of layer one of up (made monolayer fide waveguide consistsofatungstendisul sity, highercapacityphotonicchips. The lead tothedevelopmentofhigherden tude smallerthantoday’s devices.Itcould devices tosizesthatareordersofmagni proof ofconceptforscalingdownoptical three layersofatomsthin. The workisa device intheworld–awaveguidethatis meptec.org Alternatively, adoublingofratefor Next, considerthemantra that a Some individualphysiochemicalpro- Calculating with Eq. 1 shows that Calculating withEq.1showsthat Considering the rule from other Considering therulefromother doubling-for-10°C “rule”follows wirebonds (twoprimary“wearout” Dicing, backgrinding,pick&place off-the-shelf stock Available inhighvolumesand green moldingcompound RoHS- andREACH-compliant and glasslidswithepoxyseals Matching ceramic,plastic,quartz JEDEC standard outlines superior bondability Gold platedfor to 0.40mm pitch sizes0.80mm to 12x12mm,lead Body sizes3x3mm MARKET TRENDS havedevelopedthethinnestoptical [10] UP [9] . Howdoesthisrelateto Arrhe- members to recent subscribers . This complicationisusually ® ) –perfectforRF/MW, obey Arrhenius. obey Arrhenius. might FRONT a of ≈ 1 eV.1 ≈ of What

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Faster TimetoMarketforYour ICDesigns - - - - - perature electronics stances, andespeciallynotforhigh-tem- circum- parameter specific under only “rule” isnotapplicableingeneral,but Arrhenius treatment. Arrhenius treatment. slopes are similar around 22°C, and for E for and 22°C, around similar are slopes T tion overtimeataconstanttemperature, perature: measuringfailuresordegrada- accelerated testingonlyviaincreasedtem- of, temperature. The followingconcerns tion, radiation),inadditionto,orinstead or environmental(e.g.moisture,accelera- electrical (e.g.voltage,current,power), test. The ideaisoverstress,whichmaybe high-temperature packagingandassembly. there aremanypitfalls,especiallyfor However, inthequestforsuchamethod, cal. A fasterevaluationmethodisneeded. reliability evaluationisgenerallyimpracti- islong,sayyears,real-time component Accelerated Testing Table 1.Variations onthethemeofdoubling-for-10°C rule(usingEq.1). Photo courtesyQuartzdyne,Inc. Figure 3.Adown-hole(well-logging)multi-chipmodulespecifiedfor2yearsoperationat260°C. ture forE temperature, butonlyaroundthistempera- is areasonableapproximationaroundthis “rule” the that confirming slopes, similar in Your SupplyChain”byDavidGreen- the keynote“MakingKGDSilicon Work this criticaltopicisrevisited!Don’t miss excited tocelebrateKGD’s 20thyearas Valley.Silicon in April 21,2020 We are Good Die(KGD) Workshop on Tuesday them. ing 2020sostaytunedasweannounce of othergreatluncheonpresentationsdur sharing herthoughts! There willbeplenty spective tothingsandwasnotshyabout per fresh a brings always Jan Beyond”. on “AdvancedPackagingfor2020and now traditionalyearlyIndustryOutlook Vardaman’s (TechSearch International), Jan mention to Not treats. holiday ing friends, therewasagreatlunchinclud- perature, T 300°C. around similar are slopes the 2 = and theE the example: 125°C last Around the of tion (OCPP Open CavityPlasticPackages • • • for prototype toproduction volumes Plastic OvermoldedPackages- • • • customer samples verification and IC prototype assembly, design Accel factorforE ΔT (°C)forE E TEST a Wire bondedandflipchipdevices packages includingQFNandDFN chip scale Saw-singulated leadframe arrays Overmolded metal with nominimumorders Turn-around in24hoursorless identical toproduction parts Mechanically andelectronically plastic package Available inany Known Our nextfulldayeventistheKnown #11310, Daily,file Science (IEEC 8/8/19) turn clothingintoself-powereddevices. embed smallelectroniccomponentsand to molecules fluorinated and embroidery use which (RF-TENGs), nanogeneragtors ing isbasedonomniphobictriboelectric able andantibacterialself-poweredcloth tion processes.. The waterproof,breath without theneedforexpensivefabrica nation displaysusingsimpleembroidery taining sensors,musicplayersorillumi cloth intoaself-powerede-textilecon is capableoftransforminganyexisting devices throughclothing. This technique allows wearerstocontrolelectronic developed anewfabricinnovationthat Printed ElectronicsWorld,Printed 7/29/19) #11293,file translate intospeech.(IEEC with theirthroatsthatthedevicewould could betrainedtogeneratesignals and decoder. Inthefuture,mutepeople amplifier microcomputer,power board, a smallarmbandthatcontainedcircuit throat andconnecteditwithelectrodesto volunteer’s a over skin the to film the es.. The researchersusedwatertoattach inch 1.2 by 0.6 measures device flexible The film. alcohol polyvinyl of sheet thin throat, theylaser-scribed grapheneona artificial Tosounds. their into make ments rary tattoo,cantransformthroatmove when attachedtothenecklikeatempo valued at$1.1billionin2015andexpect The fiberopticsensormarketwas oped ACS Nanoresearchers havedevel Purdue Universityresearchers have 8/12/19) Digest, Semiconductor ASICs and #11315,file ASSPs. (IEEC play ICs,edge AI accelerators, andother MCUs ,automotive,imaginganddis low-power wearablesandIoT devices, the 28nmnodeandbelow. That includes solution forICproductsmanufacturedat to becomethenextembeddedmemory (eV)fordoublingandΔT=10°C A popularmethodistheaccelerated When therequiredlifetime of a In conclusion,thedoubling-for-10°C Figure 1providesagraphicillustra- doubling-for-10°C line(dashedgray) , higherthantheoperatingtem- ™

a a a wearable artificial throat that, throat artificial wearable a ideal for rapid ) –idealforrapid = 1 eV curve (green line) have have line) (green curve eV 1 = ≈ 1 eV.1 ≈ E For OPER Up Front Call to Action a =1eVanddoubling , often accompanied by an , oftenaccompaniedbyan eeoeeu pcaig s disrup a is packaging Heterogeneous a =1eVandΔT10°C [10] . a = 0.5 eV,0.5 = the

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3.6 0.54 5.3 T exhibit thesamefailuremechanismsat measured E electronic packagingandassembly. The +1 650-472-1192+1 [email protected] Executive Director,MEPTEC Ira Feldman Happy holidaystoyouandyours! shy! be Don’t you. serve best can tions andfeedbackastohowMEPTEC shortly.luncheons and events day full other the Weannouncing 2020. be will busy planningoureventcalendarfor information. more http://www.kgdworkshop.org/and 14 for Please seetheeventinformationonpage law, Engineering. VPNvidia Product plot with slope = −E = slope with plot 1/T appears asastraightlineonlogR-verus- Figure 4.ChangeofE as ed. likely asthetemperaturerangeisexpand- As explainedabove,thisbecomesless mechanisms obeythe Arrhenius relation. a plotforthreeE (dashed grayline). for-10°C exponentialisincludedforcomparison E for illustration;thecombinedcurve(sumofthree es.

laminate arrays) embedded thermalsensorsand SiP, MCM,MEMS,BGA, packages (stackeddie,COB,COF, Custom assemblyforcomplex Flip chipassembly Multiple encapsulationoptions Al andAuwirebond High-volume precision dieattach WINTER 2019 a

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WINTER 2019 I lookforwardtohearingyoursugges- The Advisory Board(AB)hasbeen RECENT PATENTS 10/11/19) #11369?,Binghamtonfile University, power mostlaptopcomputers.(IEEC for subsequentdiscoveriesthatnow teries —workthatprovidedthebasis density, highlyreversiblelithiumbat intercalation chemistryinhigh-power nal patentontheconceptofuse a machine-learningbasedmodel. mation andapertureshapeinformationto by applyingthemeasurementshapeinfor board, circuit printed first the on printed the pluralityofsecondsolderpastesare and paste solder first the when mation ture havethemeasurementshapeinfor aper first the than other apertures second of secondsolderpastesprintedthrough rality ofaperturesandeachaplurality plu the of aperture first a through printed paste solder first a that values probability tion abouteachoftheapertures,obtains of aperturesandapertureshapeinforma printed circuitboardthroughaplurality first a on printed pastes solder of plurality ment shapeinformationabouteachofa inspection apparatusobtainsmeasure EP3501828 – No- A printedcircuitboard YoungKoh (Assignee: Technology)- Pub. lithium-ion batteryHeholdstheorigi leading tothedevelopmentof won theprizeforpioneeringresearch University.Binghamton Whittingham distinguished professorofchemistryat was awardedtoM.Stanley Whittingham, for detectinganomalyinsolderpaste PCB inspectingapparatus,method The 2019NobelPrizeinChemistry #11186,file (IEEC 5/7/19) Sensors, Vibration Sensing,PressureSensing). TemperatureSensing, Acoustic/ Sensing, Sensor, (Strain Optical-Fiber Application Based Sensor, InterferometricDistributed tering BasedSensor, RamanScattering Based DistributedSensor, BrillouinScat basis of Technology;: RayleighScattering growth. The marketissegmentedonthe significant propelling is projects struction con various in sensors optic fiber deploy Additionally, governmentinitiativesto infrastructure arefactorsdrivinggrowth. oil andgasindustryinvestmentsin the in adoption Increasing 2026. to 2016 ed toregisteraCAGRof10.4%from The prefactorshavebeensetatarbitraryvalues This assumes that a component will This assumesthatacomponentwill Thus, aprocessobeying Arrhenius The Arrhenius equationmayberecast logR = logAE = − logR WINTER 2019 asitdoesat T RECENT PATENTS 125 2.0 0.97 9.7 a can vary with temperature if canvarywithtemperatureif ISO 13485: ISO 9001 ISO 13485: ISO 9001 They won’t replace silicon, but MEPTEC REPORT a MEPTEC REPORT : : 2015 Certified values appropriate for valuesappropriatefor 2015 Certified 2016 Certified 2016 Certified MEPTEC REPORT OPER a a 20.0 fordifferent Trang /kT Eq. 2 300 1.4 2.0 and that the andthatthe a . Figure 4 is such such is 4 Figure . ISO 13485: ISO 9001 ISO 13485: ISO 9001 : : 2015 Certified 2015 Certified 2016 Certified 2016 Certified 37.0 500 1.2 3.6 | 21 |

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- 4 20 R&D CONSULTANT FORELECTRONICS TECHNOLOGY DR. RANDALL K. KIRSCHMAN packaging andassembly for high-temperature operation. electronics to relation in testing, accelerated and reliability on observations basic few a is presents temperature Part as concluding raised.This materials packaging and assembly of erties TOPLINE CORPORATION MARTIN HART the balanceofpeacein World Order. nents could ultimately diminish market readiness, possibly tipping lions of dollars. A production stoppage of critical FPGA compo strike, potentially costing the defense industry hundreds of mil of hundreds industry defense the strike,costing potentially 28 next generation networks,generation communications. next and computers power systems;photonics;MEMS;and hw/sw electronics; packaging;cybersecure 2.5D/3D electronics; healthcare/medical in “Flashes.”UniversitycurrentlyBinghamton researchhas thrusts BINGHAMPTON UNIVERSITY BENSON CHAN

ALT CIN – TOACTION CALL mitigate the risk of waiting for an unexpected disaster to disaster unexpected an for waiting of risk the mitigate

PACKAGING – the challenges presented by variations of the basic propbasic the presentedof challenges variations bythe otis rils rm h Bnhmo Uiest S3IP University Binghamton the from articles contains TECH BRIEFS – TECH Coupling &Crosstalk 11 6 Member News Parts Parts II, III and IV of this series explored The State-of-the-Art State-of-the-Art The TechnologyBriefs - - - W This event together to willbring experts cover topics suchas: functional view ofthechallenges ofproducing KGD. problems inanother. What ismissingaforum thatwilltake ahigherlevel andcross- cross more thanonefunctionalarea. Orworse changesinonearea may exacerbate However, theseefforts inisolationmay notbesufficient especially sinceissuesmay coverage thathistorically was thecase. automation (EDA) designfor test tools (DFT) are generating much higherlevels oftest progress since the first KGD conference inNapa in 1994. For example, electronic design It isclearthatthevariousto functionalareas have thatnecessary KGDhave made flex (CoF), andchiponglass(CoG). tion bare dieusedinmodules andonflex-circuits suchaschiponboard (CoB), chipon (SiP), Heterogeneous Integration (HI),andPanel Level Processing (PLP). Notto men- ing 2.5/3Ddiestacking, Fan-out Wafer Level Packaging (FOWLP), System inPackage (KGD) isessentialfor many, ifnotall,ofthecurrent ‘crop’ ofadvanced packaging includ- SEMI GlobalHeadquarters,Milpitas,California Tuesday, April21,2020 KNOWN GOODDIEWORKSHOP

puet netet oa can today investment prudent A      24 Figure 1.SingleEnvironment forCross-Substrate ConnectivityPlanningandOptimization. bring devices of disparate technologies bring devicesofdisparatetechnologies an overallsmallerform-factor. performance requirementswhileproviding poser providestheneededdensityand interposer isagoodexample. The inter high-bandwidth memory(HBM)onan with SoC/ASIC a integrating of trend bandwidth andperformance. The current the samepackagetosupportneeded devices areco-locatedwithmemoryin SoC/ASIC Increasingly devices. these less heatischangingthatparadigmfor the needtouselesspowerandgenerate signal speedsanddataratescoupledwith on aprintedcircuitboard(PCB). Today’s by mountingandconnectingthesedevices devices historically has beenfacilitated MEMORYSOC/ASIC FOR ACCESS Mentor Kevin Rinebold,Technology Manager–AdvancedPackagingSolutions Advanced Packages Test Considerations for2.5/3DHeterogeneous Post-Layout Verification, Analysisand

EDA andCAD Tools Business Model Big Data and Analytics Test andHandling Metrology andInspection This approach can also be applied to This approachcanalsobeappliedto | MEPTEC REPORT For questionsaboutevent attendance, sponsorships, orexhibiting, [email protected]. has fueledthedevelopment ofadvanced packaging. Having Known GoodDie tor process nodes, thedemandfor greater costperformance anddifferentiation ith thedemiseofMoore’s Law dueto theeconomicsofadvanced semiconduc- FOR MOREINFORMATION ANDTOREGISTERONLINETODAY GOTOKGDWORKSHOP.ORG PACKAGING ® , ASiemensBusiness WINTER 2019 Limited Sponsorships&Exhibit Tables are Available KNOWN GOODDIE - WORKSHOP 20 same time, expanded EDA tool support EDAsupport expanded tool time, same verification. the testability At and stress more in-depth,system-levelelectrical, as well as verification, physical level required—one thataccountsforassembly- is flow verification comprehensive a that tiple datasourcesandformatsitisclear and testthesepackage.Giventhemul- strates, andservicestodesign,assemble, diverse eco-systemtosupplythedie,sub- methodologies. challenges totraditionaldesigntoolsand are moresilicon-likethuscreatingunique materials, andprocessesthatincreasingly ages utilizemanufacturingtechniques, integration. These heterogeneouspack- strate, otherwiseknownasheterogeneous and processestogetherontoasinglesub- Heterogeneous packaging relies on a Heterogeneous packagingreliesona KGD Powers More thanMoore! 2020 port MEPTEC entire heterogeneouspackageassembly. around a3Ddigitalmodel,ortwin,ofthe for electrical,stress,andtestanalysisbuilt process integrated single a provide flows performance expectations.Ideallythese ers canmeettheirmarketschedulesand design- package ensure that flows mated is requiredtoensurefast,accurate,auto- chip-package interactions(CPI)neces- imity oftheseelementsgreatlyenhances between dieandsubstratethecloseprox- performance. With decreasingdelineation needed solutionforsystemscalingand and multiplesubstratestodeliverthe typically incorporatemultipledevices Verification Heterogeneous AssemblyLevel 2.5/3D Heterogeneous packages 2.5/3D Heterogeneouspackages Volume 23, Number4 PRESENTS Volume 23, Number4 13

meptec.org

Industry Insights Industry for theseassemblies how parasiticextractioncouldbeachieved dles. There hasevenbeendiscussionof inputs (data,formats,etc.),andlikelyhur have beenexplored,includingtherequired LVSassembly-level an process for tices (LVS) prac- schematic Best verification. the needforassembly-levellayoutvs. meptec.org construction requiresabilitytoaggregate of multipledevicesandsubstrates.Model resentation ofthefullsystemcomprised provides designersacomprehensiverep- of the2.5D/3Dheterogeneousassembly Digital Twin duced discussed, andautomatedsolutionsintro- neous assemblieshasbeenextensively endless cycleofiterations. balance andoptimalsolutioncanbean right the Finding testing. and formance, routability, electricalandthermalper ing andco-designtoevaluatesubstrate and departments,usingrapidprototyp- while collaboratingacrossgeographies tiple substratesinoneenvironment,often mul- manage to ways find must Designers substrates, orimpacttheentiresystem. strate canhavearippleeffect onadjacent or powerdelivery, adecisionononesub- critical elementslikehigh-speedinterfaces flow. co-design unified a With sitating nicate decisionstostakeholders. and designscenarios,clearlycommu- trade-offs evaluate and perform efficiently eliminate potentialdownstreamissues, ment, designerscanbetteranticipateand interposer, package,PCB)inoneenviron- ability toseethecompletepicture(die, databases) inoneenvironment. With the and managemultiplesubstrates(design tion, designersmustbeabletocoordinate flow.automated and able, repeat- efficient, an in processes these of ment thatenablesdesignerstomanageall addressed istheneedforasingleenviron- erogeneous assembly. What hasnotbeen and successfulmanufacturingofthehet- functionality correct guarantee to ficient LVSassembly-level suf- and are etc.), to-package alignment,scaling,orientation, (LVL)layout (die- vs. verification layout if packagedesignrulechecking(DRC), system-level designersalsoneedtoknow October, 23,2019 SEMICONDUCTOR ENGINEERING, Reprinted withpermissionfrom new GaN and SiC devices are making a new GaNandSiCdevicesaremakinga various challenges. devices areexpensivetechnologieswith Développement. Generally, GaNandSiC power semimarket,accordingto Yole than 90%marketshareintheoverall Today, silicon-baseddeviceshavemore displace theirsiliconrivalsanytimesoon. relatively lowadoptionratesandwon’t based devices. silicon- than efficient more and faster are wide-bandgap technologies,meaningthey various segments.BothGaNandSiCare compete againstIGBTs andMOSFETs in the marketforyears,GaNandSiCdevices respects. reaching theirtheoreticallimitsinseveral mature andinexpensive,buttheyarealso (IGBTs). are transistors Both bipolar gate namely powerMOSFETs andinsulated- been dominatedbysilicon-baseddevices, minimize theenergy lossesinsystems. and efficiencies the boost They state. “off” the in it stop and state “on” the in flow to trains. The devicesallowtheelectricity as automotive,powersupplies,solarand switch inhigh-voltageapplicationssuch a as operate semis Power silicon. and SiC and competitivetechnologieslikeGaN, ized transistorsthatincorporatedifferent based devicesinthemarket. a showdownagainsttraditionalsilicon- for stage the setting (SiC), carbide silicon and (GaN) nitride gallium on based tors out thenextwaveofpowersemiconduc ROLLING VENDORS ARE SEVERAL meptec.org SEMICONDUCTOR ENGINEERING Mark LaPedus,ExecutiveEditorforManufacturing much more attractiveaspricesdrop They won’t replace silicon,butGaNandSiCare becoming Power SemiWars Begin MARKET TRENDS Building a digital twin (virtual model) Building adigitaltwin(virtualmodel) heteroge- of verification Physical In heterogeneous design and verifica- and design heterogeneous In mature, flows and methodologies As That’s beginningtochangebecause Still, GaNandSiCdeviceshave In in. fit SiC and That’sGaN where For years,thepowersemimarkethas special are semiconductors Power [1][2] . There havebeenanalysesof [3][4] . - - -

- analysis. Tools likeMentor’s Xpedition and verification drive to suitable sentation ent formatsintoacohesivesystemrepre- data fromdifferent sourcesandindiffer verification. heterogeneous automated for flows signoff qualified proven, providing to approach unified a of beginning the to led has tion EDAautoma- and tool standardization try finally,and test. analysis, extraction (PEX),stressandthermal LVS,into expanding LVL, parasitic beginning withsubstratelevelDRC assemblies heterogeneous of verification strate). embedded bridges,andpackagesub- of thedesignhierarchy(die,interposers, level every of verification electrical and golden referenceforcompletephysical Verilog format. This netlistservesasthe replaced byafullsystemlevelnetlistin represent pinandconnectivityinformation need tousemultiplestaticspreadsheets and analysisoperations. This eliminates verification drive to reference golden the digital twinapproachisthatitservesas pseudo components. interfaces withouthavingtoinstantiate automatically recognizesdevice/substrate that exist also should Functionality files. LEF/DEF,like AIF,CSV/TXT or GDS, is doneusingindustrystandardformats the heterogeneousassembly. Ideallythis age themultipledatabasescomprising man- and import can Integrator Substrate Figure 2.2.5D/3DDigitalTwin (VirtualModel)ofHeterogeneous Assembly. • them: events takingplaceinthismarket. Among foreseeable future,”Linsaid. can stillhavetheirplace,atleastforthe ket isgrowingveryquickly. Everydevice place foralltechnologies.“Thetotalmar a is There needs. all fits that semi power grow veryfast,”Linsaid. con carbideandIGBTs. The marketcould GaN couldbereallymuchbiggerthansili years, five in rate growth the calculate we the comingyears.” expect thecompetitiontobeverystrongin huge andisattractingalotofplayers. We analyst at Yole. “Themarketpotentialis automotive market,”saidHongLin,an to growveryfast,drivenmainlybythe carbide powerdevicemarketisexpected devices, accordingto Yole. “Thesilicon compared tosingledigitsforsilicon-based ple, isgrowingatadouble-digitpace, bigger dentinthemarket.SiC,forexam categorized. Figure 1.Howpowerswitchesare

Combining thedigitaltwinwithindus- The digitaltwinenablesautomated the of benefits primary the of One new SiCfabs. Vendors arepreparing their capitalspendingandbuilding Cree, Rohmandothersareincreasing Nonetheless, thereareanumberof As itturnsout,though,thereisnoone GaN isatinymarkettoday. “When Source:Infineon

™ - - - -

to verify connectivity.verify to automated An pared againstthegoldenschematicnetlist produce thephysicalnetlistwhichiscom- derived fromphysicallayoutdatato the connectedshapesandpinlocations Connectivity Checking(LVS) (digital twin)data,Mentor’s Calibre and perplacement.Usingvirtualmodel how todifferentiate thelayeringperdie understand EDAmust The tool checks. tion factors,andpadcentersoroverlap between substrates,scalingorcompensa- also includesLVL checksforalignment within eachdietoseetheseimpacts.It may requireextractingseverallayers die (spacing,featuressizes,etc.)which which checkstheinteractionsbetween results. verification of veracity the ensure to environments verification and design cal tomaintainindependencebetweenthe to theirtarget foundryrules.It‘salsocriti- individual diehasalreadybeenchecked each premise the on based simplified significantly is verification erogeneous Het- verification. assembly package same whenautomatingheterogeneous the is goal The processes. verification designers toperformawidevarietyof tools withinasingleframeworktoenable EDAspecialized multiple of use the been Physical Verification meets all physical requirements. meets allphysicalrequirements. DRC/LVL checksensuringthedesign rect assemblyrepresentationtoperform cor 3DSTACKthe extracts automatically by a numerical figure with a “V” or volt or “V” a with figure numerical a by other chips.Eachpowersemiisdenoted and semis power as such devices, efficient power plants,accordingtoNCState. sold in1yearisequivalentto17500MW PCs desktop in wasted power the example, the conversionprocessinsystems.Inone bines. drives, powersupplies,solarandwindtur power insystems,suchascars,motor devices thatcontrolandconvertelectric system, accordingtotheschool. is transportedthroughapowerelectronic More than80%oftheworld’s electricity ing toNorthCarolinaStateUniversity. kilowatts ofpowereveryhour, accord The EndofSilicon? to the firm. the to less thana$10millionbusiness,according Yole. In2018,theGaNdevicemarketwas 2018 to$564millionin2019,according market willgrowfrom$420millionin according to Yole. Ofthat,theSiCdevice 2018 tomorethan$21billionby2024, expected togrowfrom$17.5billionin • • • WINTER 2019

WINTER 2019

LVS checking in an IC looks at at looks IC LVSan in checking Verification DRC, of comprised is has verification IC of hallmark One Therefore, the industry requires more Therefore, theindustryrequiresmore Generally, poweriswastedduring various of use make electronics Power In total,theworldgenerates12billion In total, the power device market is In total,thepowerdevicemarketis fabs. uptick indemandcompoundsemi Equipment vendorsareseeingan is makinginroadsinvarioussystems. against powerMOSFETs. GaN ing whatitcallsa“frontalassault” supplier ofGaNpowersemis,ismak- a (EPC), Conversion Power Efficient meet demand. ply dealswithSiCdevicemakersto Automotive OEMsaresecuringsup- car market. for hugedemandinthebattery-electric MEPTEC REPORT MEPTEC REPORT ™

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- - - - WINTER 2019 CALL TO ACTION

Does the FPGA Industry Face Peril? Pt. II

Martin Hart TopLine Corporation

PREVIOUSLY, PART I OF THE FALL 2019 MEPTEC REPORT “Call to Action” addressed a concern that the main producers of Field Programmable Gate Arrays (FPGA) rely on a single source subcon- tractor to attach copper wrapped solder columns as their final production step. The Defense Logistics Agency (DLA) publishes a list of supply chain subcontractors authorized to assemble FPGA devices in the Qualified Manufacturer List (QML-38535). Stakeholders have reason to be alarmed. A production stoppage of critical FPGA devices could result in the failure of the Producers of FPGA devices with solder columns (in Alphabetical order). defense industry to fulfill commitments for delivery of warfighters. Radiation vertically in place by precision machined column attachment services as long as fund- Hardened FPGA packages are constructed fixtures without slanting or falling over ing is available to pay for the cost of QML to withstand intense radiation and high at any time during the entire attachment qualification. A sizable investment would temperatures in order to satisfy mission and reflow process. A final assembly step be required to support an accelerated initia- requirements. requires that the entire matrix array of up to tive by FPGA makers to mitigate risk and 1752 columns be planarized without dam- qualify multiple subcontractors to attach Supply Chain Resiliency aging a single column. No manufacturing copper wrapped solder columns. FPGA Several risk archetypes for achieving defects are allowed. Talented operator skills makers need to take the lead in initiating the a robust and resilient production of FPGA must be employed during every step in qualification of alternative subcontractors. devices include a diminishing domestic the process of attaching columns to FPGA As a practical matter subcontractors cannot manufacturing base and a fragile market packages. Attaching copper wrapped solder independently apply for QML status with- as described in the Department of Defense columns to FPGA packages is fundamen- out the support of the FPGA maker. (Presidential Executive Order 13806) tally a non-automated, artisan process. Industrial Policy report titled, “Assessing Fortunately, royalty-free, U.S. manufac- Conclusion and Strengthening the Manufacturing and tured copper wrapped solder columns are It’s time for advocacy stakeholders to Defense Industrial Base and Supply Chain readily available today in the supply chain initiate a shared vision to ensure a robust, Resiliency of the United States”. FPGA without delay. However, starting from resilient and sustainable supply chain for packages with solder columns are produced scratch, it could take 24 months for alterna- FPGA devices. Domestic manufacturing of in a low-volume manufacturing environ- tive subcontractors to undergo the arduous copper wrapped solder columns is already ment; as such, around 75,000 individual process of attaining QML status for column available. The next step is to qualify FPGA devices spread over 100 different attachment services. multiple microelectronic subcontractors outline packages are produced annually. who are ready and willing to provide the Total annual volumes of 70 million cop- Monetary Considerations critical process of copper wrapped column per wrapped solder columns are minuscule Companies that produce FPGA devices attachment services for FPGA packages. A when compared to volumes of Commercial are not required to voluntarily qualify prudent investment today can mitigate the Off-The-Shelf (COTS) FPGA devices con- multiple subcontractors to attach copper- risk of waiting for an unexpected disaster suming billions of solder balls. wrapped solder columns to their products. to strike, potentially costing the defense Attaching solder columns to FPGA A lack of funding by FPGA manufacturing industry hundreds of millions of dollars. A packages is substantially different from is most often cited as the primary reason production stoppage of critical FPGA com- attaching solder balls that dominate the for not qualifying a second source. Multiple ponents could ultimately diminish market COTS market. Solder columns are cylin- microelectronic subcontractors in the supply readiness, possibly tipping the balance of drically shaped pins that must be held chain are ready, willing and able to provide peace in the World Order. ◆

4 | MEPTEC REPORT WINTER 2019 meptec.org UP FRONT

Warming Up to 2020

Ira Feldman Executive Director, MEPTEC

WELCOME! FROM LONG TIME friends, there was a great lunch includ- law, Nvidia VP Product Engineering. MEPTEC members to recent subscribers ing holiday treats. Not to mention Jan Please see the event information on page to casual visitors, we are glad you are Vardaman’s (TechSearch International), 14 and http://www.kgdworkshop.org/ for here. now traditional yearly Industry Outlook more information. The cold of winter has started in North on “Advanced Packaging for 2020 and The Advisory Board (AB) has been America. It’s true that here in Silicon Beyond”. Jan always brings a fresh per- busy planning our event calendar for Valley we are blessed with moderate tem- spective to things and was not shy about 2020. We will be announcing the other peratures. However, the chill is in the air sharing her thoughts! There will be plenty full day events and luncheons shortly. hopefully accompanied by much needed of other great luncheon presentations dur- I look forward to hearing your sugges- rain. Some find this time of year dreary, ing 2020 so stay tuned as we announce tions and feedback as to how MEPTEC but I enjoy the warmth of the holidays them. can best serve you. Don’t be shy! spent with family and friends. Our next full day event is the Known We had a very well attended annual Good Die (KGD) Workshop on Tuesday Happy holidays to you and yours! MEPTEC holiday gathering. Okay truth April 21, 2020 in Silicon Valley. We are be told it was the December Semiconduc- excited to celebrate KGD’s 20th year as Ira Feldman tor Industry Speaker Series luncheon. this critical topic is revisited! Don’t miss Executive Director, MEPTEC Beyond wishing everyone ‘happy the keynote “Making KGD Silicon Work [email protected] holidays’ and catching up with industry in Your Supply Chain” by David Green- +1 650-472-1192

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 HENKEL APPOINTS Improved Productivity and Reliability for NEW CFO Thin Memory Chips Effective January 1, 2020, Marco Swoboda, Corpo- Development of DDS2320, Die Separator with Dual Processing Stage rate Senior Vice President Finance, will become new DISCO CORPORATION), A Chief Financial Officer of semiconductor manufactur- Henkel. He will succeed ing equipment manufacturer, Carsten Knobel who will take has developed DDS2320, a over the position as CEO fully automatic die separator effective January 1, 2020. capable of processing 300 “We are pleased to name mm wafers that contributes to Marco Swoboda as a highly improved throughput and reli- qualified successor to our ability in memory production. Chief Financial Officer from This equipment was exhibited within our organization. He at SEMICON Japan 2019. has strong financial exper- Memory demand is ex- tise with many years of pected to increase with the international experience,” development of IoT, AI, and said Dr. Simone Bagel-Trah, ADT. As a result, productivity Chairwoman of the Share- improvement in memory chip holders’ Committee and the manufacturing and improve- Supervisory Board. ment of post-processing device www.henkel.com reliability will be required more than in the past. shrinking in one unit • Reverse-side spinner  MITSUNOBU While DISCO had previ- • Parallel processing with cleaning/transfer KOSHIBA OF JSR TO ously introduced the die sepa- dual expansion unit RECEIVE SEMI SALES rator DDS2300 to the market, Approximately 40% AND MARKETING DD2320 has been newly Improved Device Reliability FootPrint Reduction EXCELLENCE AWARD developed to meet these emer- Post-Processing In previous models, auxil- SEMI has announced that gent needs. Particle adhesion is iary equipment was installed Mitsunobu (Nobu) Koshiba reduced by performing pro- in the area around the main of JSR Corporation has Improved Productivity cessing and transfer after equipment. DDS2320 won the SEMI Sales and Efficient production of reversing the workpiece, lead- achieves a smaller footprint Marketing Excellence Award, thin die is now possible due ing to improved device reli- by having the auxiliary equip- inspired by Bob Graham, to the adoption of a newly ability and yield. ment installed internally. for 2019. The 22nd recipi- developed expansion unit. • Reverse-side cool expan- For more information, ent of the award, Koshiba • Cool expansion and heat sion / heat shrinking visit www.discousa.com. ◆ was honored for his role in developing and bringing to market multiple photoresist SEMI and VLSI Research Unveil End-to-End generations that have been critical to the semiconductor Semiconductor Manufacturing Industry Report industry. He will be recog- SEMI AND VLSI RESEARCH HAVE expertise delivers an unparalleled breadth of nized during ceremonies unveiled the Semiconductor Manufacturing market research spanning the entire semicon- at SEMICON Japan 2019, Monitor, a report covering the semiconductor ductor manufacturing supply chain.” December 11-13, in Tokyo. manufacturing industry from materials to elec- Published four times each year, the annual www.semi.org tronic systems. The inaugural report includes subscription provides information on: comprehensive 2018 and 2019 quarterly data for • Electronic systems sales  ANALOG APPOINTS the semiconductor manufacturing supply chain, • IC sales by logic and memory DR. SUSIE WEE TO a one-quarter outlook, and semiconductor equip- • Semiconductor manufacturing CapEx BOARD OF DIRECTORS ment forecast scenarios to 2020. • Foundry, fabless, OSAT and semiconductor Analog Devices, Inc. has “The Semiconductor Manufacturing Monitor equipment company revenues announced the appoint- sets a new standard for semiconductor manu- • Silicon shipments ment of Dr. Susie Wee to facturing by offering critical insights for making • Global wafer fab capacity the Board of Directors as an strategic business decisions and investments in • IC inventory independent director, effec- our highly dynamic industry,” said Ajit Mano- This Semiconductor Manufacturing Monitor tive November 29, 2019. cha, SEMI president and CEO. “The combina- is ideal for companies requiring cost-effective,  tion of SEMI’s leading benchmark data and comprehensive industry data from trusted sourc- VLSI Research’s semiconductor manufacturing es. Visit www.semi.org to learn more. ◆

6 | MEPTEC REPORT WINTER 2019 meptec.org nepes Corporation to Acquire Deca Technologies Manufacturing Operations

DECA TECHNOLOGIES IS Patterning combined with pleased to announce that it has nepes strong experience in reached an agreement with fan-out and large panel manu- nepes Corporation whereby facturing creates a powerful nepes will expand its geo- combination for future growth. graphic footprint and manu- Multiple industry research facturing capabilities by firms have identified M-Series taking over the operations of designed into several Tier One Deca Technologies Philip- handsets in support of a leader pines manufacturing facility. in PMIC applications, further SPECTRUM IS YOUR The investment will permit announcements are expected the expansion of the WLCSP to follow as more customers capacity already in mass adopt the technology. Integra- HI-REL IC PACKAGE production and now offer up tion of nepes’ large panel and to 100,000 wafers per month SIP capabilities with M-Series with a dual site capability and Adaptive Patterning will AND LID SOLUTION courtesy of the Korea site in create multiple exciting cus- addition to the Philippines tomer module solution pos- FOR MIL-AERO, AUTOMOTIVE, COMMUNICATIONS, facility. sibilities including advanced As part of the agreement, heterogeneous integration. MEDICAL, WIRELESS AND AVIONICS APPLICATIONS nepes has licensed Deca’s nepes has manufacturing M-Series technology to fur- sites in South Korea and Spectrum offers: ther enable the rapid industry China and international sales • Highly knowledgeable sales staff with decades adoption of advanced fan-out offices in San Diego, CA and of Industry Experience technology. Deca’s revolution- Shanghai, China. Visit www. • Highest quality ROHS, REACH, Non-Conflict Minerals ary M-Series with Adaptive nepes.co.kr for more. ◆ and Counterfeit Prevention compliant materials • ISO-9001:2015 and AS9120B QMS Certified • Qualified Source for: Mil-Aero, Automotive, NXP Increases Performance and Communications, Medical, Wireless, Avionics Expands LPC5500 Arm® Cortex®-M33 • World Wide Same Day Shipping • Guaranteed On-Time Delivery Microcontroller Series • Small Business, Veteran Owned leveraging 40-nm NVM • Competitive pricing process technology to deliver a cost- and power-efficient microcontroller platform. The LPC552x/S2x is a mainstream family in LPC5500 series, providing a perfect balance between security, NXP SEMICONDUCTORS performance efficiency and has announced the avail- system integration for gen- ability of its LPC552x/S2x eral embedded and industrial Located in Silicon Valley for the past 30 years, Spectrum Semiconductor Materials, Microcontroller (MCU) IoT markets. It combines the Inc. is a World Wide Authorized Distributor of packages and lids for IC assembly. family – further extending high-performance efficiency Our proven track record, consistent customer service and long-standing supplier its performance efficient of the Cortex-M33 core with relationships makes us the premier distributor for your IC Packaging needs. LPC5500 MCU series with multiple high-speed inter- Visit www.spectrum-semi.com to see what we can do for you! the second of seven families faces, an integrated power planned for the series. The management IC, and rich LPC552x/S2x MCU family analog integration. offers significant advantages Key features include: for developers, including To learn more about the pin-, software- and peripher- LPC552x/S2x MCU fam- al-compatibility to acceler- ily, visit: www.nxp.com/ ate time to market, while LPC552x. ◆ 155 Nicholson Ln. San Jose, CA 95134 (408) 435-5555 Email: [email protected] meptec.org  MEMBER NEWS

Dr. Wee is the Senior Vice With Sub Micron Accuracy from Lab to Fab President and General Man- ager of DevNet and CX Eco- FINETECH’S HIGH-PRE- system Success at Cisco CISION placement and Systems and will serve on assembly systems support the Board’s Compensation customers from the photonics Committee. and optoelectronics indus- “We are pleased to welcome try in cost-efficient product Susie to the ADI Board. development and transfer to Her extensive experience in automated manufacturing. information technology and With the newly introduced application development, FINEPLACER® lambda 2 together with her established and the high-yield production track record of driving soft- platform FINEPLACER® ware innovation at global femto 2, the Berlin-based pre- as well as diverse and very transceivers (TOSA/ROSA) technology companies, will cision machine manufacturer demanding bonding technolo- or laser diode modules. be of great value to ADI and offers integrated equipment gies. Applications include the Thanks to the proven our customers,” said Ray and process solutions for all development and production FINEPLACER® alignment Stata, ADI Chairman of the product stages from a single of optical transceivers up to and placement principle with Board. source. 400 G for data communica- only one moving axis, the www.analog.com As a manufacturer of tion, environmental sensors system combines highest micro assembly equipment for autonomous driving, or process quality, stability and  NORDSON MOVES and process technology, power laser modules for use accuracy. In conjunction with TO NEW OFFICE AND Finetech has been support- in industrial and medical specially developed optical DEMONSTRATION ing start-ups, as well as applications. systems with an optical reso- CENTER IN TOKYO global technology leaders, for The FINEPLACER® lutions down to 0.7 µm, it Nordson Corporation almost three decades in the lambda 2 is used to place enables superimposed images announces that Nordson development of innovative and connect components of the highest optical quality Advanced Technology K.K. semiconductor products. with an accuracy of better for the reliable detection and Japan has relocated to new, They are the first choice than 0.5 microns - ideal for alignment of finest structures larger office and demonstra- for complex multi-stage the high requirements, e.g. in the micron range. tion facilities in central Tokyo assemblies with extremely in the development of opto- For more information, to deliver superior sales, high accuracy requirements, electronic products such as visit www.finetechusa.com. ◆ service, technical training, and support to its customers and sales network in Japan. Mobileye and NIO Partner to Bring Level 4 Autonomous The Nordson Advanced Technology group sells Vehicles to Consumers in China and Beyond and supports the products from several Nordson divi- the system for Mobileye and also integrate the sions (Nordson ASYMTEK, technology into its electric vehicle lines for Nordson SELECT, Nordson consumer markets and for Mobileye’s driverless DAGE, Nordson MARCH, ride-hailing services. NIO’s variants will target Nordson MATRIX, Nordson initial release in China, with plans to subsequent- SONOSCAN, and Nordson ly expand into other global markets. YESTECH) under a unified, Under the planned collaboration, Mobileye in-country team. With the will provide NIO with the design of the self-driv- expanded facility, Nordson ing system building on the Mobileye AV Series, ® Advanced Technology K.K. MOBILEYE, AN INTEL COMPANY, AND a L4 AV kit comprised of the Mobileye EyeQ consolidated its fluid dis- NIO, a pioneer in China’s premium electric vehi- system-on-chip, hardware, driving policy, safety pensing and conformal coat- cle market, are engaging in a strategic collabora- software and mapping solution. NIO will take ing, test and inspection, and tion on the development of highly automated and on the automotive-grade engineering, integra- plasma treatment equipment autonomous vehicles (AV) for consumer markets tion and mass-production of Mobileye’s system into one location. The move in China and other major territories. As part of for both consumer automotive markets and for was completed in the sum- the planned cooperation, NIO will engineer and Mobileye’s mobility-as-a-service (MaaS) applica- mer and an opening event manufacture a self-driving system designed by tions. In addition to integrating the self-driving was held in October 2019. Mobileye, building on its Level 4 (L4) AV kit. system into its vehicle lines, NIO will develop a www.sonoscan.com This self-driving system would be the first of its specially configured variant of electric AVs that kind, targeting consumer autonomy and engi- Mobileye will use as robotaxis, deployed for  neered for automotive qualification standards, ride-hailing services in global markets. quality, cost and scale. NIO will mass-produce Visit www.intel.com for more info. ◆

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 BERND HOPS TO Henkel Celebrates Groundbreaking of HEAD CORPORATE New Plant in Korea COMMUNICATIONS AT INFINEON New High-tech Facility as Global Hub for the Electronics Business Infineon Technologies AG has announced that effective January 2020 Bernd Hops, currently Head of External Communications, will take over as Head of Communi- cations and Public Authori- ties & Associations at Infine- on Technologies AG. He will succeed Klaus Walther, who held this position from 2013. In this capacity, Mr. Hops will report to Chief Executive Officer Dr. Reinhard Ploss and have global responsibility for internal, external and political communication. www.infineon.com

 INTEL ACQUIRES HENKEL HAS HELD THE Technologies. tion, the production facilities groundbreaking ceremony for The Songdo Plant will have will fulfill high sustainability ARTIFICIAL INTELLI- 2 GENCE CHIPMAKER a new production facility in a gross area of 10,144m in standards and be equipped with HABANA LABS the high-tech industrial cluster a two-story building and will the state-of-the-art technologies Intel Corporation has in Songdo, Korea. With an commence full production in such as solar energy panels, announced that it has investment of more than 30 Q1 of 2022. The new facility high-efficiency equipment for acquired Habana Labs, an million euros, the new plant will be designed as a high-tech energy conservation and secur- Israel-based developer of will become a global produc- smart factory including a coming of green land. tion hub for the electronics prehensive building manage- For more information, visit programmable deep learn- ◆ ing accelerators for the data business of Henkel Adhesive ment system (BMS). In addi- www.henkel.com. center for approximately $2 billion. The combination strengthens Intel’s artificial Intel Research Identifies Digital Skills Gap intelligence (AI) portfolio and accelerates its efforts in the Slowing Industry 4.0 nascent, fast-growing AI INTEL HAS RELEASED THE RESULTS OF cited by respondents that have the potential silicon market, which Intel a new study, “Accelerate Industrial,” that repre- to derail investments in smart solutions in the expects to be greater than sents the most comprehensive view of Industry future: $25 billion by 2024. Intel’s 4.0, the digital transformation of the manufac- • 36% cite “technical skill gaps” that prevent AI strategy is grounded in turing sector. The research uncovered a serious them from benefiting from their investment. the belief that harnessing skills gap that most Western industrial produc- • 27% cite “data sensitivity” from increasing the power of AI to improve tion training programs and government invest- concerns over data and IP privacy, ownership business outcomes requires ment initiatives fail to address. and management. a broad mix of technology The study found that today’s leaders need to • 23% say they lack interoperability between – hardware and software – create tomorrow’s future-ready workforce. This protocols, components, products and systems. and full ecosystem support. requires the collaboration of universities, gov- • 22% cite security threats, both in terms of Today, Intel AI solutions are ernment and industry – including initiatives that current and emerging vulnerabilities in the fac- helping customers turn data focus on worker training for the transforming tory. into business value and manufacturing sector. • 18% reference handling data growth in driving meaningful revenue A recent Deloitte/Manufacturing Institute amount and velocity, as well as sense-making. for the company. In 2019, study suggests that industries are entering a “Accelerate Industrial” was conducted and Intel expects to generate period of acute long-term labor shortages, with authored by Dr. Faith McCreary, a principal over $3.5 billion in AI-driven a shortfall in manufacturing expected to be 2.4 engineer, experience architect and researcher at revenue, up more than 20 million job openings unfilled by 2028, resulting Intel, in tandem with Dr. Irene Petrick, senior percent year-over-year. in a $2.5 trillion negative impact on the U.S. director of Industrial Innovation for Intel’s ◆ www.intel.com economy. Industrial Solutions Division. For more informa- The study uncovered the top five challenges tion visit www.intel.com. ◆

10 | MEPTEC REPORT WINTER 2019 meptec.org COLUMN

space flight, combine the need for first before the patterns are written on the COUPLING & time success without any failures due to masks is “physical verification”. At this the lives at stake and enormous cost. stage the mask patterns are checked CROSSTALK My son does not fully comprehend against design rules (minimum feature By Ira Feldman why I insist on checking his math home- size, minimum clearances, etc.), electri- work with him before he is ‘done’. Like cal checks are performed, and layout most high school students, he thinks he versus schematic (LVS) is run. LVS cal- Electronic coupling is the transfer of ener- is done after he quickly writes out the culates the schematic of the patterns – as gy from one circuit or medium to another. answers in his notebook but before we generated – and compares them against Sometimes it is intentional and sometimes go through to check… He hasn’t grasped the input schematics. This makes sure not (crosstalk). I hope that this column, by the value in reinforcing his mastery of the EDA tools did not create an error by mixing technology and general observa- the material as he attempts to explain his adding extra circuitry, neglecting part of tions, is thought-provoking and “couples” steps (especially those he failed to write the circuitry, or misinterpreting the cir- with your thinking. Most of the time I will out) nor finding simple calculation errors cuitry. Yes, we trust the tools to operate stick to technology but occasional cross- before turning in his homework. Ask- correctly but it is essential to verify the talk diversions may deliver a message ing him to detail out all the steps of his output to make sure there are no errors. closer to home. calculations is our family’s current “trust Each and every discrepancy needs to but verify”. be checked carefully to make sure there Trust Your Paranoia! are no systemic errors or fatal mistakes. Only after the design team is fully satis- PRESIDENT RONALD REAGAN’S “Trust, but verify” fied that everything is correct, does the use of the Russian proverb “Doveryai, mask data get sent off to generate the no proveryai” was the perfect soundbite appears to be a physical glass masks. to describe the 1987 Intermediate-Range At the moment the EDA data be- Nuclear Forces Treaty. What does this nonsensical phrase comes physical masks is where nature and Andy Grove’s “only the paranoid since verification intrudes and physical variations become survive” have to do with semiconduc- the difference between failure and suc- tors? implies a lack of cess. Just like a film negative, an error in “Trust, but verify” appears to be trust. However, it generating the mask or contamination on a nonsensical phrase since verifica- the mask will cause defects in every IC tion implies a lack of trust. However, it accurately describes patterned. Needless to say, mask fabrica- accurately describes how models of trust tors very carefully measure and inspect work. The extensive process of verifica- how models of the masks to insure they match the sub- tion built into the treaty basically meant trust work. mitted data. there was no trust between the United In the actual IC fabrication process States and the former Soviet Union. But, itself there are systemic (process “bias”) as each side performed their commit- Semiconductor design using modern and random defects that will impact the ments in a verifiable manner the treaty electronic design automation (EDA) yield of the individual devices. Hence the worked. software has extensive process checks to need for extensive quality control includ- Most people trust something until it make sure the design is correct. As the ing “metrology” (measurement) and test- no longer works. We hop in our car trust- process nodes have shrunk to ever small- ing to separate the defective devices from ing that the brakes will stop the vehicle er sizes, not only has the non-recurring those presumed good. I’ve previously when needed. Did you take a moment engineering (NRE) costs increased, but discussed the need for Known Good Die to inspect the brake pads before driving the complexity of the physical process (KGD) and I hope you will join us as off? Of course not, unless you already also has increased, resulting in more MEPTEC discusses the need and ever suspected a problem. Did you tell a col- opportunities for design errors and fab- present challenges at the upcoming KGD league or friend a ‘secret’? Will you con- rication yield loss. Most modern inte- Workshop on April 21, 2020. tinue to share with them? Yes, until that grated circuits (ICs) are designed using a In addition to a method for finding trust is broken and something untoward high-level description (HDL), examples the good die, what is needed in terms of happens. Cases of “blind trust” rarely include VHDL and Verilog, which pro- trust? Beyond the random variations that end well… vides a ‘logical’ language (think software cause die to fail, how does one ensure A good engineer, by nature and prac- code) to describe the desired functional- there are no ‘bad actors’ in one’s supply tice, tends to be skeptical. Usually a proj- ity. The design in HDL can be simulated chain? Jeff Demmin (Booz Allen Hamil- ect needs to be successful the first time and analyzed to verify the desired opera- ton and MEPTEC Advisory Board mem- or the cost of failure will be too high. We tion. At some point the HDL is expressed ber), touched upon this in his MEPTEC- double-check, we cross-check, and some- as an electrical circuit schematic which is IMAPS Semiconductor Industry Speaker times triple-check our process assump- also checked and simulated. This circuit Series luncheon presentation on Septem- tions as well as the calculations and data. schematic is then translated into a physi- ber 11, 2019. The cost of correcting a small error on a cal layout, i.e. the patterns and shapes of Today’s distributed global supply semiconductor mask set can run into the the traces to be processed on the IC. chain typically has over a dozen entities millions of dollars. Some endeavors, like One of the last checks performed ‘touching’ an IC between fabrication and meptec.org WINTER 2019 MEPTEC REPORT | 11 COLUMN

assembly into an electronic sub-system. then be integrated with more common in the day-to-day activities. Most of these companies are located out- building blocks available from the com- Bottom line? For any important pro- side of the US. And there are increasing mercial market with less concern as to cess, even though you may trust that cases of counterfeit ICs being found due the level of trust. it is being done ‘correctly’, you must to the economic incentives. With the IC So, regardless of one’s level of establish an independent ‘audit’ or itself it is very difficult and costly to con- paranoia, processes (as always) need to checking process. Be paranoid and trust, firm that the actual circuits match those be established to ensure one’s supply but verify. And do not hesitate to ask for of the design and do not contain changes chain’s quality and security. And the ‘outside’ help!

or extraneous circuitry. Unfortunately, roots of the paranoia expressed by former For more of my thoughts, please see reverse engineering an IC is a destruc- CEO and Intel co-founder Andy Grove? my blog http://hightechbizdev.com. tive process. So, one can never say with His biggest concern was that of missing As always, I look forward to hearing 100% certainty that a specific IC being strategic inflection points (SIP) where the your comments directly. Please contact used has not been tampered with. fundamentals of the business or available me to discuss your thoughts or if I can be Combined with no longer having technology have shifted. If a company of any assistance. ◆ domestic companies that are ‘trusted’ did not see and respond to these SIP, they semiconductor foundries available to may be passed by competitors or left out build complete devices (especially at of a market entirely. Thus, his focus on IRA FELDMAN is the Principal advanced process nodes) this creates a manufacturing and quality (product and Consultant of Feldman Engineering challenge for defense related applica- process). Corp. which guides high technology tions. In addition to developing methods Mr. Grove realized that existing teams products and services from concept for detecting the counterfeiting of or have a very large bias towards the status tampering with packaged devices, the quo. He often used outsiders (other divi- to high volume manufacturing. He Defense Advanced Research Projects sions / business units, consultants, etc.) engages on a wide range of projects Agency (DARPA) is driving the develop- to review things from a fresh perspective. including technical marketing, prod- ment of Heterogenous Integration (HI) This is similar to having a separate team uct-generation processes, supply- based solutions. Their approach is to use do the design verification and physical chain management, and business HI ‘chiplets’ developed and fabricated in verification of a chip design. Like most development. secure and trusted facilities for the most audit processes, an outsider may find ([email protected]) ‘sensitive’ functions. These chiplets can details overlooked by the those involved

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would do anything in the world for you. opportunity to fire back. INDUSTRY They have provided a real service to For many years they have offered a the semiconductor assembly and test seg- real and valuable service to our industry INSIGHTS ment of our industry. The MEPTEC lun- and have always done it with integrity, By Ron Jones cheons are a great opportunity for mem- honesty and openness. bers of our segment to get together, talk Some things never change. shop, and just catch up on being friends. This article is not about me, but mere- Changes The MEPTEC symposiums are a great ly to establish my bona fides as somebody way to stay up on industry trends that are that understands the assembly, packaging I’M A SEMICONDUCTOR GUY, taking place in our market. and test arena and who has dealt with through and through. Always have been, Bette and Gary for many years. We are always will be. lucky to have them providing this service I started at Signetics R&D in Janu- Technology has certainly for us and I don’t think it would be out of ary 1967 and have been in the industry changed during my 53 line to say thank you next time you com- ever since. To put a finer point on it, I am municate with them. ◆ mostly an assembly/test semiconductor years in the industry. guy. If you scratch me, what will flow When I began, we were out is a mixture of die attach epoxy com- on one-inch wafers RON JONES is CEO of N-Able Group pound and under fill resin. International (NGi); a semiconductor My first assembly position was at and now twelve-inch focused consulting and recruiting com- Texas Instruments in 1970 as a die attach wafers are typical. pany. N-Able Group serves clients in the and wire bond engineer on TI’s first auto- Americas, Asia and Europe. NGi supports mated assembly line. A couple of years the semiconductor supply chain including later I was the first engineering manager One thing about the semiconductor fabless and IDM semiconductor device on the ABACUS automated assembly line industry is that there is always change. companies, wafer foundry and OSAT pro- building 14/16 plastic DIPs. I was also For Bette and Gary, they moved from Sili- viders, materials and equipment suppliers, the manager for the consolidated military con Valley to Medicine Park, OK, then to high-rel assembly/test operation in TI’s the Charleston, South Carolina area. software companies and investors. Email Sherman plant. Technology has certainly changed [email protected] for more info. I joined Amkor in 1985 and shortly during my 53 years in the industry. When after moved to live in Korea as Corpo- I began, we were on one-inch wafers rate VP of Worldwide Operations. I next and now twelve-inch wafers are typical. joined Indy Electronics/Olin Interconnect Then geometries are measured with a Technologies in Manteca as president. yardstick and they are now down in the When that facility was sold, I moved to deep submicron range. A typical device Thailand as CEO of Thai Microsystems. used to be seven masking levels and now When Thai Microsystems was sold, it’s not unusual to have devices with 50 I formed N-Able Group International in levels. For all these changes, the typical 1996 – half of our business has been in process steps are spin, expose, develop, consulting or recruiting for the semicon- etch, deposit/implant, oxidize… Rinse and ductor assembly test arena. repeat. I began my association with MEPTEC On the other hand, some things in 1990. That is when I first met Bette never change. Bette and Gary are the Cooper and later Gary Brown. We have same responsible, conscientious, ethical worked on a number of things together people they have been over the decades over the years: that I have known them. In my opinion, the MEPTEC Report is one of the most • I have attended many, many professionally done industry magazines MEPTEC meetings. I have run across, and Gary is one of the • I joined the advisory board in 1997 most talented graphic artists I know of. and transitioned off in 2010 when the Working with them is a combination board was scaled down. of collaboration and Saturday Night Live. Every e-mail contains a zinger of some • I began writing a column for the sort in both directions. You can say what- MEPTEC Report in 1998 and con- ever you want without fear that it will be tinue to do so today. taken the wrong way. They are both witty During those many years I’ve gotten and more than willing to fire salvos but at to know Bette and Gary very well. They the same time more than willing to take epitomize semiconductor assembly and incoming fire. When I see an incoming test as much as anybody I know. They are email from either of them, I know there’ll knowledgeable, honest and ethical and be something in it to laugh about and the meptec.org WINTER 2019 MEPTEC REPORT | 13 MEPTEC PRESENTS KNOWN GOOD DIE WORKSHOP 2020 KGD Powers More than Moore!

KNOWN GOOD DIE WORKSHOP 2020 Tuesday, April 21, 2020 SEMI Global Headquarters, Milpitas, California

ith the demise of Moore’s Law due to the economics of advanced semiconductor process nodes, the demand for greater cost performance and differentiation W has fueled the development of advanced packaging. Having Known Good Die (KGD) is essential for many, if not all, of the current ‘crop’ of advanced packaging including 2.5/3D die stacking, Fan-out Wafer Level Packaging (FOWLP), System in Package (SiP), Heterogeneous Integration (HI), and Panel Level Processing (PLP). Not to mention bare die used in modules and on flex-circuits such as chip on board (CoB), chip on flex (CoF), and chip on glass (CoG).

It is clear that the various functional areas that necessary to have KGD have made progress since the first KGD conference in Napa in 1994. For example, electronic design automation (EDA) design for test (DFT) tools are generating much higher levels of test coverage that historically was the case.

However, these efforts in isolation may not be sufficient especially since issues may cross more than one functional area. Or worse changes in one area may exacerbate problems in another. What is missing is a forum that will take a higher level and cross- functional view of the challenges of producing KGD.

This event will bring together experts to cover topics such as:

 Metrology and Inspection

 Test and Handling

 Big Data and Analytics

 Business Model

 EDA and CAD Tools

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Power Semi Wars Begin They won’t replace silicon, but GaN and SiC are becoming much more attractive as prices drop

Mark LaPedus, Executive Editor for Manufacturing SEMICONDUCTOR ENGINEERING

Reprinted with permission from for huge demand in the battery-electric SEMICONDUCTOR ENGINEERING, car market. October, 23, 2019 • Automotive OEMs are securing supply deals with SiC device makers to SEVERAL VENDORS ARE ROLLING meet demand. out the next wave of power semiconduc- • Efficient Power Conversion (EPC), a tors based on gallium nitride (GaN) and supplier of GaN power semis, is mak- silicon carbide (SiC), setting the stage for ing what it calls a “frontal assault” a showdown against traditional silicon- against power MOSFETs. GaN based devices in the market. is making inroads in various systems. Power semiconductors are special- • Equipment vendors are seeing an ized transistors that incorporate different uptick in demand in compound semi and competitive technologies like GaN, fabs. SiC and silicon. Power semis operate as a switch in high-voltage applications such Figure 1. How power switches are In total, the power device market is as automotive, power supplies, solar and categorized. Source: Infineon expected to grow from $17.5 billion in trains. The devices allow the electricity 2018 to more than $21 billion by 2024, to flow in the “on” state and stop it in the bigger dent in the market. SiC, for exam- according to Yole. Of that, the SiC device “off” state. They boost the efficiencies and ple, is growing at a double-digit pace, market will grow from $420 million in minimize the energy losses in systems. compared to single digits for silicon-based 2018 to $564 million in 2019, according to For years, the power semi market has devices, according to Yole. “The silicon Yole. In 2018, the GaN device market was been dominated by silicon-based devices, carbide power device market is expected less than a $10 million business, according namely power MOSFETs and insulated- to grow very fast, driven mainly by the to the firm. gate bipolar transistors (IGBTs). Both are automotive market,” said Hong Lin, an mature and inexpensive, but they are also analyst at Yole. “The market potential is The End of Silicon? reaching their theoretical limits in several huge and is attracting a lot of players. We In total, the world generates 12 billion respects. expect the competition to be very strong in kilowatts of power every hour, accord- That’s where GaN and SiC fit in. In the coming years.” ing to North Carolina State University. the market for years, GaN and SiC devices GaN is a tiny market today. “When More than 80% of the world’s electricity compete against IGBTs and MOSFETs in we calculate the growth rate in five years, is transported through a power electronic various segments. Both GaN and SiC are GaN could be really much bigger than sili- system, according to the school. wide-bandgap technologies, meaning they con carbide and IGBTs. The market could Power electronics make use of various are faster and more efficient than silicon- grow very fast,” Lin said. devices that control and convert electric based devices. As it turns out, though, there is no one power in systems, such as cars, motor Still, GaN and SiC devices have power semi that fits all needs. There is a drives, power supplies, solar and wind tur- relatively low adoption rates and won’t place for all technologies. “The total mar- bines. displace their silicon rivals anytime soon. ket is growing very quickly. Every device Generally, power is wasted during Today, silicon-based devices have more can still have their place, at least for the the conversion process in systems. In one than 90% market share in the overall foreseeable future,” Lin said. example, the power wasted in desktop PCs power semi market, according to Yole Nonetheless, there are a number of sold in 1 year is equivalent to 17 500MW Développement. Generally, GaN and SiC events taking place in this market. Among power plants, according to NC State. devices are expensive technologies with them: Therefore, the industry requires more various challenges. • Cree, Rohm and others are increasing efficient devices, such as power semis and That’s beginning to change because their capital spending and building other chips. Each power semi is denoted new GaN and SiC devices are making a new SiC fabs. Vendors are preparing by a numerical figure with a “V” or volt- meptec.org WINTER 2019 MEPTEC REPORT | 15

MARKET TRENDS

age. “The ‘V’ as in VDSS is the maximum compared to their silicon-based peers. The material based on silicon and carbon. It allowed operating voltage, or drain-source devices can be made much smaller in size has 10 times the breakdown field strength voltage specification,” explained Alex for the same relative voltage and current and 3 times better thermal conductivity Lidow, chief executive of EPC. “The handling capability.” than silicon. terminology ‘DSS’ means drain-to-source GaN and SiC power semis have been There are two SiC device types—SiC with the gate shorted.” shipping for some time, but they are still power MOSFETs and diodes. SiC power Nonetheless, there are several power expensive. “The manufacturing cost is MOSFETs are power switching transistors. semis to choose from. On the silicon front, the main obstacle to market growth, since A diode passes electricity in one direction the choices include power MOSFETs, today both are mainly still using 6-inch and blocks it in the opposite direction. super-junction power MOSFETs and and below wafers for production. Once the SiC devices are produced in 150mm IGBTs. cost can be improved to a certain thresh- fabs today, although 200mm is in R&D. Considered the least expensive and old, the market size could explode,” Liu In the production flow, a SiC substrate is most popular device, power MOSFETs are said. developed. An epitaxial layer is grown on used in adapters, power supplies and other the substrate. It is then processed into a products. They are used in lower-voltage device. 10- to 500-volt applications. Making the substrate is the biggest Super-junction power MOSFETs, SiC and GaN challenge. “This wider bandgap gives which are souped-up MOSFETs, are used are promising the materials interesting qualities such as in 500- to 900-volt systems. Meanwhile, faster switching and higher power den- the leading midrange power semiconduc- components for sity,” said Llewellyn Vaughan-Edmunds, tor device is the IGBT, which is used for director of strategic marketing at Applied 1,200-volt to 6.6-kilovolt applications. the power semi- Materials, in a blog. “A major challenge is MOSFETs compete against GaN conductor market substrate defects. Basal plane dislocations devices in the lower voltage segments, and screw dislocations can create ‘killer while IGBTs and SiC go head-to-head at due to the higher defects’ that must be reduced for SiC the high end. All devices compete with efficiency and devices to achieve the high yields required one other in the 600- to 900-volt range. for commercial success.” Regardless, IGBTs and power MOS- smaller form-factor The issues with the SiC substrate trans- FETs will remain the mainstream tech- lates into higher costs and potential supply nologies for the foreseeable future. “Sili- characteristics. constraints during boom cycles. “Cost is con is a very mature technology, leading a challenge versus silicon or even GaN- to better cost positions in many aspects, on-silicon approaches. There are two main including from a supply chain and internal Still, there is a place for all power semi reasons—the cost of the SiC substrate and production processes to existing designs types, according to Infineon. Infineon has the material yield. Given the tight supply and processes at the customer side,” said a unique perspective, given that it sells conditions, those prices are unlikely to Gerald Deboy, a senior principal at Infi- IGBTs, MOSFETs, GaN and SiC. start dropping soon, but the situation will neon. “This is why for many applications “Criteria for selection of a wide- improve,” said Kevin Crofton, president of silicon-based power switches will continue bandgap device instead of traditional SPTS Technologies and senior vice presi- as the preferred technology for many silicon depends on balancing system cost dent at KLA. years.” and performance requirements for particu- To address the cost issues, some ven- Silicon-based devices, however, have lar applications,” Infineon’s Deboy said. dors are working on 200mm SiC fabs. several limitations, such as high conduc- “There are various applications where This will increase the die per wafer, there- tion losses and low switching frequencies. a tipping point in cost and performance by reducing the cost. Conduction loss is due to the resistance in goals has been reached for systems based Meanwhile, SiC MOSFETs are based the device. on wide bandgap material. Depending on two structure types—planar and trench. That’s why OEMs are interested in two on the specific application, GaN or SiC Planar incorporates a traditional source- wide-bandgap technologies—GaN and devices have a better cost position at the gate-drain structure. Trench forms a “U SiC. Silicon has a bandgap of 1.1 eV. In system level, even while the GaN or SiC shape” vertical gate channel. comparison, SiC has a bandgap of 3.3 eV, device itself is more expensive than the “At the device level, first and second while GaN is 3.4 eV. silicon alternative.” silicon carbide MOSFET generations “GaN and SiC are wide-bandgap mate- based upon planar technologies are now rials, which means higher bonding energy What is SiC? well established, but scaling of these tech- of the atoms in the crystal,” said Steven The SiC market is heating up. Sup- nologies to reduce cost and improve per- Liu, vice president of corporate market- pliers of SiC devices include Cree/Wolf- formance is technically challenging,” said ing at UMC. “SiC and GaN are promising speed, Infineon, Mitsubishi, On Semicon- David Haynes, senior director of strategic components for the power semiconduc- ductor, STMicroelectronics, Rohm and marketing at Lam Research. “Trench- tor market due to the higher efficiency Toshiba. based silicon carbide MOSFETs offer the and smaller form-factor characteristics, SiC is a compound semiconductor potential to overcome this scaling barrier meptec.org WINTER 2019 MEPTEC REPORT | 17 MARKET TRENDS

for key applications in electric vehicles deliver significant cost benefits versus all ics and RF. The RF version of GaN is used and hybrid electric vehicles, but the per- silicon-based IPMs or indeed hybrid IPMs in 5G, radar and other applications. GaN formance and reliability of these devices in a smaller form factor. However, at the power devices, which are different, are still must improve to address a broader device level, IGBTs are still substantially used in power switching apps. EPC, GaN range of automotive applications.” cheaper than SiC MOSFETs and have Systems, Navitas, Panasonic, Transphorm In both cases, suppliers are striving proven performance and reliability, as well and others sell GaN power devices. to make good parts with a low on-resis- as being established in the automotive These devices are made on 150mm tance. This involves unwanted resistance supply chain. As a result, it is likely that wafers. Many suppliers have their devices between the source and drain. “My goal IGBT and SiC technologies will coexist produced on a foundry basis by Episil and is to make every generation with a lower for many years.” TSMC. specific on-resistance,” said John Palmour, One expert summarized the situation In EPC’s GaN flow, a thin layer of CTO of power and RF at Cree. “It also has with SiC. “If you look at Japan, they are aluminum nitride (AlN) is deposited on a to be reliable.” making 3.3-kV SiC MOSFETs. They have silicon substrate. A GaN layer is grown on SiC-based devices, meanwhile, are a massive rail infrastructure there,” said the AlN layer. A source, gate and drain are used in 600-volt to 10-kilovolt applica- Victor Veliadis, executive director and formed on the GaN layer. tions. At the high end, some sell 3.3- to CTO at PowerAmerica, a Manufactur- “From a technical perspective, GaN 10-kilovolt devices, which are used for ing USA institute that is accelerating the remains less mature than SiC,” Lam’s power grids, trains and wind power. development of wide bandgap semicon- Haynes said. “If one considers GaN-on- The big market for SiC falls in the ductor technology. silicon HEMT (high electron mobility 600- to 1,200-volt range. For this, battery- transistor) technologies, yield remains a electric cars are the biggest market, fol- concern because of the quality of GaN lowed by power supplies and solar. GaN and SiC are MOCVD growth on silicon. There are also For years, electric-vehicle OEMs used still challenges associated with device per- IGBTs and MOSFETs in many parts of taking off. These formance and reliability.” the vehicle. Then, instead of using IGBTs, devices give That’s not the only issue. “Wafer Tesla began using STMicroelectronics’ breakage caused by wafer bow is still an SiC power devices for the traction inverter engineers some issue for this technology,” KLA’s Crof- within its Model 3 car. The traction invert- ton said. “The plasma processes are also er provides traction to the motor to propel new and different required to be very low energy because a vehicle. SiC devices also are used for the options. But of concerns about plasma-induced device DC-to-DC converter and on-board charger damage. Equipment makers are striving to in electric cars. they won’t make their reactors sufficiently benign to Other OEMs are also evaluating or displace silicon. the device.” using SiC. “The performance of silicon On the device front, meanwhile, GaN carbide provides higher efficiencies. That semis are targeted for different markets. allows you to go further on a battery “1,200 and 900 volts are automotive. EPC and others compete in the lower charge or reduce the battery, which is the That’s the biggest application for SiC,” voltage segments from 15 to 200 volts. most expensive part of the vehicle,” Pal- Veliadis said. “If you look where silicon In these segments, GaN competes against mour said. carbide is going, it started at 1,200 volts, power MOSFETs. Each electric car vendor has differ- which is far from where silicon is com- Others compete in the 600-, 650-, and ent requirements. “We refer to it by bus petitive. Now, it’s trying to work it’s way 900-volt markets. These devices compete voltage. A standard bus voltage would be down and trying to get market share in the against IGBTs, MOSFETs and SiC. 450 volts. If you have a 450-volt bus, you 900- and 600-volt range. One company, EPC, is expanding would use a 650-volt power transistor. “If you go to 600 volts, and you look its efforts in the low-voltage GaN arena. Some people are also looking at using an at everything silicon does, SiC will likely “It was only about a year ago that EPC 800- or 850-volt bus. There, you would do it more efficiently. There are obstacles did what I call a frontal assault on sili- use a 1,200-volt transistor,” Palmour said. when you go to a lower voltage. At 600 con MOSFETs —and we did that at the “Some people are looking in between. We volts, silicon is still relatively efficient 48-volt node,” EPC’s Lidow said. “GaN, are having discussions with people about because of the infrastructure. It’s very at least from EPC, is not only higher 650, 900 and 1,200 volts.” cheap. When you go to 1,200, it’s very performance than MOSFETs, but we also Some OEMs will use SiC. Others expensive to do it with silicon,” he said. priced it right at MOSFET prices.” may stick with IGBTs due to cost. “The Indeed, there are some changes taking cost is still a challenge and competition Going, Going GaN place in the 48-volt market in automotive, from proven silicon-based IGBT solutions Meanwhile, GaN, a binary III-V mate- data centers and other segments. will be a reality for some time to come,” rial, has 10 times the breakdown field For example, data centers consist of Lam’s Haynes said. “At the integrated strength with double the electron mobility a multitude of servers, each of which are power module (IPM) level, SiC can win than silicon. housed in a cabinet or rack. The power is out. Indeed, a SiC power module can GaN is used for LEDs, power electron- distributed in the backplane of the rack

18 | MEPTEC REPORT WINTER 2019 meptec.org using rack-mounted power supplies. like 5, 4 or 3 volts. They are using GaN to GaN, meanwhile, is gaining traction at In the data center, AC voltage is gen- do that.” the 600-, 650- and 900-volt markets, espe- erated and fed into the server racks. The In 12-volt backplanes, some OEMs cially the consumer adapter market and power is then converted into a lower volt- used 40-volt power MOSFETs, according other systems. “GaN is making inroads age. At one time, the racks used 12-volt to a blog from GaN Systems. At 48 volts, into areas where silicon performance is power supplies. Over time it became inef- OEMs are forced to use 100-volt MOS- simply not acceptable,” said Primit Parkih, ficient to distribute the power at 12 volts FETs, but these are less efficient, accord- chief operating officer at Transphorm. “As because it caused an increase in power ing to the company. GaN prices decrease, GaN will continue to consumption and losses for servers in the OEMs also have the option to use chip away at the current market.” data center. 48-volt DC-DC converters based on GaN For 600 and 650 volts, GaN is targeted So in 2011, Facebook and others devices. “They are smaller, cheaper and for adapters, automotive and power sup- formed the Open Compute Project (OCP). more efficient. And the dominant topology plies. At 900 volts, GaN is targeted for As part of its efforts, OCP pushed for is something called an LLC topology. And automotive, battery chargers, power sup- a 48-volt power rack distribution spec, these things are tiny and 98% to 99% effi- plies and solar. Like SiC, GaN is trying which is more efficient and also reduces cient,” Lidow said. to get more traction in electric vehicles, power. Besides servers, GaN is targeted for especially for on-board chargers and DC- “In the past, you would have 12 volts other 48-volt apps. “It’s coming in on to-DC converters. coming onto the board. It would go to a automotive. Instead of having a kilowatt of point-of-load converter, and that would electrical load, they’re going up to 6 and 8 Conclusion convert from 12 volts down to the voltage kilowatts. So they’re going to 48-volt sys- Clearly, GaN and SiC are taking off. needed by the microprocessor. But it took tems. And they’re going to GaN,” he said. These devices give engineers some new a lot of real estate, and it wasn’t efficient,” “Robots are going to 48 volts for similar and different options. Lidow said. “Now, they’re bringing the 48 reasons. So there are different marketplac- But they won’t displace silicon. It’s volts onto the server board. And in one big es feeding off each other in the advances difficult to replace a familiar technology in step, they are going all the way down to in GaN.” mission-critical products. ◆

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meptec.org WINTER 2019 MEPTEC REPORT | 19 PACKAGING

Packaging & Assembly for High-Temperature Electronics Part V – Reliability and Testing

Dr. Randall K. Kirschman R&D Consultant for Electronics Technology

PART I OF THIS SERIES OF ARTICLES Arrhenius Model introduced semiconductor devices and A widespread approach to predict— their high-temperature capabilities that via extrapolation—the effect of tempera- must be accommodated by assembly and ture on electronic component failure rates packaging materials and techniques, plus is the Arrhenius relation: a glimpse of assembly and packaging Rate, R = A•exp(−E /kT) Eq. 1 materials and technology in regard to a high-temperature operation. Parts II, III Where prefactor A is a constant, and IV explored the challenges presented Ea is an associated energy (eV) by variations of the basic properties of called the activation energy, assembly and packaging materials as k is Boltzmann’s constant (0.862e−4 eV/K), temperature is raised. and T is absolute temperature (K).* Figure 2. Example of a process rate changing with time (intermetallic growth in Au-Al This Part, concluding this series, wirebond) at a constant temperature (200°C) presents a few basic observations on For packaging and assembly, values Data from [5]. reliability and accelerated testing, in of the activation energy, Ea, are reported relation to electronics packaging and to range roughly between 0.5 and 2 eV[3][4]. tion then is how effective is an Arrhenius assembly for high-temperature opera- Figure 1 is a logR-versus-T plot of Eq. 1 treatment for high operating temperatures? [1] tion . Reliability is a serious challenge for three Ea values in this range. An expo- One difficulty is that Eq. 1 states that for high-temperature electronics, and a nential relationship (described below) is R is a function of Ea and T; but not a few aspects have been touched upon in included for comparison, which appears function of time. However, especially at previous Parts. as a straight line in contrast to the curved high temperatures, many processes exhibit Certainly, semiconductor devices and lines of the Arrhenius relation. a rate change over time at a constant passive components spring to mind in It is comforting to have some uncom- temperature. As an example, the experi- connection with reliability and acceler- plicated guide for reliability prediction— mental data in Figure 2 for intermetallic ated testing. However, packaging and whether it is applicable or not. The ques- growth in an Au-Al wirebond show the assembly also play a critical role, in the rate decreasing considerably with time form of die and substrate attachments, at a constant temperatureData from [5]. This wirebonds, encapsulation, underfill, implies an Ea that is changing with time and molding. (Although the latter three at a constant temperature, which muddies typically apply only to the lower end of the Arrhenius treatment and makes com- high-temperature electronics, because parisons between different temperatures polymeric packaging materials raise reli- difficult. Besides, it is unclear how inter- ability concerns at temperatures above metallic growth—as an example—relates ≈200–250°C[2]. (See Parts I and II) to failure rate via Arrhenius. Increasing temperature is associated Furthermore, as has often been pointed with faster aging, shorter lifetimes, and out, a multi-material, multi-component degraded reliability because there is more electronic assembly (e.g. Figure 3) will thermal energy to enable restructuring, likely have a menagerie of degradation decomposition, migration, metallurgical mechanisms (processes) represented by a Figure 1. Comparison of Arrhenius rates for and chemical interactions, and other det- range—or even a “spectrum”—of activa- three activation energies, Ea, with adjusted rimental processes. However, tempera- prefactors, plus the exponential doubling- tion energies, and thus a range of tem- ture is not the only factor, and might not for-10°C line (dashed gray line, arbitrarily set to 1 perature dependencies, particularly over be the predominant one. at −100°C). an extended temperature range typical of high-temperature electronics[6][7][8]. Even *All temperatures in equations are absolute temperatures. something as “simple” as a wirebond can

20 | MEPTEC REPORT WINTER 2019 meptec.org have several degradation mechanisms, each with a different rate: annealing, cor- rosion, interdiffusion, and intermetallic formation[9]. This complication is usually brushed aside by using a single “aggregate,” “average,” “effective” or “global” Ea for all processes over the temperature range considered. Some individual physiochemical pro- Figure 3. A down-hole (well-logging) multi-chip module specified for 2 years operation at 260°C. cesses, (e.g. diffusion, intermetallic com- Photo courtesy Quartzdyne, Inc. pound formation, oxidation, decomposition, outgassing, electrochemical migra- T (°C) → 22** 125 300 500 tion, or growth of whiskers, dendrites and filaments), might obey Arrhenius. Accel factor for Ea = 1 eV and ΔT = 10°C 3.6 2.0 1.4 1.2 But for other processes the temperature dependence of failure is overshadowed ΔT (°C) for Ea = 1 eV and doubling 5.3 9.7 20.0 37.0 by other factors. Consider solder joints E (eV) for doubling and ΔT = 10°C 0.54 0.97 2.0 3.6 and wirebonds (two primary “wearout” a items particularly applicable to packaging and assembly). Although constant high Table 1. Variations on the theme of the doubling-for-10°C rule (using Eq. 1). temperature would be a major influence, these are more likely to fail as a result of Figure 1 provides a graphic illustra- This assumes that a component will temperature variations (driven by envi- tion of the last example: Around 125°C exhibit the same failure mechanisms at ronmental temperature, by internal power, the doubling-for-10°C line (dashed gray) TTEST as it does at TOPER and that the or by a combination) and exacerbated and the Ea = 1 eV curve (green line) have mechanisms obey the Arrhenius relation. by vibration or shock. High temperature similar slopes, confirming that the “rule” As explained above, this becomes less exposure can even remove damage[9]. is a reasonable approximation around this likely as the temperature range is expand- Similar considerations apply to encapsula- temperature, but only around this tempera- ed. tion, underfill, and molding materials. ture for Ea ≈ 1 eV. For Ea = 0.5 eV, the The Arrhenius equation may be recast slopes are similar around 22°C, and for Ea as Doubling-for-10°C = 2 the slopes are similar around 300°C. logR = logA − Ea/kT Eq. 2 Next, consider the mantra that a In conclusion, the doubling-for-10°C process doubles in rate for every 10°C “rule” is not applicable in general, but Thus, a process obeying Arrhenius increase[10]. How does this relate to Arrhe- only under specific parameter circum- appears as a straight line on a logR-verus- nius—which might be supposed is the stances, and especially not for high-tem- 1/T plot with slope = −Ea. Figure 4 is such [10] basis for this doubling-for-10°C “rule”— perature electronics . a plot for three Ea values appropriate for and to an extended temperature range? electronic packaging and assembly. The Calculating with Eq. 1 shows that Accelerated Testing measured Ea can vary with temperature if the doubling-for-10°C “rule” follows When the required lifetime of a Arrhenius around 125°C, assuming the component is long, say years, real-time commonly used Ea of ≈ 1 eV. What reliability evaluation is generally impracti- about other temperatures? Keeping Ea ≈ cal. A faster evaluation method is needed. 1 eV and ΔT = 10°C, the corresponding However, in the quest for such a method, increase in rate (or acceleration factor see there are many pitfalls, especially for below) would be 3.6x at 22°C**, but only high-temperature packaging and assembly. 1.2x at 500°C, rather than 2x (Table 1, A popular method is the accelerated first row). test. The idea is overstress, which may be Considering the rule from other electrical (e.g. voltage, current, power), angles: Again keeping Ea ≈ 1 eV, a dou- or environmental (e.g. moisture, accelera- bling of rate at 22°C would require a tion, radiation), in addition to, or instead ΔT of only 5.3°C, but at 300°C it would of, temperature. The following concerns require a ΔT of 20°C, and at 500°C a ΔT accelerated testing only via increased tem- of 37°C (Table 1, second row). perature: measuring failures or degrada- Alternatively, a doubling of rate for a tion over time at a constant temperature, Figure 4. Change of E for different T rang- ΔT of 10°C needs an Ea of only 0.54 eV TTEST, higher than the operating tem- a es. The prefactors have been set at arbitrary values at 22°C, but 2 eV at 300°C, and 3.6 eV at perature, TOPER, often accompanied by an for illustration; the combined curve (sum of the three 500°C (Table 1, bottom row). Arrhenius treatment. Ea lines) is slightly displaced for clarity. A doubling- for-10°C exponential is included for comparison **Room temperature is taken to be 22°C. (dashed gray line). meptec.org WINTER 2019 MEPTEC REPORT | 21 PACKAGING

TTEST → 300 400 500 400 500 600 interact in complex ways with temperature vs vs vs vs vs vs vs and with each other. TOPER (°C) 200 200 200 300 300 500 ΔT (°C) → 100 200 300 100 200 100 Alternatives? Considering the pitfalls indicated in 0.3 3.6 8.9 17 2.5 4.8 1.7 the preceding, what are possible alterna- 0.5 8.5 38 120 4.5 14 2.4 tives methods to assess and work toward (eV)

a reliability for high-temperature electron-

E 1.0 72 1,500 1.4e+4 20 190 5.6 ics? Without going into detail, here are a 2.0 5,200 2.1e+6 1.8e+8 410 3.5e+4 31 few[11]: Real-time testing may be an expedi- Table 2. Acceleration factors, F, for high-temperature accelerated testing (Eq. 3) ent option for applications where limited Shading indicates low acceleration factor, F < 10. operating lifetime (e.g. ≈ 100–1000 hours) or frequent maintenance can be accepted there are different mechanisms dominant that it will exceed one or more “trigger” as a tradeoff against development time at different temperatures, each having a temperatures: e.g. polymer glass-transition and cost. Possible examples include well- different Ea. As shown by Figure 4 as well temperature (Tg) or decomposition tem- logging instrumentation, jet-engine devel- as Figure 1, as temperature increases, a perature, solder melting temperature opment instrumentation, and data tracers. process with lower Ea can be overshad- (MP†), phase change, or ductile-brittle Step-stress testing applies increasing [6] owed by a process having a higher Ea. transition . Failure would be immediate overstress to identify weak points of a Indeed, it is observed experimentally that or the failure rate could be greatly acceler- package or assembly. Typically, tempera- activation energies tend to increase with ated out of proportion and meaningless for ture is increased incrementally at time increasing temperature. Thus, trying to prediction at TOPER. Individual parts might intervals until something fails, followed [12] curve-fit a single aE is unreasonable, as not even survive the high TTEST. by analysis and resolution . Preferably, illustrated by the combined (black) curve Thus, acceleration via temperature (as testing would include other stresses that in Figure 4. well as burn-in) may be impractical for will be experienced in use; also, the dif- For high-temperature electronics, with high-temperature electronics, as this could ference between testing while unpowered, a typically wider temperature range, or bring about a failure mechanism that dif- powered but not operating, and fully oper- as TTEST – TOPER widens, encountering fers from the relevant ones. ating needs consideration. shifting Ea values is more likely. Conse- Physics-of-failure (PoF) should be quently, prediction based on extrapolation Field Environment well-suited to high-temperature electron- via Arrhenius is simplistic and suspect and For real-life applications constant ics when thermal energy becomes a major likely to be optimistic[3][11]. temperature operation is rare. Consider stimulus and physiochemical processes Proceeding further, a reshuffle of the vehicles, aircraft engines, down-hole become more active. A package or assem- Arrhenius formula provides an accel- probes, spacecraft, and industrial pro- bly could be conceptually “taken apart” eration factor, F, comparing the rate, R, cesses—where high-temperature elec- to test, analyze, and simulate individual between TTEST versus TOPER: tronics would be applied. Especially for structures (e.g. a single joint) indepen- high-temperature electronics, the particu- dently, and whose “failure” mechanisms – Acceleration factor, F – RTEST/ROPER = lar temperature-vs-time, T(t), probably might be amenable to accelerated testing exp[(Ea/k)(1/TOPER – 1/TTEST)] irregular, will likely have much greater and Arrhenius treatment[3]. Eq. 3 relevance to reliability “in the field” than If PoF characterizes a “wearout” (“fail Considering only temperature as a constant (time-independent) temperatures. ure”) mechanism (e.g. metal fatigue in stress, Table 2 presents acceleration fac- Moreover, mechanical stresses from a joint) and related consequences (e.g. tors calculated from Eq 3. Lower Ea or nonuniform temperature are more likely high thermal and electrical resistance higher temperature means a lower F for as temperature increases, because of gen- and detachment of the joint), can this be the same TTEST versus TOPER and a “flat- erally decreasing thermal conductivity, or called a reliability problem, or is it rather ter” curve (Figure 1). Consequently, a from high-power devices, which are often a question of inadequacy of design? This useful acceleration factor, say > 10, may associated with high-temperature electron- facet of PoF mostly indicates what not to be impractical. For example, for TOPER = ics. do and might be better termed “Physics of 200°C or 300°C, if there is an Ea ≈ 0.5 eV Besides temperature, additional stress- Wearout.” mechanism, then TTEST must be at least es are typical. Reliability will be strongly Sound design and fabrication for 200°C higher than TOPER for F > 10 (bold influenced by diverse environmental and high-temperature operation should be red numbers). If Ea ≈ 0.3 eV the situation operational conditions: electrical stress foremost, addressing possible degrada- is even worse. and transients, static discharge, magnetic tion mechanisms, in concert with PoF, Even assuming that accelerated test- fields, hostile atmospheres, chemicals, since the objective is reliability rather than ing is practical, its temperature range of contaminants, pressure, radiation, mechan- testing per se. Reliability depends on a applicability must have limits. As TTEST is ical vibration and shock, mishandling, and component’s design, materials, geometry, increased, it becomes increasingly likely others. Furthermore, these stresses can structure, and fabrication conditions.

22 | MEPTEC REPORT WINTER 2019 meptec.org Since many of the “failure” (i.e. melting-point temperature (for elements or [11] J. J. Kopanski, D. L. Blackburn, G. G. Har- wearout) mechanisms are known (e.g. compounds), or eutectic or solidus tem- man and D. W. Berning, “Assessment of reli- metallic interdiffusion, migration, fatigue), perature (for alloys). Higher temperature ability concerns for wide-temperature operation of semiconductor devices and circuits,” Trans. avoidance solutions could be applied for (≈ > 300–400°C, although definitions differ) joining materials are usually referred to as - First International High Temperature Electron- high-temperature packaging and assembly. brazes. As used in this article, “solder” may ics Conference (HiTEC), eds. D. B. King and In other words, don’t design in a mecha- include both solders and brazes. F. V. Thome, Albuquerque, New Mexico, 16-20 nism that is known to cause failure, bear- June 1991, pp. 137-142 (Reprinted in High- ing in mind the component’s temperature, Temperature Electronics, ed. R. Kirschman, see References lifetime, and other conditions of the appli- Reference [1].) cation. Design-in and build-in reliability [1] R. K. Kirschman, Introduction to Part I: [12] M. Watts, “Life testing of high temperature rather than attempt to test-in reliability[12]. “General Introduction,” pp. 3-35, in High-Tem- electronic circuits for downhole,” Proc. - 2004 perature Electronics, ed. R. Kirschman, IEEE International Conference and Exhibition on Conclusion Press/Wiley, 1999; ISBN: 0-7803-3477-9. High Temperature Electronics (HiTEC 2004), Santa Fe, New Mexico, 17-20 May 2004 paper In regard to reliability and testing for [2] Y. Yao, G.-Q. Lu, D. Boroyevich and K. D. TA13. ◆ high-temperature electronics there is no T. Ngo, “Survey of high-temperature polymeric simple, universal answer. High-tempera- encapsulants for power electronics packag- ture operation of packaging and assembly ing,” IEEE Trans. Components, Packaging and Dr. Randall Kirschman is based in Silicon Manufacturing Technology, v. 5, n. 2, pp. 168- enters new and mostly uncharted terri- Valley and provides consulting related to 181, Feb. 2015. tory. Reliability and testing methods for R&D for electronic devices and circuits, “standard” temperature-range (−55°C to [3] P. Lall, M. G. Pecht and E. B. Hakim, as well as assistance in obtaining funding, +125°C) electronics will need reassess- Influence of Temperature on Microelectron- particularly for extreme temperatures. He ics and System Reliability, CRC Press, 1997; also presents professional development ment and revision[1]. ISBN 0-8493-9450-3; doi.org/10.1109/ courses covering the principles and practi- TCPMT.2014.2337300 Series Wrap-up cal aspects of low-temperature and high- temperature electronics. (www.ExtremeTem- [4] G. P. Pandian, D. Das, C. Li, E. Zio and This is the final article in this series peratureElectronics.com). He received his M. Pecht, “A critique of reliability prediction of five. Certainly, a great deal more Ph.D. from Caltech in physics and electrical techniques for avionics applications,” Chinese could be (and has been) said about high- Journal of Aeronautics, v. 31, n. 1, pp. 10-20, engineering. E-mail: [email protected] temperature electronics, but hopefully Jan. 2018; doi.org/10.1016/j.cja.2017.11.004 these brief articles have provided a sense of the issues involved in seriously extend- [5] S.-A. Gam, H.-J. Kim, J.-S. Cho, Y.-J. Park, J.-T. Moon and K.-W. Paik, “Effects of Cu and ing the operating temperature capability Pd addition on Au bonding wire/Al pad interfa- EPOEPOXXYY foforr ChipChip of electronics. Electrical performance is cial reactions and bond reliability,” J. Electronic paramount but packaging and assembly Materials, v. 35, n. 11, pp. 2048-2055, Nov. CoatingCoating && GlobGlob TopTop underlie electrical performance and play a 2006; doi.org/10.1007/s11664-006-0312-9 vital role. ApplicationsApplications [6] R. J. Allen and W. J. Roesch, “Reliability Applications are waiting for electron- prediction: The applicability of high temperature ONE PART ADHESIVE EP17HTNDCCM ics with high-end temperature capabilities, testing,” Solid State Technology, v. 33, n. 9, pp. beyond the present +125–200°C. And as 103-108, Sept. 1990. the market for high-temperature applica- NASA low outgassing [7] F. Bayle and A. Mettas, “Temperature tions steadily increases, so does the eco- acceleration models in reliability predictions: Thermal conductivity nomic incentive to develop and qualify Justification & improvements,” IEEE 2010 Proc. 9-10 BTU•in/ft•hr•°F new assembly and packaging materials - Annual Reliability and Maintainability Sympo- and technologies. ◆ sium (RAMS), San Jose, California, 25-28 Jan. Electrical insulation 2010; doi.org/10.1109/RAMS.2010.5448028 Volume resistivity >10 ohm-cm Acknowledgements [8] L. De Schepper, W. De Ceuninck, H. Service temperature range I am indebted to Ross Wilcoxon (Col- Stulens, L. M. Stals, R. Vanden Berghe and S. -80°F to +600°F Demolder, “A new approach to the study of the lins Aerospace) for reviewing this article intrinsic ageing kinetics of thick film resistors,” and for valuable suggestions. I especially Hybrid Circuits, n. 23, pp. 5-13, Sept. 1990. thank Bette Cooper of MEPTEC for sug- gesting this series of articles, and Gary [9] L. Yang, P. A. Agyakwa and C. M. Johnson, “Physics-of-failure lifetime prediction models Brown of MEPTEC for his excellent for wire bond interconnects in power electronic transformation of my manuscripts and modules,” IEEE Trans. Device and Materials pedantic revisions into published form. Reliability, v. 13, n. 1, pp. 9-17, March 2013; doi.org/10.1109/TDMR.2012.2235836 Notes [10] R. Wilcoxon, “Does a 10°C increase in 154 Hobart Street, Hackensack, NJ 07601 USA †Melting point (MP) as used here means the temperature really reduce the life of electronics +1.201.343.8983 ∙ mainmasterbond.com temperature above which the material is no by half?,” Electronics Cooling, pp. 6-7, Summer www.masterbond.com longer solid, and thus can be the material’s 2017. meptec.org WINTER 2019 MEPTEC REPORT | 23 PACKAGING

Post-Layout Verification, Analysis and Test Considerations for 2.5/3D Heterogeneous Advanced Packages

Kevin Rinebold, Technology Manager – Advanced Packaging Solutions Mentor®, A Siemens Business

MEMORY ACCESS FOR SOC/ASIC and processes together onto a single sub- is required to ensure fast, accurate, auto- devices historically has been facilitated strate, otherwise known as heterogeneous mated flows that ensure package design- by mounting and connecting these devices integration. These heterogeneous pack- ers can meet their market schedules and on a printed circuit board (PCB). Today’s ages utilize manufacturing techniques, performance expectations. Ideally these signal speeds and data rates coupled with materials, and processes that increasingly flows provide a single integrated process the need to use less power and generate are more silicon-like thus creating unique for electrical, stress, and test analysis built less heat is changing that paradigm for challenges to traditional design tools and around a 3D digital model, or twin, of the these devices. Increasingly SoC/ASIC methodologies. entire heterogeneous package assembly. devices are co-located with memory in Heterogeneous packaging relies on a the same package to support the needed diverse eco-system to supply the die, sub- Heterogeneous Assembly Level bandwidth and performance. The current strates, and services to design, assemble, Verification trend of integrating a SoC/ASIC with and test these package. Given the mul- 2.5/3D Heterogeneous packages high-bandwidth memory (HBM) on an tiple data sources and formats it is clear typically incorporate multiple devices interposer is a good example. The inter- that a comprehensive verification flow is and multiple substrates to deliver the poser provides the needed density and required—one that accounts for assembly- needed solution for system scaling and performance requirements while providing level physical verification, as well as performance. With decreasing delineation an overall smaller form-factor. more in-depth, system-level electrical, between die and substrate the close prox- This approach can also be applied to stress and testability verification. At the imity of these elements greatly enhances bring devices of disparate technologies same time, expanded EDA tool support chip-package interactions (CPI) neces-

Figure 1. Single Environment for Cross-Substrate Connectivity Planning and Optimization.

24 | MEPTEC REPORT WINTER 2019 meptec.org sitating a unified co-design flow. With critical elements like high-speed interfaces or power delivery, a decision on one substrate can have a ripple effect on adjacent substrates, or impact the entire system. Designers must find ways to manage multiple substrates in one environment, often while collaborating across geographies and departments, using rapid prototyping and co-design to evaluate substrate routability, electrical and thermal performance, and testing. Finding the right balance and optimal solution can be an endless cycle of iterations. Physical verification of heterogeneous assemblies has been extensively discussed, and automated solutions introduced [1][2]. There have been analyses of Figure 2. 2.5D/3D Digital Twin (Virtual Model) of Heterogeneous Assembly. the need for assembly-level layout vs. schematic (LVS) verification. Best prac- ability to aggregate data from different Physical Verification tices for an assembly-level LVS process sources and in different formats into One hallmark of IC verification has have been explored, including the required a cohesive system representation suit- been the use of multiple specialized EDA inputs (data, formats, etc.), and likely hur- able to drive verification and analysis. tools within a single framework to enable dles. There has even been discussion of Tools like Mentor’s Xpedition™ Sub- designers to perform a wide variety of how parasitic extraction could be achieved strate Integrator can import and manage verification processes. The goal is the for these assemblies [3][4]. the multiple databases comprising the same when automating heterogeneous As methodologies and flows mature, heterogeneous assembly. Ideally this is package assembly verification. Het- system-level designers also need to know done using industry standard formats erogeneous verification is significantly if package design rule checking (DRC), like LEF/DEF, AIF, GDS, or CSV/TXT simplified based on the premise each layout vs. layout (LVL) verification (die- files. Functionality should also exist that individual die has already been checked to-package alignment, scaling, orientation, automatically recognizes device/substrate to their target foundry rules. It‘s also criti- etc.), and assembly-level LVS are suf- interfaces without having to instantiate cal to maintain independence between the ficient to guarantee correct functionality pseudo components. design and verification environments to and successful manufacturing of the het- One of the primary benefits of the ensure the veracity of verification results. erogeneous assembly. What has not been digital twin approach is that it serves as Verification is comprised of DRC, addressed is the need for a single environ- the golden reference to drive verification which checks the interactions between ment that enables designers to manage all and analysis operations. This eliminates die (spacing, features sizes, etc.) which of these processes in an efficient, repeat- need to use multiple static spreadsheets may require extracting several layers able, and automated flow. to represent pin and connectivity infor- within each die to see these impacts. It In heterogeneous design and verifica- mation replaced by a full system level also includes LVL checks for alignment tion, designers must be able to coordinate netlist in Verilog format. This netlist between substrates, scaling or compensa- and manage multiple substrates (design serves as the golden reference for com- tion factors, and pad centers or overlap databases) in one environment. With the plete physical and electrical verification checks. The EDA tool must understand ability to see the complete picture (die, of every level of the design hierarchy how to differentiate the layering per die interposer, package, PCB) in one environ- (die, interposers, embedded bridges, and and per placement. Using virtual model ment, designers can better anticipate and package substrate). (digital twin) data, Mentor’s Calibre™ eliminate potential downstream issues, The digital twin enables automated 3DSTACK automatically extracts the cor- efficiently perform and evaluate trade-offs verification of heterogeneous assemblies rect assembly representation to perform and design scenarios, and clearly commu- beginning with substrate level DRC DRC/LVL checks ensuring the design nicate decisions to stakeholders. expanding into LVS, LVL, parasitic meets all physical requirements. extraction (PEX), stress and thermal Digital Twin analysis, and finally, test. Connectivity Checking (LVS) Building a digital twin (virtual Combining the digital twin with LVS checking in an IC looks at model) of the 2.5D/3D heterogeneous industry standardization and EDA tool the connected shapes and pin locations assembly provides designers a compre- automation has led to the beginning of derived from physical layout data to hensive representation of the full sys- a unified approach to providing proven, produce the physical netlist which is com- tem comprised of multiple devices and qualified signoff flows for automated het- pared against the golden schematic netlist substrates. Model construction requires erogeneous verification. to verify connectivity. An automated meptec.org WINTER 2019 MEPTEC REPORT | 25 PACKAGING

Figure 3. Integration of Verification and Layout Tools Enables Efficient Identification and Resolution of DRC Issues. package LVS flow in its simplest form and back side. These TSVs allow die and thermal analysis, designers can reference must ensure that the interposer/package substrates to be stacked and directly inter- a system-level model for in-context die GDS correctly connects die to die (for connected. However, in addition to their level simulation, and create a die level multi-die systems) and die to C4/BGA own significant electrical characteristics, thermal model that can be imported bumps (for both single die and multi-die TSVs also have an indirect effect on the into a larger system for thermal simula- systems) as intended by the designer [3]. electrical behavior of devices and inter- tion. While boundary conditions can be In heterogeneous package assem- connects in their vicinity. To accurately imported for more accurate modeling at blies this connectivity may be the die/ model a 2.5D/3D heterogeneous system, the die level this solution also exports interposer, die/interposer/package, or die/ a designer needs tools that extract precise detailed thermal models of the heteroge- interposer/package/pcb. Regardless of the electrical parameters from the physical neous assembly for accurate system level configuration it all starts with the ability structure of these 2.5D/3D elements, modeling. This provides designers the to generate and manage a system netlist. which can then be fed into behavioral ability to accurately model from the die The system netlist is compiled from the simulators [4]. Utilizing data from the vir- level to the system level (e.g. inside the virtual model (digital twin) of the overall tual model (digital twin) tools like Calibre die, inside the package, and package to assembly as discussed earlier. This sys- 3DSTACK used in concert with Calibre system). tem or golden net list is then compared xACT™ can be used to extract parasitics against physical design connectivity of these 2.5D/3D elements. Mechanical Stress Analysis derived from the manufacturing data like 2.5D/3D stacking can create a variety GDS in Calibre 3DSTACK. Warnings Thermal Analysis of unintentional physical stresses, such or violations can be highlighted in the 2.5D/3D heterogeneous assemblies as substrate warpage during mounting virtual model where Xpedition Substrate bring active die into closer proximity, as well as bump-induced stress. Design- Integrator functionality can be used to making thermal interaction within the ers must be able to analyze a layout for trace and debug errors. assembly an area of concern. Given this stresses caused by such chip-package proximity and higher power densities, interactions and their impact on device Parasitic Extraction heat dissipation becomes one of the main performance. By combining Calibre lay- 2.5D/3D heterogeneous designs challenges that affects the performance out processing with proprietary modeling typically use through-silicon via (TSV), and reliability of 2.5/3D heterogeneous techniques, designers can analyze MOS- which are long vias extending through assemblies. Using Mentor’s FloTHERM™ FET channel mechanical stress, as well the die or substrate to connect the front product in conjunction with a Calibre as stress-induced variation of transistor

26 | MEPTEC REPORT WINTER 2019 meptec.org electrical parameters (such as mobility still produce failures from ESD damage these processes, a single environment that and current). or from pins missed during wafer testing. enables designers to manage all of these It’s also important to recognize ther- With multi-die packaging, the quality and processes in an efficient, repeatable, and mal and mechanical stress do not happen depth of wafer testing is critical if the automated flow is essential. ◆ in isolation but are closely intertwined. target yield of assembled parts is to be Heating effects can impact mobilities, i.e. maintained. Mentor’s Tessent™ logic test References impact stress. Similarly stresses (die/sub- tools provide a variety of “best practice” [1] Tarek Ramadan, “Crossing the chasm: Bringing strate stacking and TSVs) can also have a test capabilities for heterogeneous pack- SoC and package verification together with Calibre significant impact on the thermal conduc- age testing, including: 3DSTACK,” Mentor, a Siemens business. January tivity. 2017. https://www.mentor.com/products/ic_nanome- • Re-use of die-level test patterns ter_design/resources/overview/crossing-the-chasm- bringing-soc-and-package-verification-together- Testing • Use of a common test access port (TAP) interface for all levels of with-calibre-3dstack-cee51550-0dca-4306-b33a- Known good die (KGD) are key 4131df0c6436/?cmpid=10522 substrate to effective testing prior to stacking • Use of IJTAG to enable flexibility [2] Dusan Petranovic and Karen Chow, “3D-IC in 2.D/3D heterogeneous assemblies. by controlling the modes of test system verification methodology: solutions and Package-level test generation is also patterns challenges.” Electronic Design Process Sympo- important—test teams should reuse die- sium, April 2011. https://www.researchgate.net/ • Remapping of die level test patterns level built-in self-test (BIST) and scan publication/268208901_3D-IC_System_Verifica- to the other levels of package tion_Methodology_Solutions_and_Challenges patterns by mapping them up to package substrate level. Boundary scan testing of the pack- [3] Tarek Ramadan, “Package designers need age interconnect structures ensures the IO Summary assembly-level LVS for HDAP verification,” Men- are actually connected, and can identify Heterogeneous packaging is a dis- tor, a Siemens business. December 2017. https:// www.mentor.com/products/ic_nanometer_design/ any substrate fabrication or assembly ruptive impact on traditional design and resources/overview/package-designers-need-assem- issues. Partial stack testing is usually only verification methods. The growth of these bly-level-lvs-for-hdap-verification-6faa5d86-f8ee- done on new processes or those known or designs demands an efficient, proven 4a6b-91e8-e06ca213eb81/?cmpid=11722 expected to have poor yield. automated sign-off for physical, electrical, [4] Christian Decoin and Vassilis Kourkoulos, “Fast However, even with high-quality thermal, and manufacturing performance. and accurate extraction of 3D-IC layout structures,” wafer testing and KGD, assembly can To ensure consistency and automation of Mentor, a Siemens business. July 2012.

Call for Papers Opens August 8!

As the premier event in the semiconductor packaging We welcome previously unpublished, industry, ECTC addresses new developments, trends non-commercial abstracts in areas including, but not limited to: and applications for fan-out & fan-in packages, 3D & 2.5D integration, TSV, WLP, flip-chip, photonics, LEDs, Applied Reliability materials and other integrated systems packaging topics. Assembly and Manufacturing Technology Abstract submissions and Professional Development Emerging Technologies Course proposals for the 70th ECTC are due by High-Speed, Wireless & Components October 6, 2019. Interconnections To submit, visit: Materials & Processing Packaging Technologies www.ectc.net Photonics Conference Sponsors: Thermal/Mechanical Simulation & Characterization Interactive Presentations TECH BRIEFS

State-of-the-Art Technology Briefs A special feature courtesy of Binghamton University

This feature is brought to us by Benson as commercial microprocessors. The paste. Simultaneously, the copper is fused Chan, Associate Director, Integrated microprocessor is based on the RISC-V by a very hot plasma beam of 10,000- Electronics Engineering Center (IEEC), open-source chip architecture. (IEEC file 50,000°C whereby a connection with the Binghampton University. The State-of-the- #11328, Nanowerk News, 8/29/19) silver substrate is being formed. (IEEC Art Technology Briefs contains articles file #11260, Printed Electronics World, from the Binghamton University S3IP 7/12/19) “Flashes”. Full text is available upon request through the IEEC Site at: http:// Researchers at the Rochester Insti- www.binghamton.edu/s3ip/index.html. tute of Technology have created a laser for sound. by demonstrating a Researchers from the University phonon laser using an optically levitated of Wisconsin-Madison have devised nanoparticle. The researchers studied the a method to create pieces of “smart” mechanical vibrations of the nanoparticle, glass that can recognize images without which is levitated against gravity by the requiring any sensors, circuits or power force of radiation at the focus of an opti- sources. They use optics to condense cal laser beam. The mechanical vibra- the normal setup of cameras, sensors Researchers at the Vienna University tions become intense and fell into perfect and deep neural networks into a single of Technology have created an ultra- sync. Because the waves emerging from piece of thin glass. Embedding artificial thin transistor, with excellent electrical a laser pointer are in sync, the beam can intelligence (AI) inside inert objects is properties and can be miniaturized to travel a long distance without spreading a concept could open new frontiers for an extremely small size. This next big in all directions. In a standard optical low-power electronics. AI gobbles up miniaturization step in microelectron- laser, the properties of the light output substantial computational resources every ics is becoming possible – with two- are controlled by the material from which time you glance at your phone to unlock dimensional (2D) materials. They used a the laser is made. In the phonon laser the it with face ID. In the future, one piece of novel insulator made of calcium fluoride, roles of light and matter are reversed. glass could recognize your face without to produce the new ultra-thin transistor. (IEEC file #11148, R&D, 4/15/19) using any power at all. (IEEC file #11257, The prototype with its superior electri- Science Daily, 7/8/19) cal properties outshines all previous University of Utah engineers have models. Now the team wants to find out discovered a way to produce more elec- which combinations of insulators and tricity from heat than thought possible by semiconductors work best. It may take creating a silicon chip, known as a ‘Near- a few more years before the technology Field Radiative Heat Transfer Device,’ can be used for commercially available that converts thermal radiation into computer chips as the manufacturing pro- electricity. The team produced a 5mm- cesses for the material layers still need to by-5mm chip of two silicon wafers with be improved. (IEEC file #11280, Science a 100 nanometers gap between them. Daily,7/24/19) This could lead to much longer battery life in devices such as laptop computers Lumitronix has succeeded in integrat- and cellphones, and solar panels that are MIT researchers have built a modern ing plasma-metallized flexible printed cir- much more efficient at converting radiant microprocessor from carbon nanotube cuit boards with electronic components. heat to energy. (IEEC file #11258, Science transistors, which are widely seen as a The novel technology turns a plurality of Daily, 7/10/19) faster, greener alternative to their tradi- materials into electrically conducting and tional silicon counterparts. The micro- solderable printed circuit boards that were The EV Group (EVG) has unveiled processor, which can be built using tradi- not suitable previously for an assembly MLE™ (Maskless Exposure), a revolution- tional silicon-chip fabrication processes, with electronic components. Within the ary next-generation lithography technol- representing a major step toward making framework of this special type of metal- ogy developed to address future back-end carbon nanotube microprocessors more lization, a plasma spray head is used to lithography needs for advanced packag- practical. They demonstrated a 16-bit spray a conductive metal in the form of a ing, MEMS, biomedical and high-density microprocessor with more than 14,000 powder under high atmospheric pressure printed circuit board applications. The CNFETs that performs the same tasks onto the basic material coated with silver MLE combines high-resolution pattern-

28 | MEPTEC REPORT WINTER 2019 meptec.org ing with high throughput and yield, while to become the next embedded memory ed to register a CAGR of 10.4% from eliminating the overhead costs of photo- solution for IC products manufactured at 2016 to 2026. Increasing adoption in the masks. Heterogeneous integration is an the 28nm node and below. That includes oil and gas industry and investments in increasing driving force in semiconductor low-power wearables and IoT devices, infrastructure are factors driving growth. development, impacting the advanced MCUs, automotive, imaging and display Additionally, government initiatives to packaging, MEMS and PCB markets. ICs, edge AI accelerators, and other deploy fiber optic sensors in various con- (IEEC file #11240, Semiconductor Digest, ASICs and ASSPs. (IEEC file #11315, struction projects is propelling significant 7/2/19) Semiconductor Digest, 8/12/19) growth. The market is segmented on the basis of Technology; Rayleigh Scattering Binghamton University researchers Purdue University researchers have Based Distributed Sensor, Brillouin Scat- have found a way to improve the perfor- developed a new fabric innovation that tering Based Sensor, Raman Scattering mance of tiny sensors by developing a allows wearers to control electronic Based Sensor, Interferometric Distributed more reliable way to use actuators that devices through clothing. This technique Optical-Fiber Sensor, Application (Strain control MEMS. The team found that is capable of transforming any existing Sensing, Temperature Sensing, Acoustic/ combining two methods for electrostatic cloth into a self-powered e-textile con- Vibration Sensing, Pressure Sensing). actuation – parallel-plate and levitation taining sensors, music players or illumi- (IEEC file #11186, Sensors, 5/7/19) actuators – led to a predictable linearity nation displays using simple embroidery that neither of those systems offered on without the need for expensive fabrica- The 2019 Nobel Prize in Chemistry its own. These findings could be revolution processes. The waterproof, breath- was awarded to M. Stanley Whittingham, tionary for microphone manufacturing, able and antibacterial self-powered cloth- distinguished professor of chemistry at because with this design the signal can be ing is based on omniphobic triboelectric Binghamton University. Whittingham boosted high enough that the background nanogeneragtors (RF-TENGs), which use won the prize for pioneering research noise from the electronics is no longer an embroidery and fluorinated molecules to leading to the development of the issue. More than 2 billion microphones embed small electronic components and lithium-ion battery. He holds the origi- are made around the world each year, and turn clothing into self-powered devices. nal patent on the concept of the use of that number is growing as more devices (IEEC file #11310, Science Daily, 8/8/19) intercalation chemistry in high-power feature vocal interaction. (IEEC file density, highly reversible lithium bat- #11303, Binghamton University, 8/15/19) teries — work that provided the basis for subsequent discoveries that now Engineers at the University of Califor- power most laptop computers. (IEEC nia have developed the thinnest optical file #11369?,Binghamton University, device in the world–a waveguide that is 10/11/19) three layers of atoms thin. The work is a proof of concept for scaling down optical devices to sizes that are orders of magni- RECENTRECENT PATENTS PATENTS tude smaller than today’s devices. It could lead to the development of higher den- PCB inspecting apparatus, method sity, higher capacity photonic chips. The ACS Nano researchers have devel- for detecting anomaly in solder paste waveguide consists of a tungsten disul- oped a wearable artificial throat that, (Assignee: Koh Young Technology)- Pub. fide monolayer (made up of one layer of when attached to the neck like a tempo- No- EP3501828 – A printed circuit board tungsten atoms sandwiched between two rary tattoo, can transform throat move- inspection apparatus obtains measure- layers of sulfur atoms) suspended on a ments into sounds. To make their artificial ment shape information about each of a silicon frame. The monolayer is patterned throat, they laser-scribed graphene on a plurality of solder pastes printed on a first with an array of nanosized holes forming thin sheet of polyvinyl alcohol film. The printed circuit board through a plurality a photonic crystal. (IEEC file #11300, flexible device measures 0.6 by 1.2 inch- of apertures and aperture shape informa- Semiconductor Digest, 8/12/19) es. The researchers used water to attach tion about each of the apertures, obtains the film to the skin over a volunteer’s probability values that a first solder paste throat and connected it with electrodes to printed through a first aperture of the plu- MARKETMARKET TRENDS TRENDS a small armband that contained a circuit rality of apertures and each of a plurality board, microcomputer, power amplifier of second solder pastes printed through The embedded memory market has and decoder. In the future, mute people second apertures other than the first aper- the potential to reach $1.2 billion by could be trained to generate signals ture have the measurement shape infor- 2024, growing with a 295% CAGR with their throats that the device would mation when the first solder paste and over this period. MRAM promises life translate into speech. (IEEC file #11293, the plurality of second solder pastes are beyond eFlash. Among various emerging Printed Electronics World, 7/29/19) printed on the first printed circuit board, NVM technologies, spin transfer torque by applying the measurement shape infor- magnetoresistive RAM (STT-MRAM) is The fiber optic sensor market was mation and aperture shape information to gaining significant momentum and poised valued at $1.1 billion in 2015 and expect- a machine-learning based model. meptec.org WINTER 2019 MEPTEC REPORT | 29 TECH BRIEFS

Multi-layer circuit board using inter- and a length and a width of the substrate ent currently drafted) that recently came poser layer and conductive paste.- waveguide is defined by a fence of out of CASP center. More information is (Assignee: Sierra Circuits, Inc.)- Patent ground-stitching vias that short the first available at www.binghamton.edu/casp. No- 10,349,520– A multi-layer circuit layer of metal and the second layer of board is formed by positioning a top sub metal to a plate of the third layer of metal Integrated Electronics Engineering having traces on at least one side to one that forms a back short. Center (IEEC) - The IEEC is a New or more pairs of composite layers, each York Center of Advanced Technology composite layer comprising an interposer Deterioration detection sensor of (CAT) responsible for the advancement layer and a sub layer. Each sub layer is printed wiring board.- (Assignee: of electronics packaging. Its mission is to adjacent to an interposer layer having an FANUC)-Patent No- 16/234111–An provide research into electronics packag- interconnection aperture, the interconnec- object is to provide a deterioration detec- ing to enhance our partner’s products, tion aperture positioned adjacent to inter- tion sensor of a printed wiring board improve reliability and understand why connections having a plated through via in which the accuracy of detection is parts fail. More information is available or pad on each corresponding sub layer. enhanced. A deterioration detection sen- at www.binghamton.edu/ieec Each interposer aperture is filled with a sor of a printed wiring board is a circuit conductive paste, and the stack of top sub board which is vertically provided on a NorthEast Center for Chemical pairs of composite layers are placed into printed wiring board and is soldered to Energy Storage (NECCES) - NECCES a lamination press, the printed wiring board with a soldering Director and Distinguished Professor portion at a lower end. The deteriora- of Chemistry and Materials Science M. Staged via formation from both sides tion detection sensor includes a detection Stanley Whittingham was recognized of chip. - (Assignee: Tessera Inc.) Patent surface for detecting a foreign material. with the Nobel Prize in Chemistry for No- 10,354,942– A method of fabricating The detection surface forms an intersec- development of lithium-ion batteries, a semiconductor assembly can include tion surface which intersects the planar which “have revolutionized our lives” providing a semiconductor element hav- direction of the printed wiring board. and “laid the foundation of a wire- ing a front surface, a rear surface, and a In the deterioration detection sensor as less, fossil fuel-free society.” Whit- plurality of conductive pads, forming at described above, a wiring in the detection tingham won the prize for pioneering least one hole extending at least through surface is broken, and thus the foreign research leading to the development of a respective one of the conductive pads material is detected. the lithium-ion battery along with John by processing applied to the respective B. Goodenough, Virginia H. Cockrell conductive pad from above the front sur- Centennial Chair in Engineering at the face, forming an opening extending from BINGHAMTONBINGHAMTON UNIVERSITY UNIVERSITY University of Texas at Austin and Akira the rear surface at least partially through Yoshino of Meijo University in Japan. “I a thickness of the semiconductor element, BINGHAMTON UNIVERSITY cur- am overcome with gratitude at receiving such that the at least one hole and the rently has research thrusts in healthcare this award, and I honestly have so many opening meet at a location between the / medical electronics; 2.5D/3D packag- people to thank I don’t know where to front and rear surfaces, and forming at ing; power electronics; cybersecure hw/ begin,” said Whittingham. “The research least one conductive element exposed at sw systems; photonics; MEMS; and next I have been involved with for over 30 the rear surface for electrical connection generation networks, computers and com- years has helped advance how we store to an external device. munications. The S3IP Center of Excel- and use energy at a foundational level, lence is an umbrella organization com- and it is my hope that this recognition PCB with substrate integrated wave- prising five constituent research centers. will help to shine a much-needed light on guide transition. (Assignee: Texas More information is available at www. the nation’s energy future.” More infor- Instruments)- Patent No- 20190207286– binghamton.edu/s3ip. mation is available at www.binghamton. In described examples, an integrated edu/necces. waveguide transition includes a substrate Center for Autonomous Solar Power with a waveguide side and an oppos- (CASP) - The CASP center focusses on ing waveguide termination side. A first thin film solar cells and supercapaci- Analytical and Diagnostic Laboratory layer of metal covers a portion of the tors. The recent progress incudes 7.5% (ADL) - The ADL provides an array of waveguide side, a second layer of metal efficiency pure sulfide CZTS solar cell analytical and diagnostic tools located is separated from the first layer of metal without an antireflection coating, and in a single facility to address the needs by a first layer of dielectric, and a third nano-structured transition metal oxide of faculty and industry in understanding layer of metal covers a portion of the supercapacitor with specific capacitance materials, structures and failures that are waveguide termination side and is sepa- of 760 F/g, maximum energy density of found in electronics packaging. The ADL rated from the second layer of metal by 8 Wh/kg, and a power density of 13 KW/ supports the 5 research centers previously a second layer of dielectric. A substrate kg. The CASP team has been invited to mentioned. The facilities of the ADL are waveguide perpendicular to a plane of take part in the Cohort 5 NEXUS-NY available to our industry partners. More the substrate extends from the waveguide program to explore market opportunity information is available at www.bing- side to the waveguide termination side; of a dielectric capacitor technology (pat- hamton.edu/adl ◆

30 | MEPTEC REPORT WINTER 2019 meptec.org

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