Proceedings 20 International Parallel and Distributed Processing
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Mull It Over: Mutation Testing Based on LLVM
Mull it over: mutation testing based on LLVM Alex Denisov Stanislav Pankevich Independent researcher Independent researcher Berlin, Germany Berlin, Germany Email: [email protected] Email: [email protected] Abstract—This paper describes Mull, an open-source tool for framework [4]. It uses two components of LLVM: IR, its low- mutation testing based on the LLVM framework. Mull works level intermediate language, to perform mutations and JIT with LLVM IR, a low-level intermediate representation, to per- for runtime compilation and execution of a tested program form mutations, and uses LLVM JIT for just-in-time compilation. This design choice enables the following two capabilities of Mull: and its mutated counterparts. LLVM IR is also referred to language independence and fine-grained control over compilation as LLVM Bitcode or simply as bitcode. We use these terms and execution of a tested program and its mutations. Mull interchangeably. can work with code written in any programming language that supports compilation to LLVM IR, such as C, C++, Rust, or We consider the following criteria important for a practical Swift. Direct manipulation of LLVM IR allows Mull to do less implementation of mutation testing tool: the tool must be work to generate mutations: only modified fragments of IR code fast, configurable and easy to set up and use. The tool are recompiled, and this results in faster processing of mutated should allow smooth integration with build tools. The tool programs. To our knowledge, no existing mutation testing tool provides these capabilities for compiled programming languages. should be ready for use in mutation testing analysis of real- We describe the algorithm and implementation details of Mull, world production and open source projects. -
A Comparative Survey on Flight Software Frameworks for 'New Space'
https://doi.org/10.5028/jatm.v11.1081 ORIGINAL PAPER xx/xx A Comparative Survey on Flight Software Frameworks for ‘New Space’ Nanosatellite Missions Danilo José Franzim Miranda1,2,*, Maurício Ferreira3, Fabricio Kucinskis1, David McComas4 How to cite Miranda DJF https://orcid.org/0000-0002-9186-1740 Miranda DJF; Ferreira M; Kucinskis F; McComas D (2019) A Ferreira M https://orcid.org/0000-0002-6229-9453 Comparative Survey on Flight Software Frameworks for ‘New Kucinskis F https://orcid.org/0000-0001-6171-761X Space’ Nanosatellite Missions. J Aerosp Technol Manag, 11: e4619. https://doi.org/10.5028/jatm.v11.1081 McComas D https://orcid.org/0000-0002-2545-5015 ABSTRACT: Nanosatellite missions are becoming increasingly popular nowadays, especially because of their reduced cost. Therefore, many organizations are entering the space sector due to the paradigm shift caused by nanosatellites. Despite the reduced size of these spacecrafts, their Flight Software (FSW) complexity is not proportional to the satellite volume, thus creating a great barrier for the entrance of new players on the nanosatellite market. On the other side, there are some available frameworks that can provide mature FSW design approaches, implying in considerable reduction in software project timeframe and cost. This paper presents a comparative survey between six relevant fl ight software frameworks, compared according to commonly required ‘New Space’ criteria, and fi nally points out the most suitable one to the VCUB1 reference nanosatellite mission. KEYWORDS: Flight Software, On-Board Software, NASA cFS, New Space. INTRODUCTION Flight Soft ware (FSW) is soft ware that runs on a processor embedded in a spacecraft ’s avionics. -
Avs Developer's Guide
333333333 3333 AVS DEVELOPER'S 333333333333GUIDE Release 4 May, 1992 Advanced Visual Systems Inc.33333333 Part Number: 320-0013-02, Rev B NOTICE This document, and the software and other products described or referenced in it, are con®dential and proprietary products of Advanced Visual Systems Inc. (AVS Inc.) or its licensors. They are provided under, and are subject to, the terms and conditions of a written license agreement between AVS Inc. and its customer, and may not be transferred, disclosed or otherwise provided to third parties, unless otherwise permitted by that agreement. NO REPRESENTATION OR OTHER AFFIRMATION OF FACT CONTAINED IN THIS DOCUMENT, INCLUDING WITHOUT LIMITATION STATEMENTS REGARDING CAPACITY, PERFORMANCE, OR SUITABILITY FOR USE OF SOFTWARE DESCRIBED HEREIN, SHALL BE DEEMED TO BE A WARRANTY BY AVS INC. FOR ANY PURPOSE OR GIVE RISE TO ANY LIABILITY OF AVS INC. WHATSOEVER. AVS INC. MAKES NO WARRANTY OF ANY KIND IN OR WITH REGARD TO THIS DOCUMENT, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. AVS INC. SHALL NOT BE RESPONSIBLE FOR ANY ERRORS THAT MAY APPEAR IN THIS DOCUMENT AND SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION INCIDENTAL, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF OR RELATED TO THIS DOCUMENT OR THE INFORMATION CONTAINED IN IT, EVEN IF AVS INC. HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. The speci®cations and other information contained in this document for some purposes may not be complete, current or correct, and are subject to change without notice. The reader should consult AVS Inc. -
IRIS Performer™ Programmer's Guide
IRIS Performer™ Programmer’s Guide Document Number 007-1680-030 CONTRIBUTORS Edited by Steven Hiatt Illustrated by Dany Galgani Production by Derrald Vogt Engineering contributions by Sharon Clay, Brad Grantham, Don Hatch, Jim Helman, Michael Jones, Martin McDonald, John Rohlf, Allan Schaffer, Chris Tanner, and Jenny Zhao © Copyright 1995, Silicon Graphics, Inc.— All Rights Reserved This document contains proprietary and confidential information of Silicon Graphics, Inc. The contents of this document may not be disclosed to third parties, copied, or duplicated in any form, in whole or in part, without the prior written permission of Silicon Graphics, Inc. RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure of the technical data contained in this document by the Government is subject to restrictions as set forth in subdivision (c) (1) (ii) of the Rights in Technical Data and Computer Software clause at DFARS 52.227-7013 and/ or in similar or successor clauses in the FAR, or in the DOD or NASA FAR Supplement. Unpublished rights reserved under the Copyright Laws of the United States. Contractor/manufacturer is Silicon Graphics, Inc., 2011 N. Shoreline Blvd., Mountain View, CA 94039-7311. Indigo, IRIS, OpenGL, Silicon Graphics, and the Silicon Graphics logo are registered trademarks and Crimson, Elan Graphics, Geometry Pipeline, ImageVision Library, Indigo Elan, Indigo2, Indy, IRIS GL, IRIS Graphics Library, IRIS Indigo, IRIS InSight, IRIS Inventor, IRIS Performer, IRIX, Onyx, Personal IRIS, Power Series, RealityEngine, RealityEngine2, and Showcase are trademarks of Silicon Graphics, Inc. AutoCAD is a registered trademark of Autodesk, Inc. X Window System is a trademark of Massachusetts Institute of Technology. -
Integrated Solution for Rapid Development of Complex Gnc Software
INTEGRATED SOLUTION FOR RAPID DEVELOPMENT OF COMPLEX GNC SOFTWARE Jean-Sébastien Ardaens (1), Gabriella Gaias (2) (1) German Space Operations Center (DLR/GSOC), 82234 Wessling, Germany, [email protected] (2) German Space Operations Center (DLR/GSOC), 82234 Wessling, Germany, [email protected] ABSTRACT low altitude (500km) with very different ballistic coefficients, it has to be avoided to fix problems - which The paper describes the integrated software solution could have been detected before - after establishing the retained for the design and development of the formation because of the high propellant cost required AVANTI experiment, a challenging on-board to maintain the formation. autonomous formation-flying endeavour to be After a brief description of the envisioned experiment, conducted in 2016. This solution aims at enabling rapid the paper proposes some ideas to reduce the prototyping by providing a powerful development, development and validation efforts of such a GNC validation and testing environment, able to support experiment while ensuring a smooth integration in the simultaneously the design and validation of novel satellite bus to augment the chance of successful Guidance, Navigation and Control algorithms, the completion of the experiment. definition and documentation of the interfaces with the ground segment, the implementation of the onboard 2. OVERVIEW software using space quality standards, the integration into an existing satellite bus and all related testing 2.1. The AVANTI Experiment activities. As mentioned in the introduction, AVANTI will 1. INTRODUCTION demonstrate the capability to perform rendezvous and receding approaches with respect to a noncooperative The possibility to conduct a spaceborne experiment is a client satellite making use of vision-based angles-only rare and precious opportunity that has to be taken even measurements. -
Source Code Verification for Embedded Systems Using Prolog
Source Code Verification for Embedded Systems using Prolog Frank Flederer Ludwig Ostermayer University of Wuerzburg University of Wuerzburg Aerospace Information Technology Knowledge-based Systems [email protected] [email protected] Dietmar Seipel Sergio Montenegro University of Wuerzburg University of Wuerzburg Knowledge-based Systems Aerospace Information Technology [email protected] [email protected] System relevant embedded software needs to be reliable and, therefore, well tested, especially for aerospace systems. A common technique to verify programs is the analysis of their abstract syntax tree (AST). Tree structures can be elegantly analyzed with the logic programming language Prolog. Moreover, Prolog offers further advantages for a thorough analysis: On the one hand, it natively provides versatile options to efficiently process tree or graph data structures. On the other hand, Prolog’s non-determinism and backtracking eases tests of different variations of the program flow without big effort. A rule-based approach with Prolog allows to characterize the verification goals in a concise and declarative way. In this paper, we describe our approach to verify the source code of a flash file system with the help of Prolog. The flash file system is written in C++ and has been developed particularly for the use in satellites. We transform a given abstract syntax tree of C++ source code into Prolog facts and derive the call graph and the execution sequence (tree), which then are further tested against verification goals. The different program flow branching due to control structures is derived by backtracking as subtrees of the full execution sequence. -
Software Evolution from TET-1 to Eu:CROPIS
Software Evolution from TET-1 to Eu:CROPIS Olaf Maibaum (1), Ansgar Heidecker (2) (1) German Aerospace Center (DLR), Simulation and Software Technology, Lilienthalplatz 7, 38108 Braunschweig, Germany (2) German Aerospace Center (DLR), Institute of Space Systems, Robert Hooke Str. 7, 28359 Bremen, Germany ABSTRACT The base of the Eu:CROPIS (Euglena Combined Regenerative Organic food Production In Space) Attitude and Orbit Control System (AOCS) is the three layer AOCS software architecture of the TET-1 satellite (Technology demonstrator). Because of different AOCS requirements between TET-1 and Eu:CROPIS, a software reuse is only possible for software components in the interface layer. In the other two architecture layers, the software components have to be replaced by new implementations to fulfil the changed requirements of the Eu:CROPIS mission. In contrast to the former software evolution from BIRD (Bispectral Infra-Red Detection) to the TET-1 AOCS, the software evolu- tion is forced in Eu:CROPIS by the reuse of software design principals applied in TET- 1. This enables the change of the underlying scheduling mechanisms from a fixed-time approach to a more reactive software behavior presented in this paper. 1. INTRODUCTION The reactive scheduling mechanism used in the Eu:CROPIS AOCS is a result from ex- periences made in the BIRD mission [7]. This mechanism, named “Tasking Frame- work”, resolves one weakness in the BIRD and TET-1 AOCS software [8]: the scant timing for the control torque computation. The Tasking Framework is the core element in the runtime system development of DLR’s OBC-NG (Onboard Computer – Next Generation) project [5], which will provide a distributed onboard computer platform for reconfigurable and high redundant systems. -
Overview of Recent Supercomputers
Overview of recent supercomputers Aad J. van der Steen high-performance Computing Group Utrecht University P.O. Box 80195 3508 TD Utrecht The Netherlands [email protected] www.phys.uu.nl/~steen NCF/Utrecht University July 2007 Abstract In this report we give an overview of high-performance computers which are currently available or will become available within a short time frame from vendors; no attempt is made to list all machines that are still in the development phase. The machines are described according to their macro-architectural class. Shared and distributed-memory SIMD an MIMD machines are discerned. The information about each machine is kept as compact as possible. Moreover, no attempt is made to quote price information as this is often even more elusive than the performance of a system. In addition, some general information about high-performance computer architectures and the various processors and communication networks employed in these systems is given in order to better appreciate the systems information given in this report. This document reflects the technical state of the supercomputer arena as accurately as possible. However, the author nor NCF take any responsibility for errors or mistakes in this document. We encourage anyone who has comments or remarks on the contents to inform us, so we can improve this report. NCF, the National Computing Facilities Foundation, supports and furthers the advancement of tech- nical and scientific research with and into advanced computing facilities and prepares for the Netherlands national supercomputing policy. Advanced computing facilities are multi-processor vectorcomputers, mas- sively parallel computing systems of various architectures and concepts and advanced networking facilities. -
Performance Optimization Strategies for Transactional Memory Applications
Performance Optimization Strategies for Transactional Memory Applications zur Erlangung des akademischen Grades eines Doktors der Ingenieurwissenschaften von der Fakultät für Informatik des Karlsruher Instituts für Technologie (KIT) genehmigte Dissertation von Martin Otto Schindewolf aus Eschwege Tag der mündlichen Prüfung: 19. April 2013 Erster Gutachter: Prof. Dr. Wolfgang Karl Zweiter Gutachter: Prof. Dr. Albert Cohen KIT – Universität des Landes Baden-Württemberg und nationales Forschungszentrum der Helmholtz-Gesellschaft www.kit.edu Ich versichere hiermit wahrheitsgemäß, die Arbeit bis auf die dem Aufgabensteller bereits bekannte Hilfe selbständig angefertigt, alle benutzten Hilfsmittel vollständig und genau angegeben und alles kenntlich gemacht zu haben, was aus Arbeiten anderer unverändert oder mit Abänderung entnommen wurde. Karlsruhe, den 4. März 2013 Martin Schindewolf Abstract Transactional Memory (TM) has been proposed as an architectural extension to enable lock-free data structures. With the ubiquity of multi-core systems, the idea of TM gains new momentum. The motivation for the invention of TM was to simplify the synchronization of parallel threads in a shared memory system. TM features optimistic concurrency as opposed to the pessimistic concurrency with traditional locking. This optimistic approach lets two transactions execute in parallel and assumes that there is no data race. In case of a data race, e.g., both transactions write to the same address, this conflict must be detected and resolved. Therefore a TM run time system monitors shared memory accesses inside transactions. These TM systems can be implemented in software (STM), hardware (HTM) or as a hybrid combination of both. Most of the research in TM focuses on language extensions, compiler support, and the optimization of algorithmic details of TM systems. -
Mutation Analysis for Cyber-Physical Systems: Scalable Solutions and Results in the Space Domain
ACCEPTED FOR PUBLICATION ON IEEE TRANSACTIONS ON SOFTWARE ENGINEERING 1 Mutation Analysis for Cyber-Physical Systems: Scalable Solutions and Results in the Space Domain Oscar Cornejo, Fabrizio Pastore, Member, IEEE, and Lionel C. Briand, Fellow, IEEE Abstract—On-board embedded software developed for spaceflight systems (space software) must adhere to stringent software quality assurance procedures. For example, verification and validation activities are typically performed and assessed by third party organizations. To further minimize the risk of human mistakes, space agencies, such as the European Space Agency (ESA), are looking for automated solutions for the assessment of software testing activities, which play a crucial role in this context. Though space software is our focus here, it should be noted that such software shares the above considerations, to a large extent, with embedded software in many other types of cyber-physical systems. Over the years, mutation analysis has shown to be a promising solution for the automated assessment of test suites; it consists of measuring the quality of a test suite in terms of the percentage of injected faults leading to a test failure. A number of optimization techniques, addressing scalability and accuracy problems, have been proposed to facilitate the industrial adoption of mutation analysis. However, to date, two major problems prevent space agencies from enforcing mutation analysis in space software development. First, there is uncertainty regarding the feasibility of applying mutation analysis optimization techniques in their context. Second, most of the existing techniques either can break the real-time requirements common in embedded software or cannot be applied when the software is tested in Software Validation Facilities, including CPU emulators and sensor simulators. -
AVS on UNIX WORKSTATIONS INSTALLATION/ RELEASE NOTES
_________ ____ AVS on UNIX WORKSTATIONS INSTALLATION/ RELEASE NOTES ____________ Release 5.5 Final (50.86 / 50.88) November, 1999 Advanced Visual Systems Inc.________ Part Number: 330-0120-02 Rev L NOTICE This document, and the software and other products described or referenced in it, are con®dential and proprietary products of Advanced Visual Systems Inc. or its licensors. They are provided under, and are subject to, the terms and conditions of a written license agreement between Advanced Visual Systems and its customer, and may not be transferred, disclosed or otherwise provided to third parties, unless oth- erwise permitted by that agreement. NO REPRESENTATION OR OTHER AFFIRMATION OF FACT CONTAINED IN THIS DOCUMENT, INCLUDING WITHOUT LIMITATION STATEMENTS REGARDING CAPACITY, PERFORMANCE, OR SUI- TABILITY FOR USE OF SOFTWARE DESCRIBED HEREIN, SHALL BE DEEMED TO BE A WARRANTY BY ADVANCED VISUAL SYSTEMS FOR ANY PURPOSE OR GIVE RISE TO ANY LIABILITY OF ADVANCED VISUAL SYSTEMS WHATSOEVER. ADVANCED VISUAL SYSTEMS MAKES NO WAR- RANTY OF ANY KIND IN OR WITH REGARD TO THIS DOCUMENT, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PUR- POSE. ADVANCED VISUAL SYSTEMS SHALL NOT BE RESPONSIBLE FOR ANY ERRORS THAT MAY APPEAR IN THIS DOCUMENT AND SHALL NOT BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMI- TATION INCIDENTAL, INDIRECT, SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF OR RELATED TO THIS DOCUMENT OR THE INFORMATION CONTAINED IN IT, EVEN IF ADVANCED VISUAL SYSTEMS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. The speci®cations and other information contained in this document for some purposes may not be com- plete, current or correct, and are subject to change without notice. -
Design and Implementation of Multi-Core Support for an Embedded Real-Time Operating System for Space Applications
Design and Implementation of Multi-core Support for an Embedded Real-time Operating System for Space Applications Master of Science Thesis KTH Royal Institute of Technology Author: Wei Zhang, KTH, Sweden Supervisor: Ting Peng, DLR, Germany Examiner: Assoc. Prof. Ingo Sander, KTH, Sweden Abstract Nowadays, multi-core processors are widely used in embedded applications due to the advantages of higher performance and lower power consumption. However, the complexity of multi-core architectures makes it a considerably challenging task to extend a single-core version of a real-time operating system to support multi-core platform. This thesis documents the process of design and implementation of a multi-core version of RODOS - an embedded real-time operating system developed by German Aerospace Center and the University of Würzburg - on a dual-core platform. Two possible models are proposed: Symmetric Multiprocessing and Asymmetric Multi- processing. In order to prevent the collision of the global components initialization, a new multi-core boot loader is created to allow that each core boots up in a proper manner. A working version of multi-core RODOS is implemented that has an ability to run tasks on a multi-core platform. Several test cases are applied and verified that the performance on the multi-core version of RODOS achieves around 180% improved than the same tasks running on the original RODOS. Deadlock free communication and synchronization APIs are provided to let parallel applications share data and messages in a safe manner. Key words: real-time operating system, multi-core architecture, embedded sys- tem Acknowledgment This thesis is dedicated to my parents whose support and help over the years let me study abroad and pursue my dream.