Nvcool: When Non-Volatile Caches Meet Cold Boot Attacks*
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NVCool: When Non-Volatile Caches Meet Cold Boot Attacks* Xiang Pan∗, Anys Bachay, Spencer Rudolph∗, Li Zhou∗, Yinqian Zhang∗, Radu Teodorescu∗ ∗The Ohio State University fpanxi, rudolph, zholi, yinqian, [email protected] yUniversity of Michigan [email protected] Abstract—Non-volatile memories (NVMs) are expected to re- Despite all their expected benefits, non-volatile memories place traditional DRAM and SRAM for both off-chip and on- will also introduce new security vulnerabilities as data stored chip storage. It is therefore crucial to understand their security in these memories will persist even after being powered-off. vulnerabilities before they are deployed widely. This paper shows that NVM caches are vulnerable to so-called “cold boot” In particular, non-volatile memory is especially vulnerable attacks, which involve physical access to the processor’s cache. to “cold boot” attacks. Cold boot attacks, as first proposed SRAM caches have generally been assumed invulnerable to cold by Halderman et al. [13], use a cooling agent to lower the boot attacks, because SRAM data is only persistent for a few temperature of DRAM chips before physically removing them milliseconds even at cold temperatures. from the targeted system. Electrical characteristics of DRAM Our study explores cold boot attacks on NVM caches and capacitors at very low temperatures cause data to persist in the defenses against them. In particular, this paper demonstrates that hard disk encryption keys can be extracted from the NVM cache chips for a few minutes even in the absence of power. This in multiple attack scenarios. We demonstrate a reproducible allows the attacker to plug the chips into a different machine attack with very high probability of success. This paper also and scan the memory image in an attempt to extract secret proposes an effective software-based countermeasure that can information. When the memory is implemented using NVM, completely eliminate the vulnerability of NVM caches to cold the cold boot attacks become much simpler and more likely boot attacks with a reasonable performance overhead. to succeed, because data persists through power cycles. To protect against cold boot attacks on main memory, I. INTRODUCTION one approach is to encrypt sensitive data [14]–[21]. Another Non-volatile memory (NVM) such as Spin-Transfer Torque approach is to keep secret keys stored in SRAM-based CPU Random Access Memory (STT-RAM), Phase Change Memory registers, caches, and other internal storage during system ex- (PCM), and Resistive Random Access Memory (ReRAM), ecution [22]–[31]. The rationale behind this design philosophy is a promising candidate for replacing traditional DRAM is that cold boot attacks against on-chip SRAM structures and SRAM memories for both off-chip and on-chip storage are deemed to be extremely difficult. This is because SRAM [1]. NVMs in general have several desirable characteristics data persistence at cold temperatures is limited to a few including non-volatility, high density, better scalability at small milliseconds [32]. feature sizes, and low leakage power [2]–[4]. Prior work has The security implications of implementing the main mem- examined the performance, energy, and reliability implications ory and microprocessor caches with NVM have received little of NVM register files, caches, and main memories [2]–[8]. attention. While memory encryption schemes are feasible, The semiconductor industry is investing heavily in NVM cache encryption is not practical due to low access latency technologies and companies such as Everspin [9] and Crossbar requirements. Cold boot attacks on unencrypted NVM caches [10] are focused exclusively on NVM technologies and have will be a serious concern in practice, especially given the produced NVM chips that are being sold today. A joint effort ubiquity of smart mobile and Internet of Things (IoT) devices, from Intel and Micron has yielded 3D XPoint [11], a new which are more exposed to physical tampering — a typical generation of NVM devices with very low access latency and setup for cold boot attacks. high endurance, expected to come to the market this year. This work examines the security vulnerabilities of micro- Hewlett Packard Enterprise’s ongoing “The Machine” project processors with NVM caches. In particular, we show that [12] is also set to release computers equipped with memristor encryption keys can be retrieved from NVM caches if an technology (also known as ReRAM) as part of enabling attacker gains physical access to the device. Since removing highly scalable memory subsystems. The industry expects non- the processor from a system no longer erases on-chip mem- volatile memory to replace DRAM off-chip storage in the near ory content, sensitive information can be leaked. This paper future, and SRAM on-chip storage in the medium term. demonstrates that AES disk encryption keys can be identified in the NVM caches of a simulated ARM-based system running This work was supported in part by the National Science Foundation under the Ubuntu Linux OS. grants CCF-1253933 and CCF-1629392, and The Ohio Supercomputer Center. We have examined multiple attack scenarios to evaluate the probability of a successful attack depending on the system activity, attack timing, and methodology. In order to search for AES keys in cache images, we adopted the key search algorithm presented in [13] for main memories, and made the necessary modifications to target caches which cover non- Fig. 1: AES-128 key schedule with details on key expansion. contiguous subsets of the memory space. We find that the probability of identifying an intact AES key if the processor is stopped at any random point during execution ranges between following subkeys (also known as round keys) are computed 5% and 100%, depending on the workload and cache size. We from the previously generated subkeys using publicly known also demonstrate a reproducible attack with 100% probability functions such as Rot-Word, Sub-Word, Rcon, EK, and K of success for the system we study. defined in the key expansion algorithm [34]. In each round To counter such threats, this paper proposes an effective of the key generation, the same sequence of functions will be software-based countermeasure. We patch the Linux kernel to executed. Each newly generated subkey will have the same allocate sensitive information into designated memory pages size, e.g. 16 bytes in AES-128. This process repeats a certain that we mark as uncacheable in their page table entries number of rounds (e.g. 10 rounds in AES-128) until the (PTEs). This way secret information will never be loaded expanded key is completely generated. Each subkey from the into vulnerable NVM caches but only stored in main memory expanded key will then be used in separate rounds of AES and/or hard disk, which can be encrypted with a reasonable encryption or decryption algorithms. performance cost. The performance overhead of this coun- termeasure ranges between 2% and 45% depending on the B. ARM’s Cryptographic Acceleration hardware configuration. Many of today’s processors include vectorization support in Overall, this paper makes the following main contributions: the form of Single Instruction Multiple Data (SIMD) engines. • The first work to examine cold boot attacks on non- In ARM processors, the SIMD engine, called NEON, consists volatile caches. of 32 128-bit registers (v0 - v31). Each NEON register can • Two types of cold boot attacks have been performed and conveniently load a 128-bit AES key or a full round of the shown to be effective on non-volatile caches. AES key schedule into a single register obviating the need • A software-based countermeasure has been developed for multiple accesses to the cache or the memory subsystem. and proven to be effective. In addition, ARMv8 introduces cryptographic extensions that • An algorithm for identifying AES keys in cache images include new instructions that can be used in conjunction with has been implemented. NEON for AES, SHA1, and SHA2-256 algorithms. In the AESD The rest of this paper is organized as follows: Section II case of AES, the available instructions are: for single AESE AESIMC provides background information and discusses related work. round decryption, for single round encryption, VMULL Section III explains the threat model. Section IV illustrates for inverse mix columns, and for polynomial multiply our cache-based AES key search algorithm. Section V de- long. In this paper, we explore the use of the NEON engine, scribes our experimental methodology. Section VI presents in addition to the ARMv8 cryptographic extensions. and evaluates two types of cold boot attacks. Section VII C. Cold Boot Attacks and Defenses presents countermeasures and evaluates their effectiveness and performance overhead. Finally, section VIII concludes. The idea of cold boot attacks in modern systems was first explored by Halderman et al. [13]. Their work consisted of II. BACKGROUND AND RELATED WORK extracting disk encryption keys using information present in In this section we provide some background information main memory (DRAM) images preserved from a laptop. The relevant to our study and discuss related work in the context idea of this type of attack builds on the premise that under low of cold boot attacks. temperature conditions, DRAM chips preserve their content for extended time durations. The attack also relies on the A. Advanced Encryption Standard (AES) fact that AES keys can be inferred by examining relationships The Advanced Encryption Standard (AES) [33] is a sym- between subkeys that involve computing the hamming distance metric block cipher that encrypts or decrypts a block of 16 information. The AES key search algorithm has been proposed bytes of data at a time. Both encryption and decryption use the in [13] as well. Muller et al. [35] later expanded cold boot same secret key. The commonly used AES key size is either attacks to mobile devices. When volatile memories such as 128-bit (AES-128), 192-bit (AES-192), or 256-bit (AES-256).