UNIVERSITY of CALGARY LNA and Mixer Designs for RF Front-Ends By

UNIVERSITY OF CALGARY

LNA and Mixer Designs for RF Front-Ends

Roghoyeh Salmeh

A THESIS SUBMITTED TO THE FACULTY OF GRADUATE STUDIES IN

PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

CALGARY, ALBERTA

June, 2007

Abstract

In this thesis, possible LNA and mixer circuits suitable for RF front-ends of wireless receivers with direct conversion modulation are proposed. The main objectives in each design were optimized power consumption, small chip area and low supply voltage.

A single LNA capable of providing a wide band power gain without using extra inductor was proposed in this thesis. The proposed LNA can save area and design effort, compared with LNAs with double tanks or RF front-ends with two cascaded LNAs. The bipolar wide band LNA is introduced as a RF front-end block for IEEE 802.11a standard. This LNA features a power gain of 11.13 dB, a high reverse isolation of -38.47 dB and is suitable for receivers with direct conversion modulation.

For a flexible LNA design to be accepted in industry, it is desirable to include the ESD diodes, pads, layout and package parasitics. This thesis also examines the impact of these parasitics on the gain and noise figure of a cascode CMOS LNA. A CMOS LNA integrated circuit is developed based on this analysis for GPS applications.

Two mixers were designed and developed for integrated receiver RF front-ends. The first mixer is an ultra-low power active bulk driven mixer. The presented mixer in this work is an excellent candidate for RF front-ends with low supply voltage for Bluetooth applications. Because it occupies a small area of 0.0225 mm2 on chip and has a wide band IF output, this mixer is suitable for many integrated receivers that require IF output in range of 500 kHz- 100 MHz.

This research also presents a novel active double balanced mixer using a combination of active load and current bleeding to achieve high conversion gain of 22 dB and low noise figure of 8.5 dB. The implemented CMOS double balanced mixer is introduced as a RF front-end block for GPS applications.

iii Acknowledgements

This thesis would not have been possible without the aid of many individuals who helped me get through the research and write-up. They helped me with all the different aspects from the start through the end.

First and foremost, I am indebted to my supervisors Dr. Brent Maundy and Dr. Ronald Johnston for overseeing this work. I thank them for their excellent insights into how to get things done, for their patience and helpful guidance and the long hours helping with editing this thesis. I also thank them for their non-stop support and always being available.

I also would like to thank Dr. John McRory for teaching me the basics of microwave engineering and RF design. I thank him for his support at the University of Calgary and Calgary TRLabs. I also gratefully acknowledge the financial support of TRLabs.

Without my colleagues, Adam, Albert, Chul, Danny and Zabih at SiRF Technology Inc., who patiently answered my questions and provided endless constructive feedbacks, this thesis could not be finished. I especially thank Dr. Majid Hashemi, my manager at SiRF. I have never worked with anybody who has as much intuition about physics of the transistors as he does.

I also would like to acknowledge and thank the Canadian Microelectronics Corpora- tion for paying and providing the design tools, software and the fabrication of several ICs that are part of this thesis.

I gratefully acknowledge the financial supports of the Department of Electrical and Computer Engineering of University of Calgary and NSERC.

iv I thank Ella Gee and the administration staff at the Department of Electrical and Com- puter Engineering of University of Calgary for their administration support. Thanks also to Jonathan Eskritt and Josh Nakaska for keeping the ATIPS lab working.

Niloufar and Nick, you have been incredibly supportive of me. I could not ask for better children. I greatly appreciate you supporting me when I was away working in SiRF. You gave me the courage to go on. Thanks for being very patient and understanding. Your love and every day smile made the completion of this work much easier.

Finally, I would like to thank my husband Mohammad for always being there for me. In the past 20 years, you were always stood by me, supported my decisions and never lost faith in me. I am very lucky to have you. I am looking forward to all the support you will give me in the many projects in the years to come and hope that I can be as supportive of you in your endeavors.

v To my future: my daughter, my Morning Glory, Niloufar

and my son, my Good Man, Nick

vi Table of Contents

Table of Content

Approval Page ...... ii

Abstract ...... iii

Acknowledgements ...... iv

Dedication ...... vi

Table of Contents ...... vii

List of Figures ...... xiii

List of Tables ...... xxi

List of Symbols and Abbreviations ...... xxiii

CHAPTER 1 Introduction 1.1 Scope ...... 1 1.2 Problem Overview ...... 1 1.3 Outline of the Dissertation ...... 2

CHAPTER 2 Background and Literature Review 2.1 Commercial Integrated Circuits ...... 8 2.2 Receiver Architectures ...... 10 2.2.1 Classical Super-Heterodyne Architecture ...... 13 2.2.2 Ultra-Low IF Architecture ...... 21

vii Table of Contents

2.2.3 Digital Receiver ...... 23 2.2.4 Direct Conversion Receiver ...... 26 2.3 Direct Conversion Receiver Design Issues ...... 28 2.3.1 I/Q Mismatch ...... 29 2.3.2 DC Offsets ...... 31 2.3.3 Flicker Noise ...... 33 2.3.4 Even-order Distortion ...... 35

CHAPTER 3 System Requirements ...... 39 3.1 The Frequency Range and Spectrum Environment ...... 39 3.2 Commercial Wireless Services ...... 43 3.3 IEEE 802.11 Standard ...... 43 3.4 Receiver Performance ...... 46 3.4.1 Sensitivity ...... 47 3.4.2 Dynamic Range ...... 48 3.4.3 Selectivity ...... 52 3.4.4 Fidelity ...... 54 3.5 Direct Down Conversion Receiver Requirements ...... 55

CHAPTER 4 Integrated RF Front-End Design Options ...... 60 4.1 RF Front-End ...... 61 4.1.1 RF Front-End Architectures ...... 61 4.1.2 RF Front-End Building Blocks and Characteristics .. 62 4.2 RF Front-End Selection for Homodyne Architecture ...... 63 4.3 RF Front-End Selection for Low Voltage and Low Power Applications ...... 68

viii Table of Contents

4.3.1 Power Consumption and Dynamic Range ...... 69 4.3.2 Power Consumption and Frequency Range ...... 71 4.3.3 Power Consumption and Sensitivity ...... 73 4.3.4 Power Consumption and Antenna Interface ...... 74 4.3.5 Power Consumption and Circuit Designs ...... 75 4.3.6 Power Consumption and IC Technology ...... 76

CHAPTER 5 Integrated Low Noise Amplifier Design ...... 77 5.1 Radio Frequency Low Noise Amplifier ...... 77 5.1.1 CMOS LNAs ...... 79 5.1.2 Bipolar LNAs ...... 87 5.2 LNA’s Stability ...... 92 5.3 Broadband LNA Design ...... 94 5.4 Dual-Band LNA Design ...... 95 5.5 Fully Differential LNA Design ...... 97 5.6 Gain and Noise Optimization Techniques ...... 99 5.6.1 Classical Noise Matching Technique ...... 99 5.6.2 Simultaneous Noise and Input Matching Technique 100 5.6.3 Power Constrained Noise Optimization Technique 101 5.6.4 Power Constrained Simultaneous Noise and Input Matching Technique ...... 102 5.7 Impact of parasitics on the Gain and Noise Figure of a Common Source LNA ...... 103 5.7.1 Effects of the Pads, ESD Diodes and Wire Bonding on the Input Impedance ...... 104 5.7.2 Quad Flat Nonleaded Package Electrical Model 109

ix Table of Contents

5.7.3 Gain and Noise Figure Analysis ...... 111 5.7.4 Simulations ...... 117

CHAPTER 6 Integrated RF Mixer Design ...... 119 6.1 Radio Frequency Down-Conversion Mixer ...... 119 6.1.1 Low Voltage and Low Power Challenges ...... 120 6.1.2 Passive and Active RF Mixers ...... 123 6.1.3 RF Mixer Architectures ...... 124 6.1.4 Bipolar and CMOS RF Mixers ...... 128 6.2 CMOS Gilbert Double Balanced Mixer Gain Optimization 131 6.3 Impact of the Load on the Performance of a Gilbert Double Balanced Mixer ...... 137 6.3.1 Impact of the Load on Gain ...... 138 6.3.2 Impact of the Load on Linearity ...... 141 6.3.3 Impact of the Load on Noise Figure ...... 143 6.4 A Novel Low Power, High Gain and Low Noise Figure RF Mixer ...... 145 6.4.1 Gain ...... 147 6.4.2 Linearity ...... 148 6.4.3 Noise Figure ...... 149

CHAPTER 7 Impedance Matching ...... 152 7.1 Concept of Impedance Matching ...... 152 7.1.1 Input Matching for Maximum Power Transfer .... 155 7.1.2 Input Matching for Minimum Noise Figure ...... 156 7.2 Matching Requirements for the LNA and the Mixer ...... 156

x Table of Contents

7.2.1 Matching Requirement for Mixer’s LO Inputs .... 161 7.3 Impact of Matching on the Wide-Band LNA Design ...... 166

CHAPTER 8 Radio Frequency LNA Implementation ...... 169 8.1 Integration of Wide-Band Bipolar LNA ...... 170 8.1.1 Design and Layout ...... 170 8.1.2 Simulation and Experimental Results ...... 174 8.2 Implementation of Low Power, Low Noise Figure and High Gain CMOS LNA ...... 181 8.2.1 Design and Layout ...... 182 8.2.2 Simulation and Experimental Results ...... 185

CHAPTER 9 Radio Frequency Mixer Implementation ...... 197 9.1 Implementation of Ultra-Low-Power Mixer ...... 198 9.1.1 Design and Layout ...... 198 9.1.2 Simulation and Experimental Results ...... 201 9.2 Implementation of a Novel Low Power ESD Protected Mixer with High Gain and Low Noise Figure ...... 208 9.2.1 Design and Layout ...... 208 9.2.2 Simulation and Measurement Results ...... 213

CHAPTER 10 Conclusions ...... 219 10.1 Design Summary ...... 219 10.2 Future Work ...... 221

xi Table of Contents

References ...... 223

Appendix A ...... 238

xii List of Figures

List of Figures

2.1. Block Diagram of the tuned RF receiver architecture...... 11

2.2. Block diagram of Armstrong’s original receiver...... 13

2.3. Block diagram of the super-heterodyne receiver ...... 14

2.4. The frequency scheme of a super-heterodyne receiver with high IF (a) before down conversion and (b) after down conversion...... 15

2.5. The frequency scheme of a super-heterodyne receiver with low IF...... 16

2.6. Block diagram of a single conversion super-heterodyne receiver...... 17

2.7. Block diagram of a single conversion super-heterodyne receiver with preselect tracking...... 18

2.8. Block diagram of a multiple conversion super-heterodyne receiver...... 19

2.9. Block diagram of a super-heterodyne receiver with Hartley’s image rejection architecture...... 20

2.10. Block diagram of a super-heterodyne receiver with Weaver’s image rejection architecture...... 20

2.11. Block diagram of an ultra-low IF receiver...... 22

2.12. Block diagram of a superheterodyne-like digital receiver...... 23

2.13. Block diagram of a simplified direct conversion digital receiver...... 24

xiii List of Figures

2.14. Block diagram of a direct conversion receiver...... 27

2.15. Self mixing of the LO with LO leakage...... 31

2.16. Self mixing of the signal with RF and interferer leakages...... 32

4.1. Block diagram of a direct conversion receiver...... 62

4.2. Block diagram of a direct conversion receiver with a passive mixer in the front-end...... 64

4.3. Block diagram of a direct conversion receiver with passive mixer and two LNAs. 65

4.4. Block diagram of a dual direct conversion receiver...... 67

4.5. CMOS differential pair...... 70

5.1. Circuit diagram of a common-gate LNA...... 79

5.2. Circuit diagram of an inductively degenerated cascode LNA...... 80

5.3. Small signal equivalent circuit of the input stage of an inductively degenerated cascode LNA...... 82

5.4. Equivalent small signal circuit of input stage of an inductively degenerated common source CMOS LNA...... 84

5.5. Circuit diagram of a common-emitter bipolar LNA...... 88

5.6. Circuit diagram of bipolar transistor noise model...... 89

5.7. Equivalent small signal circuit of the input stage of a common emitter LNA...... 90

xiv List of Figures

5.8. Circuit diagram of a common base LNA...... 92

5.9. Circuit diagram of a dual-band CMOS LNA...... 96

5.10. Circuit diagram of a dual-band cascode LNA with PMOS switches in the load. .. 97

5.11. Circuit diagram of a fully differential cascode LNA...... 98

5.12. Circuit diagram of a common source LNA with ESD diodes and parasitic pad capacitors...... 105

5.13. (a) Circuit diagram of equivalent input circuit of a common source LNA with ESD diodes and pads. (b) Simplified circuit of input of the LNA with ESD diodes and pads...... 106

5.14. Equivalent circuit diagram of the LNA and wire bonds...... 107

5.15. Equivalent input impedance of the LNA with pads, ESD diodes and wire bonds. 108

5.16. Equivalent electrical circuit of the QFN package...... 110

5.17. Input stage of the LNA with ESD diodes, pads, wire bonds and package parasitics...... 111

5.18. Equivalent circuit of input stage of the LNA with noise sources...... 113

6.1. Circuit diagram of the Gilbert double balanced mixer...... 122

6.2. Circuit diagram of a CMOS passive mixer...... 123

6.3. Circuit diagram of a single ended CMOS mixer...... 126

xv List of Figures

6.4. Circuit diagram of a single balanced CMOS mixer...... 127

6.5. (a) CMOS single balanced active mixer, (b) Common emitter bipolar single balanced active mixer...... 129

6.6. CMOS Gilbert Double balanced mixer with current mirror bias circuitry...... 132

6.7. Simulated voltage gain vs. LO amplitude of double balanced mixer of Figure 6.6. 133

6.8. Variation of the voltage gain of a double balanced mixer with LO amplitude. .... 133

6.9. Simulated voltage gain of a double balanced mixer vs gate bias voltage of LO switching transistor...... 134

6.10. Simulated voltage gain vs. gate voltage of RF transistors of a double balanced mixer...... 135

6.11. Simulated voltage gain of a double balanced mixer vs. (a) width of RF transistors and (b) width of LO switches...... 136

6.12. Simulated voltage gain of the mixer vs. bias current IB1...... 137

6.13. A Gilbert double balanced mixer with an active load...... 139

6.14. Simulated I-V characteristic of a NMOS transistor (W=3x10 mm, L=0.12 mm) in ST 90 nm CMOS technology...... 141

6.15. Double balanced mixer with current re-use topology...... 145wide-band

6.16. Circuit diagram of proposed CMOS double balanced mixer with current bleeding and

xvi List of Figures

an active load...... 146

6.17. Circuit diagram of the bulk driven mixer...... 150

7.1. A microwave network showing the incident, reflected and transmitted powers. 153

7.2. Block diagram of a lossless matching network connecting an arbitrary load to a source...... 154

7.3. Simulated real and imaginary parts of the input impedance of a mixer for GPS RF front-end (Schematic view)...... 158

7.4. Post layout simulated real and imaginary parts of the input impedance of a mixer for GPS RF front-end (Extracted view)...... 159

7.5. A CMOS cascode LNA with output capacitor for matching to mixer RF input. 160

7.6. A CMOS cascode LNA with parallel capacitors in the tank and output...... 161

7.7. Routing of the four LO paths from LO poly-phase outputs to the mixer quadrature inputs...... 162

7.8. Simulated image rejection of the mixer from schematic view...... 163

7.9. Post layout simulation of image rejection with R and C extracted...... 164

7.10. Alternative routing of LO outputs to the mixer inputs to compensate for amplitude and phase mismatch...... 165

7.11. Post layout simulation of the image rejection of the mixer with R and C extracted from modified layout...... 165

xvii List of Figures

7.12. Measured S-parameters of a narrow band LNA...... 166

7.13. Measured S-parameters of a wide-band LNA...... 168

8.1. Bipolar LNA circuit design...... 170

8.2. Layout diagram of the wide-band bipolar LNA...... 173

8.3. Simulated narrow band S-parameters of the bipolar LNA...... 174

8.4. Simulated wide-band S-parameters of the bipolar LNA...... 175

8.5. Simulated 1 dB compression point of the bipolar LNA...... 176

8.6. Simulated noise figure of the bipolar LNA...... 176

8.7. Measured S-parameters of the bipolar LNA at room temperature and 2 V supply. 178

8.8. Measured S-parameters of bipolar LNA at room temperature and 3 V supply. 179

8.9. Measured S-parameters of the bipolar LNA at 1 dB compression point at room temperature and 1.8 V supply. The RF input power is equal to -3 dBm...... 181

8.10. Circuit diagram of the CMOS LNA...... 183

8.11. The layout diagram of the CMOS LNA...... 184

8.12. Layout diagram of the CMOS LNA with pads and isolation rings...... 185

8.13. Simulated S-parameters, stability factor and noise figure of the CMOS LNA in room temperature (40oC internally), 1.8 V supply and RF input of -80 dBm in the Typical corner...... 187

xviii List of Figures

8.14. Simulated S-parameters, stability factor and noise figure of the CMOS LNA in room temperature ,(40oC internally) 1.8 V supply and RF input of -80 dBm in the Fast-Fast corner...... 188

8.15. Simulated S-parameters, stability factor and noise figure of the CMOS LNA in room temperature (40oC internally), 1.8 V supply and RF input of -80 dBm in the Slow-Slow corner...... 189

8.16. Simulated 1dB compression point of the CMOS LNA...... 190

8.17. Simulated transient response of the CMOS LNA in RF input level of (a) -80 dBm and (b) -20 dBm...... 191

8.18. Simulated gain (top left), reverse isolation (top right), noise figure (bottom left) and stability factor (bottom right) of the CMOS LNA from Monte Carlo simulation at room temperature (40oC internally), 1.8 V supply and RF input power of -90 dBm. 192

8.19. Measured S-parameters of the CMOS LNA...... 193

9.1. Complete circuit diagram of the bulk-driven mixer...... 198

9.2. Circuit diagram of the test buffer...... 199

9.3. Layout diagram of the mixer and test buffer...... 200

9.4. Simulated input (bottom) and output (top) of the test buffer at 4 MHz input frequency, 1.2 V supply and at room temperature...... 201

9.5. Simulated THD of the test buffer at 1.2 V and large input signal...... 202

9.6. Simulated IF output of the mixer and buffer output at 1.2 V, fRF=2.4 GHz and

xix List of Figures

fLO=2.396 GHz...... 203

9.7. Measured gain/loss of the mixer vs. supply voltage at RF input power of -20 dBm and RF and LO frequencies of 2.4 GHz and 2.396 GHz, respectively...... 203

9.8. Measured gain/loss vs. LO power; A: when the LO signal is applied to the bulk and B: when the LO signal is applied to the gate...... 205

9.9. Measured IF spectrum of the bulk driven mixer at 1.2 V and RF input of -40 dBm. 206

9.10. Measured IF spectrum of the mixer at RF and LO frequencies of 2 GHz and 1.9 GHz, respectively...... 207

9.11. The circuit diagram of the double balanced mixer with LO preamplifier...... 209

9.12. Simulated steady state time domain wave forms of the LO port and LO input vs. port resistance, Right: LO port output, Left: Gate of LO switch...... 210

9.13. Drain currents of the LO switches of Gilbert cell mixer (Figure 6.6). Top: drain current of transistor M3, bottom: drain current of transistor M4...... 212

9.14. The layout diagram of the double balanced mixer core...... 213

9.15. The steady state time domain wave form of the IF output of the proposed double balanced mixer at 1.8 V supply and RF input power of -50 dBm...... 215

9.16. Simulated RF input (top) and IF output (bottom) of the conventional Gilbert cell mixer...... 215

9.17. Simulated noise figure of the proposed double balanced mixer...... 216

9.18. Simulated 1 dB compression point of the mixer...... 216

xx List of Tables

List of Tables

3.1. Frequency ranges of different wireless systems...... 41

3.2. Summary of the first generation analog cellular radio systems...... 42

3.3. Summary of IEEE 802.11 standards...... 46

3.4. Summary of IEEE 802.11a standard...... 56

4.1. Linearity and sensitivity requirements for GSM and Bluetooth systems...... 73

5.1. Typical acceptable characteristics of an LNA...... 78

5.2. Simulated results of gain and noise figure of the LNA of Figure 5.13 without and with pads, ESD diodes, wirebonds and matching circuit parasitics at 1.8 V and 1.5 GHz. 118

6.1. Typical performance parameters of a down conversion mixer...... 120

6.2. Definition of parameters used for gain optimization of a mixer...... 132

8.1. List of Components used in the bipolar LNA and their values. The value for the bipolar transistors represents: (No. of parallel transistors)x(No. of fingers)x Emitter width. 171

8.2. List of the measured parameters of the wide-band bipolar LNA at room temperature and at different supply voltages...... 180

8.3. List of Components used in the CMOS LNA and their values...... 186

8.4. The simulated parameters of the CMOS LNA at room temperature and 1.8 V supply in different corners...... 188 8.5. Comparison of the simulated and measured parameters of the LNA...... 194

8.6. Comparison of recently published CMOS LNAs...... 196

9.1. Summary of measured performance of the bulk driven mixer...... 204

9.2. Summary of the state of the art low voltage/ low power integrated CMOS mixers.208

xxi List of Talbes

9.3. Summary of the simulated and measurement results of the mixer...... 217

9.4. Comparison of proposed mixer performance with other recent works...... 218

xxii List of Symbols and Abbreviations

List of Symbols and Abbreviations

Av Voltage Gain

W Transistor Width

L Transistor Length

µ Electron Mobility

VGS Transistor Gate-Source Voltage

VTH Transistor Threshold Voltage

VDS Transistor Drain-Source Voltage

Veff Transistor Overdrive Voltage = VGS - VTH

IDS Transistor Channel Current

Cox Gate Oxide Capacitor per Unit Area gm Transistor Transconductance gmb Transistor bulk transconductance gdo Transistor output conductance when VDS=0

ω Angular frequency

γ Channel Current Noise Factor

xxiii List of Symbols and Abbreviations

AGC Automatic Gain Control

ADC Analog to Digital Converter

AM Amplitude Modulation

AMPS Advanced Mobile Phone Service

ASIC Application Specific Integrated Circuit

BDR Blocking Dynamic Range

BER Bit Error Rate

BFSK Binary Frequency Shift Keying

BPSK Binary Phase Shift Keying

CNM Classical Noise Matching

DBS Direct Broadcast Satellite

DR Dynamic Range

DSP Digital Signal Processing

ESD Electro-Static Discharge

FCC Federal Communication Commission

FDD Frequency Division Duplex

FM Frequency Modulation

FSK Frequency Shift Keying

GPS Global Positioning System xxiv List of Symbols and Abbreviations

GSM Global System Mobile

IF Intermediate Frequency

IIP Intermodulation Intercept Point

IRR Image Rejection Ratio

LMDS Local Multipoint Distribution Service

LNA Low Noise Amplifier

LO Local Oscillator

NF Noise Figure

MDS Minimum Detectable Signal

OFDM Orthogonal Frequency Division Multiplexing

PCNO Power Constrained Noise Optimization

PCS Personal Communication Service

PCSNIM Power Constrained Simultaneous Noise and Input Matching

PLL Phase Lock Loop

QAM Quadrature Amplitude Modulation

QFN Quad Flat Nonleaded

RF Radio Frequency

RSSI Received Signal Strength Indicator

SAW Surface Acoustic Wave xxv List of Symbols and Abbreviations

SFDR Spurious Free Dynamic Range

SNIM Simultaneous Noise and Input Matching

SNR Signal to Noise Ratio

SOC System On a Chip

TDD Time Division Duplex

TDMA Time Division Multiple Access

VCO Voltage Controlled Oscillator

WLAN Wireless Local Area Network

xxvi Chapter 1. Introduction 1

CHAPTER 1 Introduction

1.1 Scope

The goal of this research is to identify and address problems involved in building complete radio frequency (RF) receivers with direct down conversion architecture in an integrated circuit. To contain the scope of the effort, the research is focused primarily on the receiver front-end design in the 1.5GHz and 5GHz frequency bands and on low cost, low voltage / low power silicon integrated circuit (IC) technologies. The selected frequency spectrum encompasses a wide range of commercially important radio applications such as global positioning system (GPS), BlueTooth (BT) wireless and cellular phones.

1.2 Problem Overview

There are a number of manufacturers that offer a wide range of RFIC products for receiver design. These include low noise amplifiers (LNAs), mixers, voltage controlled oscillators (VCO) and RF filters. However, completely integrated, high performance receivers with direct conversion modulation still do not exist in the market. One of the main challenges facing complete integration of RF receivers with direct conversion architecture has been the high performance front-end design. Advanced IC technologies with small transistor sizes, offer great advantages for digital circuits. Analog blocks such as intermediate frequency (IF) filters and automatic gain control (AGC) also benefit from small transistor Chapter 1. Introduction 2

sizes with high gain. However, the effects of mutual inductors and on-chip transmission line behaviors do not allow the RFIC blocks to benefit so much from technology advantages, which makes the design of these circuits even more challenging. Thus, a major portion of this dissertation is focused on the problem of realizing a high performance, integrated LNA and mixer. An additional obstacle to full integration of the RF receiver with base-band as a system on chip (SoC) is the presence of a common on-chip substrate. The common substrate can transfer the noise from noisy blocks to the front end and significantly effect the performance of the receiver.

Issues surrounding the implementation of the direct conversion receiver are addressed in this dissertation from both a system and a circuit perspective. The problem faced is ulti- mately a circuit problem, so the solution must also come as a circuit solution. However, the degree to which any given circuit approach is successful must be addressed in the larger context of the circuit and its intended function and environment.

A review of works on RFIC receivers in the past shows that the alternative heterodyne architectures have been extensively used. This architecture can, to some extent reduce the impact of the specific problems that direct conversion modulation is facing. But it cannot satisfy the aggressive goals of low power, simplicity and small chip area. This conclusion addressed in Chapter 2, is a major reason for this dissertation.

1.3 Outline of the Dissertation

A statement of scope, an introduction to the problem addressed and an outline of the structure of the dissertation are provided in Chapter 1.

In Chapter 2 the previous works on direct conversion modulation have been studied, with a survey of available receiver architectures both in commercial and research products. Modulation architectures that are used in the available products on the market are Chapter 1. Introduction 3

reviewed. The super-heterodyne modulation scheme is studied and its shortcomings to fulfill the aggressive goals of compact circuitry, low power consumption and simplicity are explained. This material is followed by a comprehensive survey of the literature illustrat- ing the technical challenges involved in direct conversion modulation. Fundamental bounds and practical limits of this modulation technique are then investigated in detail. Technical approaches taken and the level of performance achieved by the researchers working on RFIC receiver front-end are also presented.

Having discussed the current technologies and research effort in Chapter 2, Chapter 3 turns to the issue of receiver system requirements. The subject of system requirements is introduced through the frequency range and spectrum environment that the receiver must operate. The purpose of identifying system requirements in Chapter 3 is to define a level of technical performance that the implemented front-end must provide. The IEEE 802.11 standard is reviewed to make the front-end design commercially viable. Finally, the most important receiver parameters including the noise figure, sensitivity, dynamic range and fidelity are quantified.

Chapter 4 surveys different front-end alternatives, which are available both in commercial and research products. RF front-end building blocks are then identified and challenges of low power and low voltage designs are reviewed. The requirements of each block of the front-end are specified and LNA and mixer architectures suitable for low voltage and low power applications are selected.

Chapter 5 focuses on the circuit level LNA design by examining the receiver front- end alternatives. A historical overview of the LNA development is presented first. Design challenges and practical limits of a low power, low voltage LNA are investigated with emphasis on direct conversion modulation. The bipolar and CMOS LNAs have been compared and advantages and drawbacks of each technology have been reviewed. Chapter 1. Introduction 4

In the discussion of DC offset in Chapter 2, it is demonstrated that DC offsets are considered the most serious problem of direct conversion. This problem arises when a small portion of the local oscillator energy leaks through the mixer and LNA, due to their finite reverse isolation. The cascode architecture is known for having a high reverse isolation. Therefore, in Chapter 5, a common source/emitter with cascode topology is selected as the best choice for the LNA in the front-end.

In Chapter 5, different gain and noise optimization techniques for the LNA are studied in detail, as well. Throughout the gain and noise optimization technique in this chapter, the importance of continuous optimization of the gain and noise figure has been highlighted. Furthermore, the concept of stability in the RF LNA design has been studied. Wide band, dual-band and fully differential LNAs have also been reviewed. Practical considerations regarding layout issues and design for wide band LNAs are explained in detail. Parts of the published work by the author are included in this chapter to provide continuity of discussion and to serve as an introduction of more detailed discussion in the subsequent chapters.

Throughout the study of direct conversion modulation in Chapter 2, the importance of I/Q mismatch, even order distortion and flicker noise is highlighted, setting the stage for the study of the mixer in subsequent chapters. Chapter 6 thus, returns to the investigation of circuit level design issues of active mixers. A historical review of development of active low voltage/ low power mixers is presented first. The impact of the frequency and amplitude of the local oscillator on the mixer performance has been explained. Examples of passive and active mixer designs are reviewed. Then a detailed comparison of bipolar and CMOS mixers with the emphasis on direct conversion modulation is presented.

Advantages and drawbacks of single balanced and double balanced mixers are also reviewed in detail. The issue of I/Q mismatch is investigated and a proposed solution to reduce its affects is introduced. Then the impact of flicker noise is addressed in the overall Chapter 1. Introduction 5

noise figure of the receiver. In the discussion of flicker noise a guideline for the gain and noise figure optimization is presented. The importance of image rejection in the mixers is then reviewed. Practical considerations regarding mixer layout issues are explained in detail.

In Chapter 7 the concept of impedance matching is reviewed. The importance of impedance matching between the LNA and the mixer in the RF input of the mixer is studied. A detailed study of matching requirements for the LNA and the RF front-end in the integrated circuit form is provided.

Chapter 8 describes the designs and performances of two prototype integrated LNAs fabricated in BiCMOS and CMOS technologies. These ICs were implemented to demonstrate the validity of the theoretical predictions in earlier chapters. The first IC includes a Bipolar LNA and contains a common emitter LNA working at 5 GHz. This chip was designed primarily to validate the developed theory for wide band LNAs introduced in Chapter 5. A wide bandwidth of about 3 GHz was achieved from this LNA. The LNA draws 8 mA from 2 V supply and provides a gain of 11.13 dB at 5.3 GHz. The wide band LNA has a 4.25 dB noise figure at 2 V supply. The second LNA is a common source CMOS design implemented in ST 90 nm technology. This LNA consumes 3.8 mA from a 1.8 V supply and achieves a low noise figure of 1.9 dB and provides a power gain of 16 dB in 1.57 GHz.

Chapter 9 presents the designs and performances of the two prototype integrated mixers in CMOS technologies. The first mixer is a bulk driven mixer for ultra low-power and low voltage applications. This mixer draws 0.24 mA from a 1.2 V supply making it a viable alternative for commercially available mixers. The bulk driven mixer provide 2.55 dB power gain at 2.4 GHz RF input. This mixer was targeted to be highly linear and a 1-dB compression point of -6.5 dBm was measured. Chapter 1. Introduction 6

The second mixer is a newly proposed active mixer that draws only 0.6 mA from a 1.8 V supply. This mixer was designed primarily to provide a low noise figure and a high gain. A power gain of 22 dB and a noise figure of 8.5 dB was achieved. A literature survey shows that this mixer has the lowest power consumption for this level of performance.

Finally, Chapter 10 concludes the dissertation with a summary of achieved results and a list of research areas recommended for further investigation. CHAPTER 2. Background and Literature Review 7

CHAPTER 2 Background and Literature Review

This chapter reviews reported works in the area of integrated receiver design. The review is organized into the following main sections:

• Commercial Integrated Circuits

• Receiver Architectures

• Integrated RF Receiver Research

• Direct Conversion Receiver Design Issues

In this chapter, discussion of the works done by other researchers is cited. This is done to provide an introduction for the work covered in subsequent chapters. At first commercial available integrated receiver building blocks are presented. These blocks include LNAs, mixers, intermediate frequency (IF) filters, automatic gain control (AGC) amplifiers, voltage controlled oscillators (VCOs) and phase lock loops (PLLs).

Section 2.2 reviews the research on receiver architectures conducted in the past. Emphasis is placed on the receiver architecture suitable for use in low power applications. The study of alternative receiver architecture provides an overview of receivers that had been designed earlier providing an important historical context. The classical super-heterodyne design and its variations are examined in detail. Next, one of these variations, the ultra low IF architecture that led to the concept of direct conversion modulation is covered. Moreover, digital receivers are reviewed at the end as an alternative to analog receivers. CHAPTER 2. Background and Literature Review 8

The reported designs of wireless RF receivers are reviewed in detail in this Chapter. In these radio receivers, high consumer demands justifies designs for low power and low voltage applications. Thus direct conversion receiver designs become practical from an economical point of view.

Finally, design issues of direct conversion receiver are examined in detail and challenges of RF circuit design for this modulation technique are reviewed. Proposed solutions of other researchers for RF front-end blocks that provide good performance with minimum possible power consumption are examined.

2.1 Commercial Integrated Circuits

A study of commercial wireless products and integrated circuits (ICs) from which they are built, will help out to assess the state of the art of integrated receivers. This study will provide an indication on what is feasible with current manufacturing technologies. In this section an overview of commercial integrated circuit devices at the time of writing this dissertation is presented. In this overview, high volume market commercial circuits are classified into two broad sections:

• Commodity ICs

• Application Specific ICs(ASICs)

Commodity ICs are devices offered for high volume sale by IC manufacturers and are designed to target wide market employment. Commodity ICs often have a system design that is based on building blocks. Information on these devices is widely available in the trade journals and manufacturers new product release data sheets.

ASICs are devices designed for a single application and most of the time have higher levels of integration. Information and specifications of ASIC devices are hard to obtain. These data are often available in research papers or are classified by the manufacturers as internal information and the public is not given access to this data [1]. CHAPTER 2. Background and Literature Review 9

One of the classical predictions of VLSI densities in ICs is known as Moore’s Law. One of the founders of Intel Corporation, Gordon Moore, in 1970 predicted that chip building technology would improve very rapidly. He projected that the number of transistors on a chip would double about every 18 months. After more than 30 years from this prediction, Moore’s law has proved amazingly close to actual trends. Recently a report by iSuppli Corp., Gary Grandbois predicted that semiconductor sales will increase to $255.7 B in 2006, up 7.8 percent from $237.2 B in 2005 [2]. The personal computer (PC) and mobile phone markets are the major drivers of semiconductor sales in the past two years.

The IC technology started to advance in the late 1960s and at the beginning of 1970. In that period large sections of electronic devices (such as a TV) could be economically integrated on a single chip. By late 1970 and early 1980 most of the amplitude modulation (AM) receivers could be implemented on chip. However, still the RF building blocks such as LNAs, mixers and VCOs, the LC tuning tanks, bandpass filters and various coupling and bypass capacitors were off-chip. In the middle of the 1980’s, pagers, cellular and portable phones appeared as new electronic devices. Introduction of these products caused a significant growth in the IC market. However, the LNA, the tuning circuit and IF filter were still implemented off-chip. These new ICs provided the capability of including the mixer, local oscillator, IF amplifier limiter, quadrature detection and a high dynamic range received signal strength indicator (RSSI) on chip. In addition, the supply voltage and current consumption of these devices were lower than that of the first generation ICs, reflect- ing the growing demand for lighter devices and longer battery life time.

One of the highest level of integration of commodity IC was a VHF FM receiver presented by Motorola around 1990. This receiver included the LNA, mixer and the varactor tuning diode on-chip, but still the image rejection filter, channel selection filter and the local oscillator tuning circuit were implemented off-chip with discrete components.

The tuning circuit in the early television receivers was provided by mechanical switching of inductors or in other cases by manually tuned variable capacitors. Today most of the receivers rely on digitally programmable frequency synthesizers. At present, CHAPTER 2. Background and Literature Review 10

state of the art tuners offer precise crystal controllable frequency stability, with enhanced ease of use, extra features and no need for adjustment.

The drawback of implementing part of the receiver off-chip was one of the main reasons that ICs foundries such as IBM, ST, Motorola, Freescale and TSMC started to include these components in their design technologies. Today a wide range of inductors, capacitors and voltage controlled capacitors are available in the advanced design technologies. Economical aspects of the new products and growing demand for smaller size portable devices also pushed the IC manufacturers towards smaller transistor sizes. A few companies such as Intel even started to implement both the RF and base band section of receiver on a single chip as a system on chip (SoC) solution.

2.2 Receiver Architectures

In 1887 Hertz developed the earliest receiver architecture [3]. The main reason of devel- oping this design by Hertz was to validate the existence of radio wave predicted by Max- well in 1854. The Hertz’s receiver operated at a frequency of 31 MHz and consisted of a simple loop of wire cut by a microscopic gap. In 1896 when Marconi demonstrated reception of signals over distances of up to 9 miles, commercial development of radio receivers began. Almost at the same time Sir Oliver Lodge developed the concept of tuned radio receivers and patented it in 1899. Later in the same year Marconi patented similar technology and set the stage for rapid progress in the following years. In Hertz's, Marconi's and Lodge's receivers the selectivity and detection were done by circuits that were operating at the same frequency as the transmitted signal. This type of earlier receiver can be classified as tuned RF architecture. The block diagram of a tuned RF receiver is shown in Figure 2.1. CHAPTER 2. Background and Literature Review 11

RF Amplifier

Signal Detector

Bandpass Filter

FIGURE 2.1. Block Diagram of the tuned RF receiver architecture.

The receivers in tuned RF architecture used amplifiers and cascaded stages of tuned circuits (in the form of high order filters) to improve the sensitivity and selectivity. In a few years after the first generation of receivers were introduced, with advances of communication systems these receivers have reached a high level of sophistication. In addition to the more complex circuit design, these receivers needed highly skilled people to manually adjust the filtering circuits used. These problems, combined with high cost of implementation and production and difficulties of extending the designs to higher frequencies, pushed the development of different alternatives for receiver architecture.

Before studying different architectures of radio receivers, some of their unique problems are described first. In wireless communication essentially an unlimited number of users share different part of the frequency spectrum. Therefore, it is possible that strong signals coexist very close to a very weak signal. An RFIC radio receiver must be able to select the desired signal and reject all of the interferers, by using less than perfect active and passive components.

There are two major problems in the receiver design: image rejection and dynamic range. The receiver must be able to select the desired signal from the array of signals that are occupying the spectrum. In the ideal case, with a bandpass filter, whose centre frequency is set at the desired RF signal and its bandwidth is as wide as a channel, this goal can be achieved. CHAPTER 2. Background and Literature Review 12

In actual implementation such a filter with this small fractional bandwidth does not exist and an RF bandpass filter with center frequency of the desired signal is used. In the RF receivers a surface acoustic wave (SAW) filter is usually used for RF bandpass filtering. This filter may or may not be tunable and will select an array of radio channels close to the desired signal. Therefore, when the signal is translated to the intermediate frequency (IF) another bandpass filter is needed to remove the other preselected signals. The down converted signal after the mixer will occupy an interval greater than 0-IF on the spectrum. Therefore, the IF bandpass filter will select both the desired channel and the image channel that has been translated to -IF by the mixer. The following detector stage of the receiver can not distinguish between the desired signal and the image, thus, its output will be the result of the superposition of both inputs.

However, if the bandwidth of the RF bandpass filter is narrower than 4 times IF, it will attenuate the image signal and the image will not go through the receiver. If high IF is selected for the receiver, design of the RF bandpass filter will be more relaxed, but the down converted signal after mixer will be high frequency. Processing of a high IF needs amplifiers that are not power efficient. It also requires large capacitors which occupy a large area on-chip. In the case of low IF, the design of the RF bandpass filter will be very complex and usually hard to meet the design requirements.

The dynamic range of a receiver is mainly set by the noise figure and the non-linearity of the LNA and first mixer. If the desired RF signal is a weak signal that is surrounded by large interferers, the preselection RF bandpass filter can not stop these undesired signals. After amplification in a receiver’s front-end blocks (LNA and mixer), these large interferers may saturate the following IF circuits and prevent processing of the desired signal. Moreover, these large interferers add to the receiver’s input referred noise and corrupt the signal to noise ratio (SNR) of the receiver.

In addition, as nonlinearities exist in the LNA and mixer some of the products of intermodulation distortions of these large interferers may fall on the desired channel after CHAPTER 2. Background and Literature Review 13

down conversion. These distortions act like noise because the IF filter can not distinguish between these unwanted signals and the desired IF.

2.2.1 Classical Super-Heterodyne Architecture

The concept of heterodying an RF signal to convert it to a lower frequency was developed by Armstrong in 1918 [4]. The original block diagram of Armstrong’s receiver is shown in Figure 2.2. This receiver was intended to allow low frequency radio frequency receivers to be used at the newer HF frequency being adopted in Europe. However, very soon many additional advantages of this basic receiver architecture were recognized.

RF Amplifier Mixer

To Low Frequency Processing

Bandpass Filter

Local Oscillator (LO)

FIGURE 2.2. Block diagram of Armstrong’s original receiver.

It was thought that the super-heterodyne architecture would be the best architecture for receivers because of its high sensitivity, selectivity and additional advantages including:

• Amplification of the input signal can be done at low frequency where it is easier to achieve high gain.

• Amplification is done at two stages and at two different frequencies. Thus, there is less possibility of regenerate feedback and instability. CHAPTER 2. Background and Literature Review 14

• High order and narrow band filters are easier to build in the low frequency than the RF.

• Adjustment of the low frequency IF bandpass filters can be done just once, and after that the tuning can be achieved by varying the heterodyne oscillator frequency.

Today almost 98% of radio receivers use this architecture. The super-heterodyne receivers move the signal energy from the received RF frequency down to IF and then down to the baseband, where demodulation can occur in a series of steps. As shown in Figure 2.3, in a super-heterodyne receiver, the input signal is first amplified at RF in a tuned stage, then down converted by a mixer to a lower intermediate frequency, and substantially amplified in a tuned IF stage containing highly selective passive bandpass filters. The low noise amplifier (LNA) usually uses an inductive load to resonate with the tank capacitor.

LNA Mixer

RF Input IF Signal Broad Channel Select To Low Frequency RF Filter Filter Processing

Local Oscillator (LO)

FIGURE 2.3. Block diagram of the super-heterodyne receiver.

The LNA provides enough gain to overcome the noise of following stages. Channel selection can not be done at RF frequency, because the RF filter can not provide the precise fractional bandwidth for the desired channel. Then, the RF signal is mixed down with the variable frequency local oscillator (LO) to a lower IF. The image signal is removed CHAPTER 2. Background and Literature Review 15

from the signal with an image rejection filter and then, a filter with fixed IF center frequency will select the desired channel.

Although the high selectivity of the super-heterodyne receiver is always one of its strengths, it has limitations for achieving miniature, low power receivers. Wireless receivers must often handle very weak channels existing side by side with very strong interferer channels in the same band. The main issue in the super-heterodyne receiver is the trade-off between image rejection and adjacent channel suppression [5]. If the IF frequency is chosen to be high, as shown in Figure 2.4, the image signal is greatly attenuated whereas nearby interferers remain at high level. On the other hand if the IF frequency is selected to be low, the image corrupts the down converted signal but the adjacent interferers are sup- pressed significantly as illustrated in Figure 2.5.

Desired Channel

Interferer Signal Image Rejection Filter IF Channel Select Filter Image Signal

ω ω ω 0 ω ω 1 im IF

2 ω IF (a) (b)

FIGURE 2.4. The frequency scheme of a super-heterodyne receiver with high IF (a) before down conversion and (b) after down conversion.

Therefore, in addition to being very highly selective the IF filters and amplifiers must also have a wide dynamic range. Having a wide dynamic range provides the ability to remain sensitive to weak signals above or below (in the case of GPS signal) the intrinsic noise level in the passband and also the ability to handle strong signals without interfering with weak signals [6]. CHAPTER 2. Background and Literature Review 16

Desired Channel

Interferer Signal Image Rejection Filter IF Channel Select Filter Image Signal

ω ω ω 0 ω ω 1 im IF

2 ω IF (a) (b)

FIGURE 2.5. The frequency scheme of a super-heterodyne receiver with low IF.

These considerations determine the intermediate frequencies used in radio and television receivers [7]. Many analog cellular phones use a 90 MHz IF while in television a traditional 43.5 MHz is used. Amplification and filtering at these high IF (10-100 MHz) comes at the price of power dissipation. Furthermore, filtering a narrow band signal that is centered at high frequency and is accompanied by large interferers demands high Q’s. Therefore, IF bandpass filters may require a large number of off-chip passive components, which adds to the receiver cost.

2.2.1.1 Single Conversion Technology

The block diagram of a single conversion super-heterodyne receiver architecture is illustrated in Figure 2.6. In this figure, the preselect filter serves both to partially reject the image frequency and attenuate signals outside of the desired frequency band. This filter must have a very low noise figure and low insertion loss to minimize the degradation of the noise figure of the receiver. A low noise amplifier (LNA) that follows the preselection filter, provides enough gain to suppress the noise of the following stages relative to the desired signal and also overcome the losses of passive circuits up to the IF section. The LNA gain is particularly important for the cases where passive mixers are used in the receiver. However, a high gain LNA is desirable to achieve low noise figure performance but to avoid the input dynamic range degradation it must be optimized. CHAPTER 2. Background and Literature Review 17

Optional Amplifier / AGC

LNA IF Mixer

To Low Frequency IF Filter Receiver

Bandpass Filter

FIGURE 2.6. Block diagram of a single conversion super-heterodyne receiver.

Following the LNA, the mixer converts the amplified RF input signal to the selected IF frequency, where additional gain may also be provided. After the mixer an image rejection filter is provided, which suppresses out of band IF frequency signals and also increases the image rejection. Therefore, the image rejection filter further improves the receiver noise figure by attenuating the image frequency generated during the mixing process in the mixer output and translated to the IF spectrum. Thereafter, an amplifier or an automatic gain control (AGC) can be used. IF stage amplification increases the signal strength up to a level that it can be accurately processed by the baseband demodulator stage to recover the original transmitted signal.

The IF band pass filter that follows passes only the desired IF signal. In some applications such as analog frequency modulation (FM) and digital frequency shift keying (FSK) another amplification stage after the IF channel select filter is required. These modulation schemes are typically designed to provide very high gain, therefore the amplifier stage after the IF filter usually acts as a limiting amplifier. For this amplification stage, the intermodulation products are not very important because before this stage all the interferer signals have been attenuated by the image rejection and IF bandpass filters. For other applications with amplitude modulation (AM) and digital phase modulation schemes, CHAPTER 2. Background and Literature Review 18

automatic gain control is usually provided. This is done to retain the amplitude information and minimize the phase distortion.

As shown in Figure 2.3, in a super-heterodyne receiver, the input signal is first amplified at RF in a tuned stage, then down converted by a local oscillator to a lower intermediate frequency, and substantially amplified in a tuned IF stage containing highly selective passive bandpass filters.

2.2.1.2 Multiple Conversion Technology

In the design of super-heterodyne receivers there is a trade-off between selection of IF and LO frequencies and the required IF filter simplicity. If the frequency of the RF input signal is narrowband, then the single conversion topology without requiring a very high order IF filter is sufficient to meet the image rejection requirement. However, if the RF input signal is wide, either a multiple conversion topology or a tracking preselect filter must be used.

Optional Amplifier / AGC

Tunable Bandpass Filter LNA Mixer

IF signal To Low Frequency IF Filter Receiver

Filter Tuning

FIGURE 2.7. Block diagram of a single conversion super-heterodyne receiver with preselect tracking.

If a single conversion topology is used for down conversion of a wide band signal a tracking design shown in Figure 2.7 is needed. The tracking system employs preselection filter with bandwidth smaller than the service band of interest. The disadvantage of this CHAPTER 2. Background and Literature Review 19

scheme is the need for associated tracking between the preselect filter and the local oscillator, and a narrow band tunable RF filter. Both of these requirements are very hard to meet at RF frequencies. That is why historically the preselect tracking approach has been difficult to implement on chip.

The alternative approach to down convert a wide band RF signal to baseband is multiple conversion. In Figure 2.8 the block diagram of a multiple conversion super-heterodyne receiver is illustrated. In this type of receiver, first the incoming RF signal is converted to a relatively high IF, and then to a second lower IF. The advantage of this approach is that, it does not need a tunable preselect RF filter and its associated LO tuning circuits. In this approach narrow channel bandwidths can be handled with lower Q filter design. The disadvantage of multiple conversion is an additional mixer, local oscillator and filter, extra chip area cost, and power consumption. This approach is also more complex to design due to dynamic range performance requirements of all the active blocks ahead of the final IF filter.

Optional Amplifier / AGC

LNA IF Mixer 1 IF Mixer 2

To Low Frequency IF Filter Receiver

Bandpass Filter

LO 1 LO 2

FIGURE 2.8. Block diagram of a multiple conversion super-heterodyne receiver.

2.2.1.3 Receiver with Image Rejection Mixer Some of the IF filter requirements can be relaxed through the use of an image rejection mixer. The block diagrams of Hartley [8] and Weaver [9] super-heterodyne receivers with image rejection mixer are shown in Figure 2.9 and 2.10, respectively. In receivers with CHAPTER 2. Background and Literature Review 20

image rejection mixers, the local oscillator signal is divided into four and the quadrature mixing attenuates the image signal. It has been shown that the outputs at points A and B of Figures 2.9 and 2.10 are in phase at the desired frequency, while for the image frequency they are out of phase, so when they are summed in the output signal the image signal will be cancelled out [10].

Mixer A I I IF Bandpass o LNA 90 Filter Divider 0o

Phase Shifter + Bandpass Processing o 90 Local Oscillator Bandpass Filter IF Bandpass Q Q Filter B Mixer

FIGURE 2.9. Block diagram of a super-heterodyne receiver with Hartley’s image rejection architecture.

Mixer Mixer 2 A I IF Bandpass LNA o Filter o Splitter 0 90 Local Oscillator 2 Phase Shifter Phase Shifter + Bandpass Processing o o 90 Local Oscillator 0 Bandpass Filter IF Bandpass Q Filter Mixer Mixer 2 B

FIGURE 2.10. Block diagram of a super-heterodyne receiver with Weaver’s image rejection architecture.

In theory with precise 90o phase shifts infinite image rejection results. In practice, however, the gain and phase mismatches between the two mixers cause imperfect image rejection, limited to about 30-40 dB depending on whether or not trimming is used [11- CHAPTER 2. Background and Literature Review 21

12]. However, even 30-40 dB of loss of the image signal is enough to decrease the number of poles that is needed for the IF bandpass filter to half.

The image rejection ratio (IRR) has been shown to be [10]

2 11+ ()+ ε – a()θ1 + ε cos() IRR = ------(2.1) 11++()+ ε 2 a()θ1 + ε cos() where a is the LO amplitude, ε represents the relative voltage gain mismatch and θ is the phase imbalance in radians. If an image rejection of 60 dB is required in the receiver, and 30 dB of that is provided by the image rejection mixer, then the order of the IF bandpass filter can be reduced by almost half. For the mixer to achieve 30 dB of image rejection the phase mismatch θ must remain below 5o. In practice, in typical IC technologies achieving the necessary amplitude and phase shift accuracies are difficult. In addition, some of the concerns for mass production of the receiver with this architecture will be the extra power consumption and chip area involved in the use of two mixers.

2.2.2 Ultra-Low IF Architecture

Associated problems with implementing classical super-heterodyne receivers on-chip led the researchers to depart from this architecture. An excellent review of this work is provided by Abidi in [13].

One of the earliest departures from the super-heterodyne architecture was a receiver reported by Kasperkovitx [14] at Phillips research laboratories. The Phillips receiver, TDA 7000, was probably the first IC which had a true “radio-on-a-chip”. TDA 7000 was a FM broadcast receiver using an ultra-low IF frequency of 70 kHz.

As mentioned before in Section 2.2.1, the RF and LO frequency define the IF spectrum. In some special cases the issue of image in the receiver can be reduced without actually attenuating the image signal. This can happen when the LO and RF frequencies CHAPTER 2. Background and Literature Review 22

relationship is such that the image frequency falls within an unused portion of the RF spectrum. The block diagram of an ultra-low IF receiver architecture is illustrated in Fig- ure 2.11.

RF Amplifier IF Mixer

IF Lowpass To Low Frequency Filter Processing

Bandpass Filter

FIGURE 2.11. Block diagram of an ultra-low IF receiver.

In this receiver, the RF frequency fRF is related to the LO frequency fLO as

fLO = fRF + KB (2.2) where B is the channel bandwidth and K is a constant.

Assuming K=1/2, the IF frequency will be fIF=B/2, and channel selectivity can be done with a lowpass filter with cutoff frequency of fc=B. However, this architecture works in a system when the operating frequencies are assigned such that the adjacent channel signals are not occupied. Therefore, the image signal, which falls at the centre of the adjacent channel, will contain no energy and thus, will not interfere with the reception of the desired signal. This basic approach can also be used in systems in which the adjacent channel is occupied but guard bands are also provided. This approach was used in Philip’s FM broadcast receiver, in which no bandpass filter was required [14]. CHAPTER 2. Background and Literature Review 23

The performance of an ultra-low IF receiver depends heavily on the degree to which the image frequency channel is occupied. Therefore, it also depends on system level design and the ability of the transmitters to avoid using or contaminating the neighboring region of the frequency spectrum. In addition, this architecture puts more demand on the final channel selection low-pass filter. The number of poles required in the low-pass filter in this approach is more than twice that needed in an equivalent traditional receiver using bandpass filters with the same final selectivity [14].

2.2.3 Digital Receiver

The concept of an “all digital” receiver design was proposed by researchers as an alternative to analog signal processing limitations and complexity. The block diagram of a super- heterodyne-like design of a digital receiver is shown in Figure 2.12. In this receiver the sampling frequency is above the desired RF frequency and a digital down conversion is used to transfer the signal to a lower IF, or directly to baseband.

In Figure 2.13, the block diagram of a direct conversion digital receiver is illustrated. In this type of receiver, the input RF signal is sampled at the frequency of the desired signal using a quadrature approach.

Lowpass I Decimation Sampler ADC Channel Filters Select Filters Q Lowpass Filter

f clock Digital LO Digital Circuits

FIGURE 2.12. Block diagram of a superheterodyne-like digital receiver. CHAPTER 2. Background and Literature Review 24

In both of the receivers shown in Figures 2.12 and 2.13, the RF signal can be directly sampled, only if the digital local oscillator could produce high precision quadrature outputs. In an all digital receiver the channel selection filters will benefit from the simplicity of digital signal processing and can be realized with very high selectivity. Moreover, adap- tive algorithms can be used to overcome problems such as multipath distortions in the reception path.

Sampler ADC

Decimation Lowpass I Filters Channel Select Lowpass Filter Sampler ADC Filters Q

Digital LO and Phase Shift Digital Circuits

FIGURE 2.13. Block diagram of a simplified direct conversion digital receiver.

Unfortunately, with the current IC technologies, digital sampling of the input signal is not possible. For most wireless applications, sampling directly at the RF frequency requires a sampling rate of at least 900 MHz [13]. In addition, since no narrowband preselect filtering is used, the RF front-end is open to the full spectrum. Thus, for these receivers very high dynamic range is required, which entails a 10 bit or more analog to digital converter (ADC). Sampling the RF GHz range signals with such a precision is very difficult, costly and consumes high power. Even if the problem of ADC design with such a precision is ignored, the data rate and word widths will be too large to allow processing within the acceptable power budget for most portable devices.

To solve these problems, most designers have adopted the use of the “sub-sampling” technique. This technique introduces aliasing which must be removed by very narrow CHAPTER 2. Background and Literature Review 25

band preselect filtering prior to sampling. For example, assume that a sub-sampled direct conversion digital receiver is being considered for an input RF frequency of 10 GHz and the sampling frequency is set at 10 MHz. In such a receiver, aliases of any signals which is spaced by 10 MHz from the desired signal will be present in the baseband processing, where they may interfere with, or prevent reception of the desired signal. This problem can be solved by using a preselect filter with a bandwidth B of much less than 10MHz and an attenuation of more than 60 dB in the stop band. Assuming that a 3 pole bandpass filter is selected, this level of attenuation can only be achieved with a high Q of 500. Therefore, this approach not only does not simplify the design of integrated receiver, but also actually increases the complexity of it by putting more demand on bandpass filter design.

It might be thought that by increasing sampling frequency, the demands on the preselection filter can be removed. However, increasing the sampling frequency requires higher power consumption. Vittoz [15] has developed bounds on the power consumption of digital signal processing (DSP) circuitry (excluding the ADC) for low pass filters as a function of dynamic range requirement. To apply these bounds to bandpass filters, the centre frequency of the filter must be used in the calculation. As an example, a 10 MHz, third order IF filter requires 20 mW, which in a 1.8 V supply voltage, corresponds to 11.1 mA current consumption. Cascading two such filters to improve the channel rejection raises the current consumption to 22.2 mA at 10 MHz. Hence, even without considering the power consumption of the ADC, the DSP is not a suitable solution at frequencies of 10 MHz and above.

While it can be argued that power consumption will decrease for digital signal processing as advanced technologies allow implementation of smaller devices, these improvements will be gradual and will not change the general conclusions reached in this section [15]. Therefore, an analog front-end is the only viable solution for low power and high performance design. The digital demodulation is more properly seen at the final, low IF frequency stages. CHAPTER 2. Background and Literature Review 26

2.2.4 Direct Conversion Receiver

Direct conversion, also called zero-IF was introduced many decades ago, and is the natu- ral approach to down convert a signal from RF to baseband [16]. As early as 1924, radio pioneers had considered use of direct conversion architecture for single vacuum tube receivers. It was only in 1974 that a direct conversion measuring instrument for carrier based telephony was built [17]. In that work for the first time a high order lowpass filter for channel selection was employed.

A few years later in 1980, Vance realized that the FM receivers can be implemented on-chip [18] by taking the idea of low-IF to its minimum limit of zero-IF. Later Phillips pagers benefited from the simplicity of a zero-IF receiver [19]. Owing to the relatively large modulation index, the spectral energy of the RF input signal clusters in two lobes on either side of DC [20]. Thus, for pager receivers the direct conversion is exactly the right solution. In an effort to reduce the chip area and receiver complexity, NEC’s pagers were then transformed from the classical super-heterodyne [21-22] to direct conversion modulation scheme [23]. Other researchers also used the zero-IF scheme to develop similar integrated front-ends [24-25].

In contrast to the multi step down conversion approach of the super-heterodyne receiver, a direct conversion receiver moves the signal energy from the received RF frequency down to the baseband in a single step [26]. The block diagram of a direct conversion receiver is illustrated in Figure 2.14.

In a direct conversion receiver, the RF input signal is first passed through a bandpass filter. This preselect filter improves the dynamic range performance of the receiver by rejecting potentially large out of band interferers. Then, the RF signal is amplified by a low noise amplifier (LNA) and mixed with a local oscillator signal with a frequency equal to the desired signal. This mixing down converts the RF signal to baseband where final channel select filtering is performed with lowpass filters that are integration friendly. Thus, of all the alternative architectures developed to date, the direct conversion design as CHAPTER 2. Background and Literature Review 27

illustrated in Figure 2.14, offers the most promise for eliminating the on-chip bandpass filters, while simultaneously retaining high performance operation.

Mixer I Baseband I Processing 0 o LNA Divider Phase Shifter Baseband Processing Local Oscillator Bandpass Filter o (LO) 90 Baseband Q Q Processing Mixer

FIGURE 2.14. Block diagram of a direct conversion receiver.

The centre of the generated IF signal in a direct conversion receiver is at zero frequency, therefore no image response is produced, and no image rejection filter is needed. Therefore, the signal does not need to be routed off-chip to an image rejection filter in which a 50 ohm drive is required for load.

Interferer signals above and below the desired signal frequency are down converted to the IF baseband frequencies, above that of the desired signal. They will be removed from the processed signal in the baseband by lowpass filtering. For these reasons, the direct conversion receiver architecture can be viewed as a selective demodulator operating directly at the RF frequency.

Today, all of the transmitters in digital cellular telephones use direct conversion to produce a single sideband output [27]. In the receiver however, the classical super-heterodyne architecture is still more common. Only a handful of IC manufacturers use direct conversion for their receiver products. In [28]-[30] Alcatel has publicized its use of this architecture for its GSM and DECT receivers. However, Alcatel's front-end is a small IC and is implemented in Bipolar technology. CHAPTER 2. Background and Literature Review 28

As the super-heterodyne architecture has been in use for receivers over many decades, the designers are more familiar with its concepts and issues. Thus, there will be reluctance towards adopting a new modulation scheme unless its widespread use proves its effective- ness.

A question may arise now that if this architecture is so simple and requires less components and is promising to be low power than its super-heterodyne counterpart, why it is not widely used in the industry and its use is limited only to a few applications. The answer to this question is studied in the following section.

2.3 Direct Conversion Receiver Design Issues

Despite the attractive features of the direct conversion architecture, super-heterodyne based receiver architectures are almost exclusively used for RF signal reception. Direct conversion receivers are rarely used because they can be extremely noisy, resulting in severe performance degradation compared to conventional architectures [31]. In addition, direct translation of the RF spectrum to zero frequency raises a number of issues that do not exist or are not as serious in a super-heterodyne scheme [5]-[27]. Today, not only all of the RF blocks are being implemented on-chip using advanced IC technologies, but also radio designers are moving towards even more packing of both the RF and baseband processing onto a single chip as a system on chip (SoC).

All of these goals became possible because high levels of integration in advanced IC technologies allow implementation of more passive components such as inductors on- chip. Moreover, as the device sizes in the new design technologies are smaller, the transmission line effects will not be as severe as they were in the old technologies. These factors help to overcome the challenges of implementing direct conversion receivers in a single IC. The use of this architecture has been limited mainly due to four problems as follows:

• I/Q mismatch CHAPTER 2. Background and Literature Review 29

• DC offsets

• Flicker noise

• Even order distortion [5]-[32-33].

In the following sections these issues are studied in detail and possible solutions are listed.

2.3.1 I/Q Mismatch

Reception of the RF signals in which transmitted information is carried in both side- bands requires the implementation of in-phase (I) and quadrature (Q) channel conversions. Thus, as shown in the block diagram of Figure 2.14, a direct conversion architecture must comprise quadrature down conversion, which requires shifting either the input RF signal

or the LO output by 90o. Shifting of the RF signal on chip is not easy and can cause severe noise power-gain trade-offs. In addition, if shifting of the RF input signal does not happen

with precise 90o phase shift, neighbour interferers can occupy the band of interest. As the baseband detector can not distinguish this problem after the signal has been transformed to zero-IF, this can significantly deteriorate the receiver's performance. Thus, it is easier and better to shift the LO output as illustrated in Figure 2.12. For the receiver to work properly, the output of the local oscillator must have both a 0o (I) and 90o (Q) components at the RF frequency. Furthermore, the gains of the I and Q components must be tightly matched, because any mismatch of the I and Q signal will corrupt the down converted signal. The

problem of maintaining a precise 90o phase shift over the range of LO frequencies to which the receiver is tuned is complicated by the fact that the circuits must operate directly at the RF frequency.

Generally a conventional LO with an inductor and a capacitor (LC) resonator produces a single phase output signal. Quadrature phase shifting is then generated by passing this single phase signal through an RC and CR circuit [34]. The RC and CR circuits shift CHAPTER 2. Background and Literature Review 30

the signal by -45o and +45o, respectively. The time constants of the RC and CR circuits is equal to the period of oscillation. Any inaccuracy or mismatch between these Rs and Cs can cause mismatches between the amplitude and phase of the quadrature outputs. With the RC-CR phase shift network a phase error of 5o and amplitude error of 0.5 dB can be expected [35].

In an alternative approach, a 2fo oscillator is used to generate phase shifts [36]. The quadrature outputs are derived from dividing by two the positive and negative edges of flip flops with a clock frequency of twice the frequency of RF signal. In this method unequal delays of two flip flops and delay from 50% of duty cycle were reported to cause a phase error of less than 1%. However, in this method if achieving a lower phase error is possible, it comes with a cost of doubling the LO frequency [36]. Drawbacks of increasing the LO frequency are the need for higher power and increased sensitivity of LO frequency to parasitic.

Another way of generating quadrature output is by tapping at diametrically opposite points of a poly phase oscillator such as a variable frequency ring oscillator [37]. In this method the phase shift accuracy is limited by mismatches in the delays of the delay stages.

A phase error of less than 1o can be achieved by ring oscillators when capacitive loads of each tap are being carefully balanced.

Advanced IC technologies and on-chip implementation has led to better matched components and signal paths. IC quadrature oscillators have been reported with phase errors of less than 1o [37], which promises a better matching for the I and Q components. Researchers also developed different techniques to remove the I/Q mismatch. A general technique to remove the I/Q mismatch involves compensation, which requires a certain level of signal processing in the baseband part of the receiver. Careful circuit and layout design can also reduce the I/Q mismatch significantly. CHAPTER 2. Background and Literature Review 31

2.3.2 DC Offsets

DC offsets are considered the most serious problem of direct conversion [5]-[27]. As in the direct conversion receiver the RF signal is transformed to zero frequency, a large DC offset can corrupt the signal and saturate the signal processing blocks such as an ADC. Based on the modulation scheme used, there are different sources that can contribute to the DC offset. In this section, the two main sources of the DC offsets are studied.

In the integrated receiver, due to substrate and capacitive coupling, the isolation between the inputs of the front-end blocks such as, the LNA, mixer and LO output is not infinite. Therefore, it is possible that a portion of LO signal leaks to the inputs of LNA and mixer as illustrated in Figure 2.15. This LO leakage can then be self mixed with the LO signal in the mixer and produce a zero IF output. This effect can be better understood through an example. Assume that the sensitivity of the receiver is set around -70 dBm, and the RF front-end can provide a power gain of about 30 dB. If the reverse isolation of the LO output to the LNA input is 60 dB, then an LO signal with a 0 dBm output power strength can appear in the input of the LNA with -60 dBm power level. In such a case, the amplitude of the self-mixed component at the output of the RF front-end would be 10 dB stronger than the desired signal. In receivers that require higher input sensitivity, such as - 100 dBm, this self mixing can easily saturate the following circuits after the front-end and prohibit amplification and detection of the desired channel.

Bandpass Filter LNA IF Mixer

Baseband Processing

LO Leakage

Local Oscillator

FIGURE 2.15. Self mixing of the LO with LO leakage. CHAPTER 2. Background and Literature Review 32

A similar self mixing phenomenon can happen when a large interfering signal leaks from the LNA output to the LO input as shown in Figure 2.16. Moreover, the RF signal can be self-mixed in the mixer due to its nonlinearity and produce a DC offset at the mixer output. This offset appears in the middle of the down converted signal spectrum, and may be larger than the thermal and flicker noise.

Bandpass Filter LNA IF Mixer

Baseband Processing

RF and Interferer Leakages

Local Oscillator

FIGURE 2.16. Self mixing of the signal with RF and interferer leakages.

Furthermore, a small portion of the local oscillator energy can leak out of the antenna passband or it can couple into the antenna through external leads, and then radiate out. The radiated signal may become the in-band interferer to other receivers that are tuned in the same frequency band. For some of these receivers this interferer may be even stronger than their desired signal. In this case the problem of DC offset becomes even worse because of the time varying nature of generated self-mixed signal [5]. Standards and regulations of the Federal Communication Commission (FCC) in wireless communication limits the upper bound of the in-band LO leakage through antenna. This number is between -50 and -80 dBm, which is hard to meet for receivers with strong LO output power. If more sections of RF front-end are implemented on the same chip, or if a differential architecture is used for LO, the net coupling to the antenna can be significantly reduced and be within acceptable range. CHAPTER 2. Background and Literature Review 33

However, not all modulation schemes face the problem of DC offset when signal reception is done with direct conversion modulation. For example, in pager receivers the binary frequency shift keying (BFSK) is used. This modulation scheme is called “DC- free” because the signal energy near zero frequency is minimum. For other modulation schemes such as binary phase shift keying (BPSK) which are more spectrally efficient compared to BFSK, removing the DC offset by AC coupling method can not be used. There are large signals near DC in this modulation scheme, consequently, AC coupling the down converted signal before sampling in the baseband introduces severe intersymbol interference (ISI). Therefore, in communication receivers, AC coupling filters are exclusively used in “DC-free” modulation schemes such as BFSK [38].

A possible way of solving the DC offset problem is removing it from the down converted signal by AC coupling through a high pass filter. Unfortunately, only high pass filters with low corner frequencies, which yield slow response, are capable of achieving negligible signal degradation. A low corner frequency high pass filter requires large capacitors and resistors, which comes with a cost of larger chip area.

In applications where the time division multiple access (TDMA) modulation scheme is used, an offset cancellation method can be implemented. During the idle mode of operation, the offset can be stored on a capacitor and then be subtracted during the reception of a signal. However, the problem with this method is that interferer DC offsets may also be stored on the capacitor. Unfortunately, storing of these interferer offsets can happen any time and it does not depend on the sampling rate of TDMA. Detailed description of other methods of DC offset cancellations are described in [39-41].

2.3.3 Flicker Noise

Random trapping and releasing of charge carriers in submicron devices introduces flicker noise also known as 1/f noise or pink noise [42]. In addition to trapping and releasing, there are other mechanisms that can generate flicker noise [43]. Flicker noise is generally CHAPTER 2. Background and Literature Review 34

an intrinsic noise phenomenon and can not be easily predicted like thermal noise. In each IC technology, cleanness of the oxide-silicon interface defines the level of the flicker noise.

The trapping and releasing of the charge carriers mostly happens at low frequency. Consequently, the term 1/f reflects the fact that flicker noise can be modeled as a voltage source with a spectral density that is inversely proportional to frequency in the input of the active device. In analog and RF circuits the noise figure (NF) has been defined as the ratio of signal power to the total noise figure in the input and output as

SNR NF = ------in (2.3) SNRout where SNR is the signal to noise ratio. As illustrated in Figure 2.14, the direct conversion receiver is comprised of cascaded stages. The total noise figure of cascaded stages can be determined by knowing the NF and gain of each stage. For a system with m cascaded stages Friis developed the overall noise figure equation as [44]

NF – 1 NF – 1 NF = 1 ++++()NF – 1 ------2 - … ------m (2.4) total 1 G ⋅⋅⋅… 1 G1 G2 Gm – 1 th where Gn and NFn are the power gain and noise figure of the n stage, respectively. As Friis equation states, the noise contribution of each stage depends on the gain of preceding stages and it decreases as the gain of those stages increase. Therefore, it is most desirable to have higher gain in the first few stages of a receiver.

For most wireless applications, sensitivity of the receiver is defined such that with a gain of about 30 dB for the front-end (LNA and mixer), the down converted signal after the mixer is in the range of microvolts. As in direct conversion receivers the signal spectrum after down conversion is around zero frequency, the 1/f noise can comprise a significant portion of the signal power. CHAPTER 2. Background and Literature Review 35

However, flicker noise roll-off frequency is defined as the intersection point between the thermal noise and 1/f noise for a given device. The flicker noise roll-off frequency depends on the noise floor and the submicron technology being used [45]. In addition, it depends on the device dimensions and its bias current. Combinations of techniques can be used to reduce the effect of flicker noise in the receiver performance. For stages following the mixer which operate at low frequency, large devices with larger lengths can be used. Hence, the impact of 1/f noise is more important on the circuits that have to operate at high frequency. Moreover, to suppress the low frequency noise different techniques for periodic offset cancellation can be implemented.

2.3.4 Even-order Distortion

Almost all the devices and circuits of a receiver can be approximated with a linear model. However, in a real IC these devices and circuits demonstrate a non-linear behavior. In general nonlinearity can be approximated by a Taylor series expansion as

() () 2() 3() … yt = a1xt +++a2x t a3x t (2.5) n th where the an x (t) represents the n -order nonlinearity for n>1. Assume that the input sig- ω ω nal comprised two tone signals with angular frequencies of 1 and 2 with respective

amplitudes of A1 and A2 as

() ()ω ()ω xt = A1 cos 1t + A2 cos 2t (2.6)

If this signal is applied to a device or a circuit with a function defined by equation (2.5), the output will include frequency components that are integer components of the input frequencies.

As the amplitudes of the input signals A1 and A2 are small, the terms after the third- order in Taylor series can be simply ignored, and the output signal can be written as CHAPTER 2. Background and Literature Review 36

2 2 A1 A2 yt()= a ()A cos()ω t + A cos()ω t + a ------()12+ cos()ω t + ------()12+ cos()ω t + 1 1 1 2 2 2 2 1 2 2

()ω ω ()ω ω a2A1A2 cos 1 – 2 t + cos 1 + 2 t +

3 3 a3A1 a3A2 ------()3cos()ω t + cos() 3ω t + ------()3cos()ω t + cos() 3ω t + 4 1 1 4 2 2

2 a3A1A2 ------cos()2ω – ω t ++cos() 2ω + ω t 2cosω t + 4 1 2 1 2 2

2 a3A2A1 ------cos()2ω – ω t ++cos() 2ω + ω t 2cosω t . (2.7) 4 2 1 2 1 1 The fundamental components can be expressed as

y · ()t = a ()()ω ()ω + Fund 1 A1 cos 1t + A2 cos 2t

3a 3 3 2 2 ------3 A cos()ω t ++A cos()ω t 2A A cos()ω t + 2A A cos()ω t 4 1 1 2 2 1 2 2 2 1 1

3 2 3 2 3a3A1 3a3A1A2 3a3A2 3a3A2A1 = a A ++------cos()ω t + a A ++------cos()ω t 1 1 4 2 1 1 2 4 2 2

The high frequency terms in equation (2.7), such as 2ω1, 2ω2, 3ω1, 3ω2, 2ω1+ω2 and

2ω2+ω1 can be simply ignored because these intermodulation distortion are far from the

ω1 and ω2 frequencies. If the ω1 and ω2 are close in the frequency spectrum, then the ω ω ω ω ω ω intermodulation distortions of 2 1 –22 and 2 – 1 appear close to 1 and 2. This nonlinearity, which is due to third-order harmonic, is very important at the LNA output. CHAPTER 2. Background and Literature Review 37

In a direct conversion receiver, since the frequency of the LO is equal to the frequency of RF input, the even-order nonlinearity becomes a severe problem. As equation (2.7) describes, the second order nonlinearity includes two DC components as: a 2 2 ----2-()A + A and a A A cos()ω – ω t . These DC components can degrade the recep- 2 1 2 2 1 2 1 2 tion of the desired signal in the baseband.

Moreover, an interferer signal can go through a device which exhibits second order nonlinearity in the form of low frequency amplitude modulation (AM). Assuming the interferer can be expressed as

() εω()⋅ ω ⋅ ω xt = A1 + cos mt a cos 1t + b cos 1t

εω where cos mt is a low frequency AM signal. In this case, the second order nonlinearity

2 2 2 ()εω in equation (2.7) results low frequency terms of a + b A cos mt . This low frequency term is an even-order distortion in baseband signal and basically is the demodulated AM component [5].

Another condition in which undesired baseband component is generated, is when the second harmonic of the desired RF signal is mixed with the second harmonic of the LO. In a receiver both the LNA and mixer exhibit even order distortion. However, the design of the mixer is more complex because the RF signal applied to the mixer is amplified by the LNA. In addition, mixing of the RF and LO signals is done by the mixer. Hence, the mixer usually produces larger even-order distortion than the LNA [46].

In a super-heterodyne receiver, the low frequency distortion is usually removed by using a bandpass filter after the mixer. The even order distortion in a direct conversion receiver is buried in the desired baseband signal and can not be removed by bandpass filtering. From equation (2.7), it can be observed that the even-order harmonics can be removed if the system has odd symmetry or it is fully differential. However, in real ICs, CHAPTER 2. Background and Literature Review 38

the phase and amplitude mismatches corrupt the symmetry of the differential signals. In addition, implementing differential circuits at RF frequencies is not simple and is challenging. As the power amplifier in the transmitter is single ended, the antenna and the RF filter are usually single ended. Therefore, the RF input signal must be converted to differential either before or after the LNA. Converting the received signal before the LNA can be done by lossy RF transformers which directly increase the receiver noise figure according to equation (2.4). Moreover, to achieve the same noise figure, a differential LNA consumes more power than the single ended counterpart.

To minimize the even-order nonlinearity, researchers in [47] used a digital control for the mixer bias current and maintained the differential circuit balance. A method to adap- tively compensate the even-order distortion in direct conversion receivers is reported in [46]. In this method, digital signal processing (DSP) is used to compensate the even-order distortion in the baseband. 39

CHAPTER 3 System Requirements

Acceptance of integrated radio receivers in the industry for mass production depends to a large degree on the performance that can be achieved. Therefore, it is important to understand the system level performance that is required, before studying circuit level approaches to integration. In this Chapter the performance requirements are identified and the radio frequency band where the receiver operates is briefly reviewed. Then, an overview of important wireless services that could benefit from an integrated receiver is provided. Finally, the most critical parameters that can measure the receiver performance are examined. These parameters directly affect the design of circuits for an integrated receiver.

For the direct conversion receiver examined in Chapter 2, the RF front-end was found to be the primary stage hindering the receiver performance. Thus, study of critical parameters for receiver performance will be mostly weighted toward requirements that have a significant bearing on the front-end design.

3.1 The Frequency Range and Spectrum Environment

The useful radio frequency spectrum extends from ultra low frequencies in the range of 100 kHz, to millimeter wave frequencies of 30 GHz and above. The need for higher data rates and crowded spectral, necessitates the use of higher frequencies. Today most of mod- Chapter 3. System Requirements 40

ern wireless systems are in the ultra high frequency (UHF) range of 300 MHz to the millimeter wave (30 GHz) frequency range [48].

However, the trend is to use the higher frequencies in this range. Within this spectrum a large number of radio services exist, ranging from paging, television, mobile and satellite communication, global positioning system, to wireless local area networks (WLANs). In Table 3.1, frequencies of different wireless systems are listed [48].

Recently, commercial interest has focused on the use of 1.22-5.805 GHz frequencies to provide personal wireless and low power communications. Applications of this frequency range include the global positioning system (GPS), WLANs and personal communications services (PCSs). These systems reside in regions of spectrum close to each other and must satisfy their standard requirements. For example, in FM broadcast service, where possible, the Federal Communication Commission (F.C.C) attempts to allocate station frequency assignment at 400 kHz intervals or greater to minimize adjacent channel problems. However, in large metropolitans, stations can often be found spaced by the minimum 200 kHz interval. In addition, portable radio receivers typically have omni-directional antennas. Thus, they are more susceptible to signals arriving from any transmitter emitting radio energy in their direction. This fact makes the design of receivers more complicated. Thus, the same receiver must select, amplify and demodulate the desired signal while a wide range of interfering signals on nearby frequencies are present.

There are different ways to categorize wireless systems. One way is to divide it by the nature and placement of users. In this category, the transmitters and receivers may communicate with each other in a point-to-point, point-to-multipoint or multipoint-to-multipoint way. The wireless systems can also be characterized in terms of directionality of communication. The transmitter and receiver may communicate in a simplex, half-duplex or full-duplex system. In Table 3.2, the first generation of analog cellular radio systems that are used throughout the world are listed [49] Chapter 3. System Requirements 41

TABLE 3.1. Frequency ranges of different wireless systems.

Wireless System Operating Frequency Advanced Mobile Phone Service (AMPS) T: 824-849 MHz R: 869-894 MHz Global System Mobile (GSM) T: 880- 915 MHz R: 925-960 MHz Personal Communication Services (PCS) T: 1710-1785 MHz R: 1805-1880 MHz US Paging 931-932 MHz Global Positioning System (GPS) L1: 1575.42 MHz L2: 1227.60 MHz Direct Broadcast Satellite (DBS) 11.7-12.5 GHz

Wireless Local Area Networks (WLANs) 902-928 MHz 2.4-2.484 GHz 5.725-5.85 GHz Local Multipoint Distribution Service (LMDS) 28 GHz

US Industrial, Medical and Scientific bands (ISM) 902-928 MHz 2.4-2.484 GHz 5.725-5.85 GHz Chapter 3. System Requirements 42

TABLE 3.2. Summary of the first generation analog cellular radio systems.

Channel Mobile Transmitter / Spacing Number of Standard Base Transmitter (MHz) (kHz) Channels Region AMPS 824-849 / 869-894 30 832 The Americas TACS 890-915 / 935-960 25 1000 Europe ETACS 872-905 / 917-950 25 1240 United Kingdom NMT 450 453-457.5 / 25 180 Europe 463-467.5 NMT 900 890-915 / 12.5 1999 Europe 935-960 C-450 450-455.74 / 10 573 Germany, 460-465.74 Portugal RTMS 450-455 / 460-465 25 200 Italy Radio- 192.5-199.5 / 200.5-207.5 12.5 560 France com 2000 215.5-233.5 / 207.5-215.5 640 165.2-168.4 / 169.8-173 256 414.8-418 / 424.8-428 256 NTT 925-940 / 870-885 25 / 6.25 600 / 2400 Japan 915-918.5 / 860-863.5 6.25 560 922-925 / 867-870 6.25 480 JTACS/ 915-925 / 860-870 25 / 12.5 400 / 800 Japan NTACS 898-901 / 843-846 25 / 12.5 120 / 240 918.5-922 / 863.5-867 12.5 280 Chapter 3. System Requirements 43

3.2 Commercial Wireless Services

In addition to challenges presented by the radio spectrum environment, receiver design must take into account a wide range of system design parameters. These include the operating frequency, signal bandwidth and type of modulation. The accuracy that is required for the local oscillator in the receiver is defined by bandwidth of the channel and the RF input signal frequency. Systems such as AMPS cellular which use a 30 kHz bandwidth and operate at 900 MHz, have very stringent requirements on frequency accuracy. Due to the use of MHz range bandwidths, systems such as DECT, have more relaxed requirement. The modulation method in the receiver defines whether an AGC or a simple limiting IF amplifier is required.

To simultaneously use the antenna for transmit and receive signal in a frequency division duplex (FDD) modulation, a full duplex filter is needed. The duplex filters in these systems are required to handle substantial transmitted power. Thus, it may not be possible to use active filter technology, which is an important issue for integration of radio receiver. The alternative time division duplex (TDD) is more integration friendly, because it requires only an RF switch.

The type of multiplexing in wireless system has a great impact on the IF filter tuning method. In systems which some form of time division multiplexing (TDM) is used, it may be possible to take the filters off-line during time slots that are not of interest to the receiver. This allows simplified tuning approaches to be developed.

3.3 IEEE 802.11 Standard

RF systems have progressed rapidly with the popularization of cellular phones. This high growth demands broadband wireless communications. In 1997, the working group 11 of the Institute of Electrical and Electronics Engineers (IEEE) LAN/WLAN Standard Com- Chapter 3. System Requirements 44

mittee (IEEE 802) developed a set of wireless LAN/WLAN standards [50]. Today, the term 802.11x denotes this set of standards. However, there is no single 802.11x standard. The term IEEE 802.11 is used to refer to the original 802.11 standard known as “802.11 legacy”.

This standard provided flexibility and reconfigurability and was soon adopted for WLAN systems in office buildings, hospitals, etc. It specifies raw data rates of 1 and 2 Mega-bits per second (Mbit/s) to be transmitted via infrared (IR) signals or by spread spectrum modulation at 2.4 GHz. In this standard two types of spread spectrum are offered: direct sequence (DS) with quadrature phase shift keying (QPSK) modulation and frequency hopped with Gaussian minimum shift keying (GMSK) modulation [51]. In the DS-SS modulation, a 2 MHz channel is spread by a factor of 11 and generates a 22 MHz

–2 wide output channel. For a frame error rate of (FER) of 810× , the sensitivity of the receiver across this band-width is -80 dBm.

A weakness of this original specification was that it offered so many choices that some times it was too hard to realize interoperable systems. The IEEE 802.11 is really more of a “beta-specification” which allowed IC manufacturers the flexibility to differen- tiate their products.

The 802.11 family currently includes six over-the-air modulation techniques that all use the same protocol. The most popular techniques are those defined by the b, a, and g amendments to the original standard. Security was originally included and was later enhanced via the 802.11i amendment. 802.11n is another modulation technique that has recently been developed. The standard 802.11n is still under development, although products designed based on draft versions of the standard are being sold. Other standards in the family (c–f, h, j) are service enhancements and extensions or corrections to previous specifications. 802.11b was the first widely accepted wireless networking standard, followed by 802.11a and 802.11g. Chapter 3. System Requirements 45

The 802.11b amendment to the original standard was ratified in 1999. The 802.11b has a maximum raw data rate of 11 Mbit/s. In practice the maximum 802.11b throughput that an application can achieve is about 5.9 Mbit/s. The 802.11b standard is usually used in a point-to-multipoint configuration. In this configuration a user communicates via an omni-directional antenna with one or more users that are located in a coverage area around the access point. Typical indoor ranges are 30 m at 11 Mbit/s and 90 m at 1 Mbit/s.

The 802.11b and 802.11g standards use the 2.4 GHz band, operating in the United States. Because of this choice of frequency band, 802.11b and 802.11g equipment can incur interference from microwave ovens, Bluetooth devices, cordless phones and other appliances that use the same band. The 802.11a standard uses the 5 GHz band, and is therefore not affected by products operating on the 2.4 GHz band. In Table 3.3 a summary of the IEEE 802.11 standards are listed [50].

In 1999, the 802.11a amendment to the original standard was ratified. The 802.11a standard uses a 52 subcarrier orthogonal frequency division multiplexing (OFDM) with a maximum raw data rate of 54 Mbit/s and uses the same core protocol as the original standard and operates in 5 GHz band. This yields realistic achievable throughput in the mid - 20 Mbit/s. It is also possible to use the reduced data rate of 48, 36, 24, 18, 12, 9 and 6 Mbit/s if required. The 802.11a has 12 non-overlapping channels, 8 dedicated to indoor and 4 to point to point. The 802.11a standard is not interoperable with 802.11b, except if using equipment that implements both standards.

Unlike the 2.4 GHz band, the 5GHz band is not heavily used and thus gives 802.11a the advantage of less interference. However, this high carrier frequency also brings disad- vantages. It means that 802.11a cannot penetrate as far as 802.11b since it is absorbed more readily, if other things such as transmitted power are equal. Furthermore, it restricts the use of 802.11a to almost line of sight, which requires the use of more access points. Chapter 3. System Requirements 46

TABLE 3.3. Summary of IEEE 802.11 standards.

Operating Release Frequency Data Rate Data Rate Indoor Protocol Date (GHz) (Typical) (Max) Range

Legacy 1997 2.4-2.5 1 Mbit/s 2 Mbit/s ?

802.11a 1999 5.15-5.35 25 Mbit/s 54 Mbit/s ~50 meters 5.47-5.725 5.725-5.875

802.11b 1999 2.4-2.5 6.5 Mbit/s 11 Mbit/s ~100 meters

802.11g 2003 2.4-2.5 25 Mbit/s 54 Mbit/s ~30 meters

802.11n 2006 2.4 or 5 200 Mbit/s 540 Mbit/s ~50 meters (draft)

However, different countries have different regulatory support. The 802.11a standard is now approved by regulations in the United States and Japan. In other countries, such as the European countries, the 802.11a had to wait longer for approval. European regulators were considering the use of the European HIPERLAN standard, but in mid-2002 cleared 802.11a for use in Europe.

3.4 Receiver Performance

A receiver is required to perform the fundamental tasks, which include: Chapter 3. System Requirements 47

• Amplification of the received signal to a level which is suitable for demodulation.

• Selection of the desired signal from a dense spectrum environment.

• Demodulate the received signal to recover the transmitted information.

The ability of the receiver to carry out these tasks is typically measured through a set of quantified performances. A typical way of evaluating the receiver performance can be done by measuring the following parameters:

• Sensitivity

• Selectivity

• Dynamic Range

• Fidelity.

These performance parameters are explained in the following sections in depth. These parameters are used later to assess the proposed integrated circuit designs that are proposed in this dissertation.

3.4.1 Sensitivity

The ability of a receiver to amplify and demodulate weak signals is a measure of its sensitivity. It is often expressed in terms of the minimum signal level at the input of the receiver, which produces acceptable fidelity in the demodulated output. A reliable receiver requires receive signal power at or above a certain minimum level called minimum detectable signal (MDS). The MDS determines the minimum signal to noise ratio (SNR) at the demodulator of the receiver for a given system. Chapter 3. System Requirements 48

The receiver’s sensitivity depends on the type of signaling method, demodulation employed, and the RF and IF sections. This dissertation, however, is primarily focused on the development of the integrated RF sections for direct down conversion. The receiver noise figure will be the primary measure of sensitivity used. The noise figure of a receiver is defined as

S ⁄ N ------i i- NF = ⁄ So No

where S and N represent the signal and noise powers, respectively. The subscripts i and o represent the input at the antenna port and the demodulator input, respectively. The overall noise figure NF, can be related to the noise figure of individual blocks of the receiver by

NF2 – 1 NF= NF1 + ------(3.1) G1

where NF1 and G1 represent the noise figure and power gain of the front end of the

receiver, respectively and NF2 is the noise figure of the stages following the front end. For

a typical receiver, the gain G1 used is based on trade-offs between noise figure and dynamic range, and lies in the range of 10 to 40 dB.

3.4.2 Dynamic Range

The lowest signal level that can be received is determined by the receiver’s noise figure and the thermal noise floor. The highest signal level which is allowed is a function of saturation and distortion effects in the receiver’s active circuits. In some applications, the signal level variations may reach up to 80 dB or more. Thus, the receiver must be able to receive signals with this wide amplitude variation and process them. In receiver design, different definitions of dynamic range exist. The three main definitions of receiver dynamic range are: Chapter 3. System Requirements 49

• Total dynamic range

• Blocking dynamic range

• Spurious free dynamic range

In the subsections which follow, each of these main definitions are reviewed. More- over, the implications of these performance parameters for the design of integrated RF front-end are discussed.

3.4.2.1 Total Dynamic Range

The total dynamic range of a receiver DRtot can be defined in dB as

DRtot = Pmax – Pmin (3.2)

where Pmax is the power above which unacceptable distortion in the demodulated signal

occurs. Pmin is the minimum usable input signal power for acceptable reception. DRtot depends on the type of radio service, the power consumption and cost of the receiver hard-

ware. Typical values of DRtot found in modern receivers range from 40 dB to well over 80 dB. With an input dynamic range of about 100 dBm, the input power at the baseband signal processor can be in the 0.001 to 1 V range [48].

The value of DRtot required in a receiver is mainly determined by how close the receiver is allowed to come to the transmitter and the minimum effective radiated power at the transmitter site.

An extensive study of signal levels versus distance from base station transmitters have been performed for the case of cellular telephone receivers in [52]. The dynamic range requirements can be derived directly from transmitter power and propagation considerations. In order to translate these requirements to requirements on RF front-ends used within a receiver, additional factors must be taken into account. For example, in systems Chapter 3. System Requirements 50

employing RF preselect filters with switchable attenuators at the antenna input port, the total dynamic range requirement on the RF front-end can be smaller than that of the overall receiver.

3.4.2.2 Blocking Dynamic Range

In any receiver design, the most dynamic range requirement is the reception of a weak signal in the presence of one or more interfering signals outside the desired channel. In conditions where the desired signal is weak, for example the received signals in GPS which are near the noise floor, full gain of the receiver and hence, full sensitivity of the receiver are required. In such cases, a large interfering signal will be amplified to a very high level and will saturate the receiver circuits.

If the automatic gain control (AGC) is saturated in the input, it will not be active. Thus, the receiver’s overall gain will reduce. If gain is reduced to the point were the desired channel is no longer received, the signal is said to be “blocked”. The blocking dynamic range (BDR) of a receiver can be estimated in dB as

≈ BDR P1dB – MDS (3.3)

where P1dB is the power of the interfering signal at the antenna port which results in 1dB compression.

The BDR value required in a receiver depends on the environment in which the

receiver operates, and can be found based on similar considerations to the DRtot [52]. However, satisfying the BDR requirements is more difficult due to the presence of a large and variable numbers of interferers. Furthermore, the existence and physical distances of transmitters in other service bands make it more complicated to fully characterize the interferers. Chapter 3. System Requirements 51

3.4.2.3 Spurious Free Dynamic Range

The spurious free dynamic range (SFDR) is defined as the input power Pi3 at which the intermodulation products rise above the noise floor, divided by MDS. The SFDR can be expressed as [10]

SFDR= Pi3 – MDS (3.4) where Pi3 can be found in terms of the third-order intercept point IIP3 and MDS as

1 P = IIP – ---()IIP – MDS (3.5) i3 3 3 3 Therefore, SFDR can also be expressed as

2 SFDR = ---()IIP – MDS (3.6) 3 3 Thus, from (3.3) and (3.6) both BDR and SFDR figures of merit can be found, provided that input 1dB compression point and third-order intercept points are known. The

P1dB and IIP3 can be related by

∆ IIP3 = P1dB +

where depending on the implementation details of the circuit, ∆ is between 5 to 15 dB. In [53] a ∆ of 9 dB is suggested after simplifying the Taylor series expansion of the input and intermodulation products. Using ∆ = 9 dB, in (3.3) and (3.6), yields

2 SFDR ≈ ---()BDR + 9 3

Therefore, the following conclusions apply to BDR and SFDR: Chapter 3. System Requirements 52

• There are some upper limits on the SFDR that a receiver can achieve. As for the BDR, these limits depend on the power consumption of the active circuit.

• Increasing the receiver’s SFDR requires either a gain reduction, which worsens the overall noise figure, or an increase in the front-end compression point, which requires more power consumption.

3.4.3 Selectivity

The selectivity of a receiver is defined by its ability to reject signals out of the desired channels, amplify and demodulate signal at a desired frequency. Selectivity is primarily a function of IF channel select filter. However, the intermodulation products and blocking effect discussed in the previous sub-sections can limit the attainable selectivity. In receivers with a super-heterodyne architecture, selectivity can be measured by evaluating the adjacent channel selectivity, image rejection and spurious response rejection. In receivers with direct conversion architecture, no image signal is produced and hence, it will not be discussed in this dissertation.

3.4.3.1 Adjacent Channel Selectivity

The adjacent channel selectivity refers to any other channel which is near the desired channel. A more precise definition is either the channel immediately above or immediately below the one to which the receiver is tuned.

For practical and economical reasons, radio system specifications do not allow that two signals in the same geographical area reside in adjacent channels. This constraint on the radio system relaxes performance requirements on both transmitter spectral purity and receiver IF filtering. Chapter 3. System Requirements 53

In an alternative approach, signal bandwidth is limited to some fraction of the channel spacing to reduce interference between users allocated in adjacent channel bands. In this approach a “guard band” occur on either side of the transmitted signal [54]. In the third approach, the spectral energy in a transmitted signal employing a certain type of modulation and program material is statistically concentrated at the channel center. In this approach, the guard bands are implicitly present.

For the case, in which the guard bands are not used, the IF filter bandwidth is generally equal to the channel spacing. For the case with guard bands (either implicitly or explicitly), the IF filter bandwidth can be reduced. This allows better selectivity in adjacent channels to be achieved with a similar number of poles as that in the case without guard bands.

3.4.3.2 Spurious Response Rejection

Due to the non-linear behavior of the RF mixer, sum and difference frequencies of input signals are produced. In addition to these components, intermodulation products with lower power level are generated at frequencies given by

fmf= RF – nfLO (3.7) where m and n are positive integers. Some of these spurious responses (or spurs) may fall within the IF band and cause problems. In multichannel wireless receivers this may

become a major concern, since different combinations of fRF and fLO can happen. RF mixers often suppress most of products given in (3.7) due to symmetry and phase cancellation. If a double balanced architecture is selected for the mixer, all spurious responses due to even numbers of m or n will be rejected.

The spurious response rejection is a measure of receiver’s ability to receive a modu- lated desired RF input signal in the presence of two interfering tones. These interferers are separated from the desired input RF signal such that in the nonlinear circuits of the Chapter 3. System Requirements 54

receiver, nth order mixing of the two interferer signals happens and produces a third signal in the band of desired signal. The spurious response rejection is defined as the ability of a receiver to prevent single unwanted signals from causing degradation to the reception of a desired signal. It is expressed as the ratio of the level of a single unwanted input signal that causes the signal plus noise and distortion-to-noise and distortion ratio (SINAD) produced by a wanted signal 3 dB in excess of the reference sensitivity to be degraded to the standard SINAD, to the reference sensitivity. The SINAD is related to SNR as

SN+ S SINAD ==------1 + ---- (3.8) N N

3.4.4 Fidelity

The ability of a receiver to accurately demodulate the information contained in the desired RF signal is defined as its fidelity. In a digital system fidelity is typically measured in terms of symbol or bit error rate (BER). BER is defined as the measured average number of incorrect bits at the output of the detector divided by the total number of bits received in a unit time. To evaluate the BER the probability of error in the presence of noise and other interferers must be calculated. In an analog FM receiver, measurement of the total harmonic distortion presented in the recovered radio waveform defines the fidelity.

In both digital and analog systems, fidelity depends on the IF filter and the employed demodulator design. If it is assumed that the demodulator is ideal, the fidelity of the receiver can be related to the in-band response of the IF channel select filter. An ideal filer produces only amplitude scaling and a phase delay and has a flat amplitude response and a linear phase over the signal bandwidth.

However, real filters do not have these characteristics. Thus, an evaluation of amplitude and phase distortion from the ideal case on the receiver’s fidelity is required. In receiver design, based on the fidelity requirement on each wireless service, the effects of Chapter 3. System Requirements 55

non-ideal behavior of amplitude and phase responses must be determined and optimized to meet the needed specification.

In some PCS products operating with large bandwidths, surface acoustic wave (SAW) filters are used. The reason is that SAW filters have highly linear phase response compared to on-chip filter counterparts. However, the high cost and matching issues of SAW filters prohibits their wide use in the industry. Furthermore, implementing SAW filters in the receiver design is generally avoided in the newer wireless products due to the desire of implementing all parts of the receiver on-chip.

3.5 Direct Down Conversion Receiver Requirements

The 802.11a standard for 3rd generation of wireless communication systems has a 20 MHz channel bandwidth, in the frequency range of 5.18-5.32 GHz (centered at 5.25 GHz). At 5.25 GHz, the 20 MHz bandwidth is equivalent to 3.8% of the RF center frequency. The data rate in this standard is 54 Mb/s. The selected modulation scheme is 64 quadrature amplitude modulation (QAM) with orthogonal frequency division multiplexing (OFDM). Table 3.4 shows a summary of the IEEE 802.11a standard that has been used to calculate the receiver requirements. Chapter 3. System Requirements 56

TABLE 3.4. Summary of IEEE 802.11a standard.

Operating Frequency 5.18-5.32 GHz 5.745-5.805 GHz

Bandwidth 20 MHz

Modulation 64 QAM

Sensitivity -65 dBm

Data Rate (Typical) 25 Mbit/s

For the receiver the desired bit error rate (BER) is considered to be near fiber optic quality, BER =10-9or better. The input thermal noise floor from antenna can be calculated as [55]

⋅⋅ Nfloor = kTB (3.9) where k is Boltzmann’s constant, T is the antenna temperature in Kelvin and B is the band-

width of the received signal. Assuming T =290 oK, the input noise floor can be calculated as

() (). (3.10) Nfloor dBm = –10174dBm + log B

For the IEEE 802.11a standard, the bandwidth is 20 MHz, thus the input noise floor is -101dBm.

The sensitivity of an RF receiver is defined as the minimum signal level that the system can detect with acceptable signal to noise ratio and can be calculated from

P = P ⋅⋅NF SNR (3.11) sig RS out

where PRS is the source resistance noise, NF is the noise figure of the system and SNRout is the minimum acceptable signal to noise ratio in the output. Since the overall signal power Chapter 3. System Requirements 57

is distributed across the channel bandwidth B, the two sides of the above equation must be integrated over the bandwidth to obtain the total mean square power. For a flat channel the sensitivity of the receiver can be derived from

⋅⋅ ⋅ Psigtotal = PRS NF SNRout B . (3.12)

Therefore sensitivity is the minimum input signal that yields a given value for the output SNR. Since sensitivity is a function of the bandwidth, a receiver may appear very sensitive simply because it employs a narrowband channel, which is at the cost of low information rate. PRS is the source resistance noise and was calculated to be -174 dBm at room temperature. Sensitivity level is always specified with respect to a certain receiver performance level. As explained in the previous sections, the performance level for digital communication is evaluated by measuring the BER.

From equation (3.12) the SNR min, can be calculated as [2]

() · Pin, min = PRS ++NF 10log B + SNRmin . (3.13) dBm ()dBm ⁄ ()Hz dB dB The first three terms in equation (3.13) are the total integrated noise of the system and are equal to the system noise floor. Using the required sensitivity of the IEEE 802.11a standard the minimum output signal to noise ratio can be calculated as

-65 dBm= -101 dB+ SNRmin dB which yields a receiver output SNR min of 36 dB. For digital modulation, the bit energy to noise power spectral density, is related to the SNR and bit rate as follows

Eb Rb SNR = ------⋅ ------(3.14) No B ⁄ where Rb is the bit rate and Eb No is the bit energy to noise power spectral density. If the ⁄ SNR of the system is known from equation (3.14), then Eb No ratio can be calculated. Chapter 3. System Requirements 58

⁄ ⁄ Eb No is calculated to be 35.03 dB for a 64QAM system [48]. Knowing the Eb No and the M-ary, the BER of the system can be derived from [56]

–1 () × 21⋅ ()– M 3log M 2 Eb BER = ------× erfc ------2 - ⋅ ------(3.15) log ()M 2 N 2 M – 1 o where M is the number of signal levels on the I and Q channels and for this system is equal to 64, erf is the complementary error function. It can be noted from equation (3.15) ⁄ that the BER decreases significantly with an increase in Eb No . Furthermore, increasing

the order of M-ary modulation method reduces the error rate. The bit energy Eb can be calculated as

S Eb = ------(3.16) Rb where S is a fixed signal power. The capacity of a channel with bandwidth B and additive Gaussian band limited white noise is given by a formula derived by Claude Shannon [57]

S CB= log 1 + ------(3.17) 2 NoB where C is the maximum data rate capacity of the channel in bits per second (bps) and No/ 2 is the two sided power spectral density of the Gaussian noise. However, equation (3.17) gives the upper bound on the maximum data rate that can be achieved for a given channel in the presence of additive Gaussian noise. Only a fraction of this value is achieved by most practical modulation methods.

Equation (3.15) results in a BER of greater than 10-9 for M=64. If a better BER is

needed, such as a BER of 10-9, then the sensitivity of the system needs to be reduced or the minimum SNR of the system needs to be decreased. For the work of this dissertation, a SNR of 30 dB has been considered in the calculation. Knowing the SNR of the system, it is Chapter 3. System Requirements 59

now possible to calculate the maximum allowable noise figure for the receiver. Using ≤ () NFmax PRX – Nfloor + SNRmin , the maximum noise figure for the receiver is calculated as 6 dB. 60

CHAPTER 4 Integrated RF Front-End Design Options

Integrated RF receivers for wireless applications need to fulfill the demands of low power consumption and low cost of implementation which implies a high level of integration. An additional advantage of integration of the RF blocks in one chip is that, variations of circuit parameters across supply voltage and temperature can be improved by implementing sophisticated on-chip compensation techniques [58]. It is feasible to build stand-alone RF amplifiers [59], mixer IC’s [60-61] and oscillators into integrated RF blocks. The next development step calls for on-chip integration of these circuits into subcells, comparable in function with off-chip products. An RF low noise amplifier (LNA) with a down conversion mixer, often called the receiver’s front-end is an example of such an IC. At present, integrated RF front-ends are widely used due to their combined RF signal processing on one chip. Furthermore, a front-end translates the RF signal down to an intermediate frequency (IF), which is easier to handle and use.

As explained in Section 3.4, most of the receiver’s requirements, such as sensitivity, dynamic range and fidelity, are completely or partially related to the performance parameters of the front-end blocks of the receiver. In this section, the RF front-end design options for integrated receivers are investigated and challenges of low voltage and low power designs are studied. Chapter 4. Integrated RF Front-End Design Options 61

4.1 RF Front-End

4.1.1 RF Front-End Architectures

The function of an RF front-end is to provide an interface between the received RF signal and the IF / baseband signal processing. For some telecommunication systems, this interface is bidirectional because it consists of both transmitter and receiver. In this section the attention is paid to the front-ends for RF receiver. The selection of RF front-end topology is defined by the receiver architecture. As was explained in Section 2.2, the super-heterodyne architecture requires off-chip SAW filters. Thus, receivers with this architecture cannot be completely implemented on-chip and are not a preferred solution. Between the low IF architecture and direct conversion, the low IF architecture is less susceptible to DC offset and flicker noise. The direct conversion suffers impairments of I/Q mismatch, DC offsets, 1/f noise, even order distortion and LO leakage. The low IF architectures also suffers from LO leakage and even order distortion. Furthermore, low IF receivers need a high Q image rejection filter because during the conversion of the RF signal to low IF, an adjacent channel may fall on the image of the desired signal. In a direct conversion receiver, no image is produced, therefore, there is no need to implement an image rejection filter.

Moreover, the signal bandwidth in low IF architecture is doubled compared to the direct conversion. Hence, the low IF receiver needs an analog to digital converter (ADC) with a doubled sampling rate, which results in higher power consumption. In addition, in a low IF conversion receiver, the base band filters require double bandwidth due to double signal bandwidth, that mandates higher power consumption and design complexity [62].

The IEEE 802.11a spectrum does not contain any information at zero-frequency. Due to the “dc-free” modulation scheme in this standard, implementation of the direct conversion architecture will be easier [63]. Therefore, the direct conversion architecture is chosen for receiver front-end design in this dissertation. Chapter 4. Integrated RF Front-End Design Options 62

4.1.2 RF Front-End Building Blocks and Characteristics

The main functions of the RF front-end are to amplify a weak signal to a certain level suitable for further processing and to down convert the frequency of the input signal to low frequency suitable for signal processing. An RF front-end consists of hundreds to thou- sands of active devices. Comparing this number to millions of transistors in the baseband and digital section may cause one to assume that the design of the RF front-end is a trivial job. However, the fact is that the size of the front-end in the integrated circuit (IC) is almost half of the total size of a receiver. Furthermore, the total power consumption of the receiver is mainly determined by the power consumption of the RF font-end. Therefore, the RF front-end has a major impact on the goals of low power and small size (cheaper product).

In a direct conversion receiver, the low noise amplifier (LNA) and a down conversion mixer together make the RF front-end. As there is no image to be rejected, the LNA is directly connected to the down-conversion mixer. The block diagram of a direct conversion receiver is shown in Figure 4.1.

Mixer I Baseband I Processing 0 o LNA Splitter Phase Shifter Baseband Processing Local Oscillator Bandpass Filter o (LO) 90 Baseband Q Q Processing Mixer

RF Front-End

FIGURE 4.1. Block diagram of a direct conversion receiver Chapter 4. Integrated RF Front-End Design Options 63

As illustrated in Figure 4.1, the front-end often is directly connected to the antenna. Therefore, the RF input impedance of the front-end, over the desired frequency band must be matched to the antenna’s characteristic impedance. In most applications, the antenna’s characteristic impedance is equal to 50 Ω. For the receiver to be able to detect weak input signals, the input noise of the RF front-end must be very low [64]. In addition, the gain of the front-end must be high to reduce the noise contributions of the IF and baseband stages. Furthermore, for a receiver to be able to distinguish a weak desired signal located close to a large interferer in the frequency spectrum, the front-end must have a wide dynamic range.

4.2 RF Front-End Selection for Homodyne Architecture

As illustrated in Figure 4.1, a block diagram of the RF front-end often contains cascaded stages. Therefore, only through a careful co-design of the building blocks can good performance be achieved. A detailed comparison of possible alternatives for highly integrated RF front-ends is reported in [65]. In this section, different alternatives of RF front-end building blocks for direct conversion receiver are examined and advantages and disadvan- tages of each alternative are studied.

A possible alternative of the RF front-end is illustrated in Figure 4.2, which includes a single ended LNA and a passive mixer. Design of an LNA alone involves many trade-offs, including low noise figure performance, high gain, good linearity and low power consumption [58]. Furthermore, an LNA’s input and output impedances must minimize the need for external matching components. Combining the LNA in an integrated circuit with the mixer for a direct conversion receiver, puts additional demands on its design. To obtain this, the LNA must be designed for high gain to overcome the fundamentally high noise of the mixer and baseband stages, but too large a gain may overload the mixer and degrade the dynamic range performance. Also to meet the low power demand, it is better to avoid Chapter 4. Integrated RF Front-End Design Options 64

a power hungry RF buffer and instead connect the output of the LNA with a simple matching circuitry to the mixer input. Furthermore, to minimize the leakage of the LO signal into the input and the antenna, it is desirable to design the LNA with high reverse isolation.

Passive Mixer Baseband I Processing 0 o LNA I Splitter Phase Shifter Baseband Processing Local Oscillator Bandpass Filter (LO) Q o 90 Baseband Q Processing Passive Mixer

RF Front-End

FIGURE 4.2. Block diagram of a direct conversion receiver with a passive mixer in the front-end.

A possible option for the mixer in a direct conversion receiver can be a passive mixer as shown in Figure 4.2, because these mixers are free of flicker noise [66]. A passive mixer can be implemented by four CMOS transistors acting as analog switches. However, the reverse isolation of a passive commutating mixer is very poor, and the circuits after the mixer can change the load of the LNA and degrade its gain performance. Furthermore, since a passive mixer has power loss, the LNA must have extremely high gain and very low noise figure to compensate for the losses of mixer and suppress the noise of the following baseband sections. An LNA with these characteristics has high power consumption, and it would be very difficult to stabilize the performance with process, voltage and temperature (PVT) variations. Chapter 4. Integrated RF Front-End Design Options 65

An alternative approach to this front-end is shown in Figure 4.3, where two stages of LNAs precede a passive mixer. A low power system which is the result of comprehensive power awareness, will reduce the power consumption across the entire hierarchy of a system. In the architecture shown in Figure 4.3, the power consumption of the LNAs will be almost twice as much as a single LNA and the problem of sensitivity of gain of a second stage LNA due to poor reverse isolation of the passive mixer will remain unsolved.

Passive Mixer Baseband I Processing 0 o LNA 1 LNA 2 I Splitter Phase Shifter Baseband Processing Local Oscillator Bandpass Filter o (LO) Q 90 Baseband Q Processing Passive Mixer

RF Front-End

FIGURE 4.3. Block diagram of a direct conversion receiver with passive mixer and two LNAs.

In addition, in the front-end architecture shown in Figure 4.3, three on-chip RF matches are required. The first match is needed between the output of the first LNA and the input of the second LNA, the second match is needed between the output of the second LNA and mixer’s RF input, and the third match is required between the LO output and mixer’s LO input. One matching circuit often requires placement of on-chip passive components such as inductors that occupy a large area on-chip and will increase the chip cost significantly. Another drawback of on-chip inductors is their mutual coupling. Since LO leakage to the RF input is an issue in direct conversion receivers, a lower number of on- Chapter 4. Integrated RF Front-End Design Options 66

chip inductors is desirable to minimize the coupling of the LO signal to the LNA’s input and to the antenna.

A third alternative for the RF front-end is illustrated in Figure 4.4. In this approach, a dual-conversion to zero-IF is considered [66], where two cascaded active mixers are down converting the RF signal to zero-IF. The first mixer down converts the RF input signal to a high IF and then a second mixer translates the high IF to zero frequency. The main advantage of this architecture is that the flicker noise at the mixer output will not be an issue. An additional advantage of this approach is that none of the LO signals are set at the RF frequency. Therefore, LO leakage and its affects on the DC offsets will not be an issue.

The main drawback of this architecture is the need for two local oscillators. To stabilize the output frequencies of these oscillators, two complex phase locked loop (PLL) circuits are needed. The clock frequencies of the PLLs need an accurate crystal that is always implemented off-chip. In most of the receivers, the local oscillator and its associated PLL occupy a large area on-chip. Doubling the number of these blocks means increasing the chip area significantly.

In the architecture illustrated in Figure 4.4, the first active mixer is a power hungry block as explained in Section 2.2.1.2. However, having two cascaded active mixers in the front-end increases the power consumption of the receiver and for most of the wireless applications where the battery life time is a main concern, the dual conversion architecture may not be a practical solution. Chapter 4. Integrated RF Front-End Design Options 67

Active Mixer 1 Active Mixer 2 Intermediate Baseband I IF Filter Processing o o 0 LNA I 0 Splitter Baseband Processing Bandpass Filter Q Active Mixer 2 Baseband Intermediate Q IF Filter Processing o 90 Active Mixer 1

RF Front-End o 90

Phase Shifter Phase Shifter

Local Oscillator 1 Local Oscillator 2 (LO) (LO)

FIGURE 4.4. Block diagram of a dual direct conversion receiver.

Furthermore, design of the second active mixer will be very challenging due to dynamic range requirements. The reason is that, in cases when the input RF is a strong signal, after two amplification stages in the LNA and first active mixer, the down converted high IF signal may saturate the second mixer input circuitry. One way of evaluating the linearity of a receiver is by measuring the third order intermodulation intercept point (IIP3). For cascaded stages the IIP3 can be expressed as [66]

1 2 2 --- ()A × A 1 1 A 2 1 2 ------= ------++------1 ------(4.1) IIP3casc IIP31 IIP32 IIP33 where A1 and A2 are the gains of the first and second stages, respectively and IIP33 is the third order intercept point of the 3rd stage. Thus, to meet an IIP3 requirement for the cas- Chapter 4. Integrated RF Front-End Design Options 68

caded stages with two active blocks at the beginning, the third stage must meet the IIP33 requirement according to (4.1). It can be noted that in such a case, the required dynamic range for the third stage is higher compared to the first two stages.

For the above reasons, in this work, the RF front-end with the simplest architecture as shown in Figure 4.1 was selected. With the focus on the issues of direct conversion receiver, it will be more economical to solve them with circuit techniques rather than architectural alternatives. However, while it is more difficult to design the circuits with this architecture, it has the benefit of simplicity, lower power consumption, smaller chip area and the advantage of a high level of integration.

4.3 RF Front-End Selection for Low Voltage and Low Power Applications

Wireless communication devices must be designed with a mixture of analog, radio frequency (RF) and digital functionality, operating at the highest possible performance levels. Low power consumption and small chip area are also some important factors that must be considered in the design of devices for wireless applications [67]. Combining these requirements with wide-band needs makes the design of the RF front-end blocks even more challenging. RF blocks such as the LNA, mixer and VCO are the most power hungry blocks in any receiver, therefore any attempt to reduce the power of these blocks while increasing the performance level and bandwidth is very well spent.

However, the weight and physical volume determine whether a device be called “mobile”, it is the power consumption which is the major concern in the design of mobile wireless devices [68]. To reduce the time between the battery recharge, all sections of a wireless device, including RF, IF, baseband and digital signal processing (DSP) must be designed with minimum power consumption. Today different modulation and power management techniques are used to achieve this goal. In any transceiver, the architecture and Chapter 4. Integrated RF Front-End Design Options 69

circuit designs determine the instantaneous power consumption, but the average power depends on the power management technique and the modulation method used. Wireless devices for implantable biomedical equipment and remote sensor applications must con- sume very low power. This group of wireless devices need to operate at low voltages such as 0.9 V, which is the lower limit of useful life for most common batteries.

In a transceiver, the receiver section consumes less power than the transmitter section. However, the receiver will be switched ON for a longer time compared to the transmitter. Assuming that the RF front-end in a receiver has to drive an IF section with a real input Ω impedance of 100 k and at the signal level of 100 mVpp or lower, the maximum power

–3 3 –8 delivered by the front-end is then ()510× ⁄ ()100× 10 = 510× W. The power efficiency of the receiver RF front-end is generally very low and is around 0.01% [69]. Thus, it is worth studying methods to increase the front-end’s power efficiency to increase the battery life time. This section explores the fundamental limits on power dissipation of RF front-end blocks.

4.3.1 Power Consumption and Dynamic Range

The fundamental lower limit of the power consumption of an electronic circuit is determined by its performance. For blocks in a cascaded chain of an RF receiver, the most important parameter is spurious-free dynamic range. For any receiver, the spurious-free dynamic range can be evaluated by measuring the third order intercept point and noise floor at the output and then referring them back to the input to normalize for the receiver gain.

The minimum dynamic range in the input is limited by the integrated voltage noise spectral density across the channel bandwidth. To illustrate the effects of dynamic range in the input on the power consumption, a conventional differential pair with CMOS imple- Chapter 4. Integrated RF Front-End Design Options 70

mentation is shown in Figure 4.5, where two common source transistors are driven with balanced input signal voltages and output currents are differentially measured. The equivalent input noise voltage density is defined as [70]

2 4kTγ vn = ------. gm

i +1/2 V M - 1/2 Vin in M 1 2

FIGURE 4.5. CMOS differential pair.

The differential pair behaves like a perfect linear circuit if the CMOS transistors follow the pure square law characteristics in saturation region defined by

1 I = ---g V (4.2) D 2 m eff

where gm is the transconductance of the CMOS transistor. The Veff, often called the overdrive voltage, is defined by

≡ Veff VGS – VTH

where VGS and VTH are the CMOS transistor’s gate to source and threshold voltages,

respectively. Therefore to have a higher intercept point, the overdrive voltage Veff must be increased, which according to (4.3) will increase the current consumption. Chapter 4. Integrated RF Front-End Design Options 71

The maximum dynamic range is determined by amplitude of a large signal that satu- rates the circuit and distorts the gain. It is shown [71] that there is a trade-off between the gain, power dissipation and linearity, independent of circuit topology and power supply voltage. Assuming unilateral gains and matching for the RF front-end blocks, the power consumption can be approximated as

⋅⋅ PDC = kGIIP3 (4.3) where G is the power gain of the system and k is the linearity parameter, which depends on different factors such as IC technology and circuit topology. From (4.3) it can be noted that, in systems for very low power applications, the requirements on dynamic range must be more relaxed. Alternatively, in systems where the noise spectral density is large due to low bias current, by lowering the data rates and using narrow-band channels the system sensitivity may be improved.

4.3.2 Power Consumption and Frequency Range

The use of higher frequencies has resulted from a rapid increase of numbers of applications of wireless devices. Currently, cellular phones and other wireless devices are concentrated in the 1-5 GHz region. In the near future, this is going to change and most likely, these systems need to work over longer distances and at higher frequencies. If the wireless communication is held in far field and the polarization of the transmitter and receiver antennas are perfectly matched, the available signal power for a receiver with an omni- directional antenna can be written as [69]

λ α P = P G G ------(4.4) RX TX RX TX 4πd where PTX is the power applied to the transmit antenna, GRX and GTX are the gains of the receive and transmit antennas, d is the distance between transmit and receive antennas, λ Chapter 4. Integrated RF Front-End Design Options 72

is the wavelength and α is the propagation constant. The propagation constant α is 2 in free space and varies between 1.81 and 5.22 inside buildings [48]. Assuming that both antennas have constant gains, the receiver available power can be calculated by

P ≈ TX PRX K------α-. (4.5)  df⋅ where K is a constant factor.

According to (4.5), there are different ways to increase the available power in the receiver. One solution is to increase the transmitter power, which becomes impractical at frequencies higher than 5 GHz. Increasing the gain of antennas can not be a solution, because such antennas would be highly directional and for portable wireless communication it is not practical. Therefore, the only remaining solution is to split the frequency spectrum for short-range and high-range communications and use the high bandwidth and high data rate connections for short-range applications and limit the long range systems below 5 GHz [69].

As the upper frequency for long-range systems is limited to 5 GHz, in these systems low noise figure, high linearity and high power efficiency for most efficient use and reuse of the frequency spectrum is needed. In these systems the operating frequency will not be raised, therefore power consumption is mainly limited by the dynamic range requirements. However, in short-range systems, the power dissipation will be limited by the high frequency of operation. These systems will have relaxed specifications on linearity and sensitivity compared to the long-range systems. The power dissipation for short-range systems can be expressed as

γ PDC = Gf (4.6) γ where PDC is the DC power dissipation, G is the required power gain and is the dissipation per gain-bandwidth product, which depends on the circuit topology. The divergence Chapter 4. Integrated RF Front-End Design Options 73

of the frequency and specifications for short-range and long-range systems has already been done in wireless communication such as GSM (cellular system for long-range) and Bluetooth (short-range) systems. Table 4.1 highlights some of the requirements for these two systems.

TABLE 4.1. Linearity and sensitivity requirements for GSM and Bluetooth systems.

Wireless System GSM Bluetooth Frequency 950 MHz 2450 MHz Noise Figure (dB) 9 25

IIP3 (dBm) -10 -21

4.3.3 Power Consumption and Sensitivity

As described in Section 3.4.1, sensitivity of a receiver is mainly determined by the noise figure of the RF front-end. From the relation of gain and the NF given in Friis’ formula [44] the relationship between the noise figure and the power dissipation can be derived

NF – 1 NF – 1 NF – 1 ------2 ------3 … ------n NFtot = NF1 ++++… (4.7) G1 G1G2 G1G2 Gn – 1

NF – 1 NF – 1 γ 2 γ 2 Ptot = f 1 ------+ 1 Gtot ------(4.8) NFtot – NF1 NFtot – NF1

th where NFn and Gn are noise figure and gain of the n stage, respectively. Friis’ formula implies that to have a total noise figure close to the noise figure of the first stage a large gain is required in the first stage which requires larger power dissipation. However, it is Chapter 4. Integrated RF Front-End Design Options 74

impossible to improve the noise figure beyond the minimum noise figure of the active devices (NFmin).

There is a difference between the relationship of noise figure to the power dissipation in short-range and long-range systems. In long-range systems, linearity is one of the factors that determines the power dissipation as explained in Section 4.3.1. A large gain in the first stage of the receiver demands a larger linearity for the following stages and hence, higher power consumption. Therefore, design of RF front-end for long-range systems includes an indirect trade-off between the gain and noise figure. It is shown that the minimum power dissipation that can be achieved for two cascaded stages is equal to [69]

NF – 1 G ()NF – NF ()NF – NF 2 tot tot 1 2 1 Ptot = IIP3tot k1 ------+ 2 k1k2 ------+ NFtot – NF1 NFtot – NF1

NFtot – NF1 IIP3tot k2 Gtot ------. (4.9) NFtot – NF1

Equation (4.9) also indicates that power dissipation increases rapidly as the total noise figure becomes close to the noise figure of the first stage.

4.3.4 Power Consumption and Antenna Interface

The antenna interface includes losses in the antenna filter, switches and / or duplexer. However, while the antenna interface losses significantly affect the power consumption of the RF front-end, the losses are mostly neglected in the system designs. In order to main- tain the noise figure below the system requirement, any losses in the antenna interface must be compensated by decreasing the noise figure in the RF front-end. Furthermore, the overall gain of the front-end must be increased to keep the signal level as before. Increas- ing the gain of the RF blocks is not an easy task and results in more power dissipation. Chapter 4. Integrated RF Front-End Design Options 75

Since antenna interface losses reduce the signal level in the input, the IIP3 will decrease due to weaker signal level in the input.

4.3.5 Power Consumption and Circuit Designs

In short-range wireless services, the main challenge is designing circuits with high gain and low power consumption at high frequencies. Decreasing the transistor sizes that reduces the current consumption and increases the impedance level proportional to current, keeps the gain constant. However, decreasing the transistor sizes is limited by the IC technology, which does not allow further scaling. Therefore, as frequency increases the parasitics of the active and passive devices start to dominate and reduce the gain. In addition, increasing the internal impedance level makes the circuits excessively difficult to interface with off-chip devices due to limited impedance level of the components on a printed circuit board (PCB). Often a matching stage is required to interface the high level internal impedance and off-chip components. Any kind of matching, either with active or with passive components will result in a power dissipation or additional noise and distortion. On-chip matching with passive components will increase the chip area significantly and is not economical. Furthermore, the low quality (Q) factor of on-chip inductors and capacitors increases the noise figure. Off-chip matching circuit adds to the overall component count and depending on each PCB layout needs a redesign and re-evaluation.

4.3.6 Power Consumption and IC Technology

Many limitations imposed on the performance of electronic circuits are related to IC technology. Rapid advances in semiconductor technology demand that IC designers and process engineers work closely to understand each other’s conflicting design needs. For RF low power circuits an IC technology must be optimized such that achieving high gain- bandwidth products at low currents with small channel length (in case of CMOS transis- Chapter 4. Integrated RF Front-End Design Options 76

tors) or emitter area (in case of bipolar transistors) and small parasitics be possible. High quality passive components are also very important in lowering power dissipation of RF circuits. Dissipation-less passive components can also be used for matching of the low power circuits with the high impedance levels to the low impedance off-chip components.

For digital circuits it is possible to reduce the supply voltage and keep the scaling of the transistor sizes, however, for analog circuits this is more challenging [72]. It is very difficult to reduce the area of analog circuits and passive components in an IC technology. The voltage mismatch between transistors must be very low and with reduced area this is hard to achieve. The high accuracy or high quality factor for passive components requires a larger area. Design of analog RF circuits for low voltage applications causes degradation of signal to noise ratio (SNR) and distortion. The use of small scale transistors, which provide higher fT due to reliability issues, then becomes very challenging. 77

CHAPTER 5 Integrated Low Noise Amplifier Design

In previous chapters, the wireless standards and receiver architectures were described and the primary considerations for designing an integrated RF front-end were identified as, operating frequency, supply voltage, power dissipation, linearity, sensitivity and gain. In this chapter and subsequent chapters, the circuit level issues are explored in detail and parameters affecting the circuit design are examined.

In this section, design of low noise amplifiers are described with the emphasis on techniques that are suitable for integration in IC technologies. Following an overview of low voltage and low power challenges, the design of bipolar and CMOS LNAs are studied. Next different gain and noise optimization techniques are explored and general issues such as stability are discussed. Different LNA topologies such as differential architecture and single ended are studied and a state of the art design method of a wide-band LNA is introduced. Finally, the layout issues and impact of pads, ESD diodes, wirebonds, and package parasitics on the gain and noise figure of the LNA are analyzed.

5.1 Radio Frequency Low Noise Amplifier

A low noise amplifier (LNA) is often the first RF block in a receiver chain. The gain of this block can suppress the noise of the following cascaded stages, such as mixers and IF filters. The LNA gain can also have a major contribution in the overall gain of the receiver’s front-end and plays an important role in receiving weak input signals. Since the Chapter 5. Integrated Low Noise Amplifier Design 78

LNA is the first RF block in the receiver, it largely determines the noise figure of the system [10].

In LNA design, trade offs between many figures of merit such as power gain, noise figure, linearity and stability must be considered. Low power consumption is an additional constraint that further complicates the design process. Moreover, since the LNA receives the signal from an antenna, its input matching is a very important design issue.

TABLE 5.1. Typical acceptable characteristics of an LNA.

Parameter Acceptable value

Noise Figure 2 dB

IIP3 - 10 dBm

Power Gain 15 dB

Input Impedance 50 Ω

Input and Output Return Loss - 10 dB

Reverse Isolation 20 dB

Stability Factor > 1

In Table 5.1, typical acceptable values for the LNA are listed. It is very important to consider each parameter with its effect on the overall receiver performance based on the system requirements described in Chapter 3. For example, the gain of the LNA must be chosen based on the noise figure and linearity of the down-conversion mixer. If the gain of the LNA is chosen to be too low, the mixer’s noise figure will dominate the overall noise figure of the receiver, and if the gain is chosen to be too high, the RF signal at the input of the mixer will cause large intermodulation products [82] and distortion. Chapter 5. Integrated Low Noise Amplifier Design 79

The LNA is required to have a very low noise figure, which mandates using minimum number of active devices in the input stage. In addition, it is impossible to use active devices with high frequency resistive feedback in the input stage. Other LNA requirements such as input matching and linearity limit the acceptable topologies in each technology (bipolar or CMOS) to only a few. In the following subsection the most commonly used LNAs in each technology are studied.

5.1.1 CMOS LNAs

The most widely used LNA topologies in CMOS technology are common-gate and inductively degenerated cascode as illustrated in Figure 5.1 and 5.2, respectively.

VDD

L o

RFout V B M 1 C o

RFin

L in

FIGURE 5.1. Circuit diagram of a common-gate LNA.

Both of these topologies allow a high reverse isolation that helps with the LNA’s sta-

bility. If the input matching and noise requirements are met, the IIP3 of both the common- gate and cascode LNAs are typically better than -5 dBm. Therefore, in CMOS receiver Chapter 5. Integrated Low Noise Amplifier Design 80

implementation the linearity of the LNA will not be the limiting factor and the mixer and subsequent stages will limit the linearity of the receiver.

VDD

L T C T

RFout V B M 2

RF in M 1

L S

Z in

FIGURE 5.2. Circuit diagram of an inductively degenerated cascode LNA.

Matching of the input of the common-gate LNA is easier than the cascode LNA. The voltage gain (Av) of a common-gate LNA is equal to [68]

Q g Q Q ------i m o ------o Av ==ω ω (5.1) oC 50Qi oC where Qi and Qo are the input matching and resonant load quality factors, respectively, gm ω is the transcondutance of the transistor M1 and o is the angular frequency of operation.

The transconductance gm in the saturation region is defined as

2I µ ----W- ()------D µ ----W- gm ===nCoxVGS – VTH ()nCoxVeff . (5.2) L VGS – VTH L

In this dissertation, it is assumed that the circuit analyses are based on the transistor working in saturation region, unless it is mentioned otherwise. Chapter 5. Integrated Low Noise Amplifier Design 81

From (5.1) the voltage gain can be adjusted by either increasing the LNA current

(hence, increasing the gm) or by increasing the quality factors Qi and Qo. The Q factor with on-chip devices depends on the Q factor of the passive devices in the IC technology. Recently CMOS IC technologies included high Q factor inductors and capacitors on-chip. Assuming the common-gain LNA is driven by a source admittance of

YS = GS + jBS (5.3) where GS and BS are the real and imaginary part of the source admittance, respectively, the minimum noise figure of the LNA can be written as

()γ ⁄ NF = 1 + gm GS (5.4)

Here γ, the channel current noise factor, is a bias dependent factor that for long channel devices satisfies the inequality of

2 --- ≤≤γ 1 (5.5) 3

When the transistor is saturated, γ is equal to 2/3 and when the drain-source voltage is zero, it is equal to one. The inequality of (5.5) applies only to long channel transistors and for short channel transistors depending on the bias conditions, γ may be as high as two or three [71]. The excess noise in short channel devices may be caused by the presence of hot electrons in the channel [67].

If the LNA is perfectly impedance matched, i.e.; gm = GS , equation (5.4) can be simplified to

NF = 1 + γ (5.6)

For a long channel device operating in saturation, equation (5.6) predicts a NF of 2.2 dB. However, in practice other sources of noise degrade the NF substantially. Further- Chapter 5. Integrated Low Noise Amplifier Design 82

more, as the channel length in CMOS devices decreases, γ increases, which results in even higher NF [71].

In the cascode LNA shown in Figure 5.2, an inductive degeneration is incorporated to create a real part in the input impedance. Extensive analysis of the inductively degenerated cascode LNA are done by Andreani and Shaeffer [75- 76]. The small signal equivalent circuit of input stage of an inductively degenerated cascode LNA is illustrated in Figure 5.3.

G Rg RF-input I out

g Cgs mVgs S

L s

Z in

FIGURE 5.3. Small signal equivalent circuit of the input stage of an inductively degenerated cascode LNA.

If the parasitics capacitances of gate-drain and source-bulk and the small gate resistor

Rg of the input RF transistor M1 are ignored, the input impedance Zin can be written as

g L m S 1 Z ≈ ------1 - ++jL ω ------(5.7) in C t o jC ω gs1 gs1 o where C and g are the capacitance at the gate and transconductance of transistor gs1 m1

M1 respectively and Lt is the total inductor in the input. Cgs, the gate-source capacitance of the device in the saturation region is equal to Chapter 5. Integrated Low Noise Amplifier Design 83

2NWLC C = ------ox- + NWC . (5.8) gs 3 ov

where Cov is the overlap capacitance per unit width and N is the number of fingers (thus NW represents the total width of the transistor). To achieve an impedance match of the Ω input to a source with a 50 impedance, Lt is selected such that the last two terms in

equation (5.7) cancel each other and the current of the transistor M1 is set such that the following equation is satisfied

gm LS Z ===------1 - ω L 50Ω (5.9) in C T S gs1

ω where by definition the cutoff frequency T is the angular frequency, in which the small signal current gain of the device drops to one. For CMOS transistors, the cutoff frequency is equal to

g ------m fT = π(). 2 CGS + CGD

In the following sections it will be shown that in practical implementation of this LNA there are many other factors that affect the input impedance. Furthermore, the last two terms in (5.7) may not cancel each other at the frequency of interest and therefore, off- chip matching may be needed. As the frequency of operation increases, the required value

for LS becomes smaller and it may be possible to use the ground wirebonds as the degener-

ation inductor. For such a case the voltage gain of the transistor M1 is equal to

Voltage Gain= g Z (5.10) m1 L1

where Z is the load impedance seen at the drain of transistor M1. If transistor M2 were L1 not present, the voltage gain would be defined mainly by the LC tank and the parasitic Chapter 5. Integrated Low Noise Amplifier Design 84

capacitors of the transistor M1 at the drain. With M2 present, the output impedance of the cascode transistor g , plays an important role in the voltage gain of the LNA. do2

The small signal equivalent circuit of the LNA for noise analysis is illustrated in Fig- ure 5.4. The degeneration inductor Ls in the source of the M1 is also included in this figure. The parasitic resistance of the gate, body, source and drain terminal are ignored in the interests of simplicity. Also the effects of the common gate transistor M2 on the noise and frequency response are neglected. In this section, a simple treatment of noise analysis, for a common source LNA, which is used in most research [75-79], is presented and a more detailed discussion is given in the following sections when the noise figure is derived with the impacts of ESD diodes, pad, wirebonds and package parasitics [83]. The noise factor of the LNA is defined as the total output noise divided by total output noise due to the source [76].

i n, R out Lg

Cgs Rg in, g gm Vgs in, d io, R s R s Ls

FIGURE 5.4. Equivalent small signal circuit of input stage of an inductively degenerated common source CMOS LNA.

In Figure 5.4, in, d represents the mean squared channel thermal current defined as

2 γ ∆ ind, = 4kT gdo f (5.11) Chapter 5. Integrated Low Noise Amplifier Design 85

where k is the Boltzman constant, T is the absolute temperature, ∆f is the bandwidth. The mean squared gate induced noise current is given by [83]

2 β ∆ ing, = 4kT Rg f . (5.12)

In equation (5.12), β is a constant factor, which is almost equal to 0.27 for long channel transistors. It is written as a variable in equation (5.12) to account for a possible adjustment due to short channel effects. In (5.12) Rg represents the gate distributed resistance and at the resonance is equal to [83]

5g R = ------do . (5.13) g ω2 2 o Cgs

The transfer functions of the four noise sources in the output current in,out of the small signal model of Figure 5.4 at the resonance frequency are

g ------m - inoR,, = ω inR, (5.14) s 2 oCgs

ω jRs oCgs – 1 i ,, = g ⋅ ------⋅ i , (5.15) nog m ω2 2 ng 2Rs oCgs

2 ∆ ind, = 4kT gnd f (5.16)

i ,, = i , (5.17) noRout nRout

where the theoretical value of the transconductance gnd depends on the transistor model which has been used. The drain current in the simplest model for long channel devices is given by Shichmann-Hodges as [42] Chapter 5. Integrated Low Noise Amplifier Design 86

µ C W 2 I = ------n ox -()V – V ()1 + λV (5.18) D 2L GS TH DS

λ where represents the relative variation in length for a given increase in VDS. In this model the gdn can be written as [82]

2 g = ---g ≡ γg (5.19) dn 3 do do

When the common source transistor is in saturation, its gdo is equal to its gm. There-

2 fore the expression for ind, can be simplified as

2 γ ∆ ind, = 4kT gm f . (5.20)

The total output noise power density is the sum of (5.14)-(5.17). Assuming a 1 Hz bandwidth the noise factor at the resonance frequency can be shown to be given by [75]

2 g γ γ β β 2 1 2 m ' ' 1 1Q + --- P ------+ --- gdn ------cP 4 g 4 4 1 F = 1 +++------dn ------(5.21) 2 2 2 2 R Q g 2 R R Q g S m RsQ gm s out m

1 C ------γ γ ------gs where Q = ω is the quality factor of the input stage, ' = Ab , P = , Ab is 2Rs oCgs Ct bulk charge factor and Ct is the total capacitor in the gate.

In the industry, the common source topology is used more often than the common- gate topology. The reason is that the common source LNA offers a lower noise figure than the common-gate LNA. Moreover, a common source LNA has a better reverse isolation compared to the common-gate LNA. This is because the transistor M2 in the circuit shown in Figure 5.2, acts as a common-gate transistor and reduces the Miller affect. The drawback of the common source LNA is the need for off-chip matching components. Chapter 5. Integrated Low Noise Amplifier Design 87

However, as it will be shown later there are many additional factors that affect the impedance of the input stage of the LNA. Since the goal of this work is to design front-end blocks suitable for real life applications with performance compared to the devices available in the industry, the common source LNA was selected for the integrated circuit design.

5.1.2 Bipolar LNAs

Bipolar LNAs were the first generation of LNAs implemented in integrated circuits.

Higher gain, higher fT (about twice compared to the NMOS transistors) and a lower noise figure are the main advantages of using bipolar transistors in RFIC circuits, especially in RF front-ends. However, bipolar transistors occupy a substantially larger area on-chip than CMOS transistors and for the baseband section where millions of transistors are required, bipolar transistors are not an economical solution. Furthermore, in digital circuits, where transistors are either in ON or OFF mode, CMOS transistors are an excellent choice due to their fast switching time.

Today the complete digital and baseband sections of a wireless receiver are implemented with CMOS transistors. In recent years, different IC technologies, such as SiGe BiCMOS offer implementation of both bipolar and CMOS transistors on a single chip. Although, these technologies are more expensive compared to CMOS technologies, they offer advantages of using bipolar devices for RF section and therefore, allow implementation of a system on chip (SoC).

Similar to CMOS LNAs, there are two topologies that are widely used in bipolar technology as: common-emitter LNA and common-base LNA. To understand the limitations of bipolar LNAs, first a simple common-emitter stage, illustrated in Figure 5.5, is analyzed. Chapter 5. Integrated Low Noise Amplifier Design 88

V CC V CC

I in I 1 R L R 2 R 1 Q Q 2 1

R S L e

V S

Zin

FIGURE 5.5. Circuit diagram of a common-emitter bipolar LNA.

In this circuit the current source Iin and transistor Q2 define the bias current I1(or the collector current IC) of transistor Q1. Resistor R1 isolates the main transistor Q1 from the

noise of the bias section and transistor Q2, and if its value is sufficiently greater than RS (the source impedance), then the effects of the bias circuit noise on the noise figure of the

LNA can be ignored. The voltage drop across R2 keeps the voltages at the bases of transistors Q1 and Q2 equal, allowing almost perfect current mirroring. The input impedance of

the LNA (shown in Figure 5.5) with base resistance rb and transconductance gm for Q1 can be written as

g L ------m e ω ------1 - Zin = ++rb j oLe +ω (5.22) Cπ j oCπ

where Cπ is the base emitter capacitance of the transistor Q1 defined as

Cπ = Cb + Cje (5.23) Chapter 5. Integrated Low Noise Amplifier Design 89

where Cb and Cje are the base charging and the emitter base depletion layer capacitances, respectively. The transconductance gm of a bipolar transistor in the active region, is defined as [84]

dIC qIC gm ==------. (5.24) dVBE kT where q is the charge of an electron.

The transconductance of the input stage of the LNA at the resonant frequency can be written as [85]

i 1 G = ------out ≈ ------. (5.25) m ω L VS o e

The voltage gain of the common emitter LNA can therefore be derived as

Z ()jω ()ω ≈ ------L o- Av = GmZL j o ω (5.26) oLe

For noise analysis, a bipolar transistor in the active region can be modeled as a noise- less transistor with a voltage and a current noise source in the base as illustrated in Figure 5.6 [85]. The equivalent input voltage noise of a bipolar transistor for a 1 Hz bandwidth is given by [10]-[84]

2() 1 Vi f = 4kT rb + ------. (5.27) 2gm

2 (f) V i

Q 1

2 (f) I i

FIGURE 5.6. Circuit diagram of bipolar transistor noise model. Chapter 5. Integrated Low Noise Amplifier Design 90

In (5.27) the first term is due to the base resistor and the second term is due to collector current shot noise referred back to the input. The equivalent input current noise for a 1

Hz bandwidth of a bipolar transistor with base current IB can be written as

2 AI I I ()f = 2qI++------B------C (5.28) i B 2 f β()f where the first term in (5.28) is the base current shot noise, the second term is the flicker (1/f) noise and the third term is the input referred collector current shot noise. A is a constant that depends on the device properties. The collector current shot noise is often β ignored in the analysis for the interest of simplicity. is the current gain of the transistor

Q1 at low frequencies. The equivalent small signal circuit of input stage of a common emitter LNA for noise figure analysis is shown in Figure 5.7. The impact of the degeneration inductor in the emitter of the Q1 is not shown in Figure 5.7, and has been neglected in the analysis. The base resistor rb is a physical resistor and therefore has thermal noise. The collector resistor rc also produces thermal noise, but because it is in series with high impedance collector node, its noise contribution is negligible and thus, it is not included in small signal analysis. The resistor rπ shown in Figure 5.7, is a fictitious resistor and is used for modeling purposes and does not exhibit thermal noise.

2 2 L VLin Vrb in RLin rb I 1 +

Vπ 2 r π 2 R i Cπ g mVπ i c s b _

2 Vs

FIGURE 5.7. Equivalent small signal circuit of the input stage of a common emitter LNA. Chapter 5. Integrated Low Noise Amplifier Design 91

In Figure 5.7, RLin represents the series resistance of the input inductor Lin that is used for matching. For the un-packaged LNA the noise figure can be written as [86]

2 2 2 R r g R 1 fT g R fT 4R fo ------Lin------b------m S ------------m S ------S ---- NF = 1 ++++β β ++ (5.29) RS RS 2 2gmRS fo 2 fo RL fT where RL is the equivalent load resistance and fT is the frequency of the unity current gain

of the transistor Q1. The resonance frequency at the perfect matching in the input can be written as

1 f = ------. (5.30) o π 2 LinCπ

Generally in bipolar transistors the noise due to rb dominates as (5.29) indicates. The major way to improve the noise is to minimize the base resistance by using a larger transistor or by combining a number of transistors. This solution, however, increases the total parasitic capacitance at the input stage.

Another alternative for bipolar LNAs is a common base topology, illustrated in Figure 5.8. The main advantage of the common base topology compared to the common source architecture is the simpler input matching. Furthermore, a common base LNA has a higher linearity and better reverse isolation. However, a common base LNA exhibits a relatively high noise figure, and therefore is not suitable for applications that require high sensitivity in the input. Chapter 5. Integrated Low Noise Amplifier Design 92

V CC

R L

V out

V Q B 1

V in R I S in

FIGURE 5.8. Circuit diagram of a common base LNA.

5.2 LNA’s Stability

An important objective in the design of LNAs is to avoid even potential instability. Thus, the goal is to design a circuit that is stable under all input signal conditions and for all ranges of component values. The practical realization of integrated RFIC and analog circuits and systems is very complicated because physical circuit components such as resistors, capacitors and active devices deviate from their nominal values due to a variety of statistical and deterministic effects. Furthermore, circuit components can and will deviate from their normal values due to statistical manufacturing errors, aging and temperature [87]. Therefore, it is important to consider these factors and design the LNA such that it stays unconditionally stable or absolutely stable under any or all of these conditions.

Since the small signal model of all active devices include a feedback from output to the input, the LNA may become unstable for certain combinations of source and load impedances. A potential unstable active device can be unconditionally stable by either resistive loading or by adding a negative feedback. Since both of these solutions result in a degradation of power gain, noise figure and so on, generally they are not used in the nar- Chapter 5. Integrated Low Noise Amplifier Design 93

row band LNA design [88]. However, the feedback paths present in the model of active devices are not the only reasons that may cause instability. The ac ground and supply loops resulting from bond wire inductors may create a feedback loop and hence, oscillation. At high frequencies, such as 1-5 GHz even inductors of a few nH may provide sufficient coupling between input and output of the LNA to cause instability.

Γ < In microwave engineering a network is unconditionally stable if in 1 and Γ < Γ < Γ < out 1 , for all passive source and load impedances i. e., S 1 and L 1 , where Γ is the reflection coefficient. Alternatively, a constant used to define stability of an amplifier is the Stern stability factor which is defined as

2 2 2 1 – S – S + ∆ K = ------11 22 (5.31) 2 S12S21

∆ ∆ < where = S11S22 – S12S21 . If 1 and K >1, then the circuit is unconditionally stable for any combination of load and source impedances [48]- [89]. By combining K and ∆ a new parameter µ is derived that can be used to define the stability as

2 1 – S µ = ------11 (5.32) ∗∆ S22 – S11 + S21S12

Therefore, if µ is greater than one, the LNA is unconditionally stable and larger values of µ imply greater stability. Equation (5.31) suggests that stability of the LNA improves as S12 decreases which means the reverse isolation of the circuit increases. Fur- thermore, as (5.31) indicates stability of the LNA can be improved as S11 and S22 decrease, by providing a better matching in the input and output. Although achieving a high gain is a desirable factor in the LNA design, (5.31) suggests that increasing the gain significantly may cause oscillation. Thus, it may be worth to reduce the gain by a certain amount until unconditional stability condition is satisfied. Chapter 5. Integrated Low Noise Amplifier Design 94

However, K is a pessimistic measure of stability since it allows variation of the source and load impedances. If the load impedance of the LNA is well defined, for example in the direct conversion architecture, then it can be shown that the LNA is stable by ensuring that the real part of input impedance remains positive at all frequencies [10].

In the practical implementations of the LNA on an integrated circuit, a good number of ground pads are recommended to reduce wire bond inductor coupling. Furthermore, as (5.31) suggests, K is a function of frequency, therefore unconditional stability of the LNA must be exercised in a wide range of frequencies and not only the band of interest. The reason is that, the input RF signal may contain very high or very low frequency components, thus, although the LNA’s simulation may indicate stability in the desired frequency, these unwanted interferers may cause the circuit to oscillate. In the industry a higher band of 3-5 times the frequency of interest is recommended and for lower band generally very low IF frequencies of 10-100 kHz is used. Therefore, for an LNA with its desired frequency about 1 GHz, the stability test should be exercised over a range of 10 kHz up to 5 GHz.

5.3 Broadband LNA Design

The fast growth of wireless systems demands wide bandwidth circuits for certain applications. These wireless systems require a broadband LNA in the front-end. The architectures studied in the preceding sections, in particular the cascode architecture, mostly were focused on narrow-band LNAs. Researchers introduced different techniques to increase the bandwidth of these architectures by proposing different methods to provide broadband matching [90] or by using a single transistor LNA (instead of cascode architecture) and increasing the number of stages to provide higher gain [91]. De-queing the output resonant tank inductor is also proposed to increase output bandwidth of the LNA [93]. In this approach an additional stage has been added to compensate for the degradation of the Chapter 5. Integrated Low Noise Amplifier Design 95

power gain in the first stage. As explained in Section 4.2, drawbacks of implementing two LNAs on chip are higher power dissipation, larger chip area, a greater number of components on chip and the requirement for additional matching stage between the two LNAs.

It will be shown in Chapter 8 that it is possible to achieve a broadband design without increasing the number of stages. By shifting the resonant frequency of the tank to higher than fo and shifting the minimum of S11 by adjusting the input stage matching to lower than fo, a broadband design can be achieved. However, to satisfy the matching requirement a broadband matching [90] will be required in the input stage as well.

5.4 Dual-Band LNA Design

For certain wireless applications, a dual-band transceiver is needed to provide more bandwidth and flexibility. Dual-band transceivers are used to increase the performance of these systems by switching between two different bands to receive one band at a time [93]. One way of implementing dual-band front-end is to design two LNAs operating in two different frequencies and switch them On and Off depending on the frequency of interest. This approach requires two different designs, occupies a larger area on chip and needs implementation of switches, which add extra constraints and noise into the RF front-end.

An alternative approach to the LNA design is illustrated in Figure 5.9, where two tuning resonator tanks are implemented in the load. A reported LNA with two tanks in the load achieved a gain of 14 dB at 2.45 GHz band and 15.5 at 5.25 GHz band [93]. The drawback of this architecture is the need for two inductors in the load and hence, increased chip area. The performance parameters of the LNA, such as gain and output matching with this type of load will be very sensitive to the mutual inductance between the two inductors. Furthermore, the layout diagram of this circuit will be complicated and will contain extra transmission line effects due to the long metal lines needed for interconnec- tion between the inductors. Chapter 5. Integrated Low Noise Amplifier Design 96

VDD

L 2

C C 2 1 L 1 I B

RFout

M 2 C O

C G

R 1 M 3 M 1

RFin

FIGURE 5.9. Circuit diagram of a dual-band CMOS LNA.

An alternative approach for the dual-band LNA is illustrated in Figure 5.10. In this circuit, changing the bandwidth is done by turning On or Off the PMOS switches M4 and

M5. Although, in this LNA extra control voltages are required to turn the PMOS switches On or Off, the implementation would be very easy since there are other digital control switches available on-chip and the addition of two control bits will not add much complexity. When the PMOS switches are Off, the tank’s resonance frequency can be written as

1 ------fo = π . (5.33) 2 LT C1

With PMOS switches both being On the resonance frequency is modified to Chapter 5. Integrated Low Noise Amplifier Design 97

------1 fo = π (5.34) 2 LT CT where CT is the total capacitance in the tank i. e., CT = C1 ++C2 C3 .

VDD

C C 1 2 C 3 L T VB1 VB2 M 4 M 5

I B

RFout

M 2 C O

C G

R 1 M 3 M 1

RFin

FIGURE 5.10. Circuit diagram of a dual-band cascode LNA with PMOS switches in the load.

5.5 Fully Differential LNA Design

Generally in the RF front-end, a double balance structure is selected for the down conversion mixer due to its power handling capability, broader bandwidth, higher LO to RF isolation and spurious signals suppression of even harmonics of the RF and LO signals. In the direct conversion receiver, the prevention of LO feed through and the suppression of even harmonics are desirable, but requires the implementation of a double balance architecture for the mixer. If any of the LNAs studied in the preceding sections is used in the front-end Chapter 5. Integrated Low Noise Amplifier Design 98

of the receiver, its single ended output has to be converted to fully differential before connecting it to the mixer. This approach requires extra passive components which will affect the power gain. An alternative approach is to use a fully differential architecture as illustrated in Figure 5.11. As Figure 5.11 suggests, a fully differential circuit needs an additional tank and hence, an additional on-chip inductor that occupies a large area. In recent years, advanced IC technologies offer symmetric inductors as well, hence, it becomes possible to implement the load resonator with a symmetric inductor. However, the area of the symmetric inductor follows this inequality

A <

Furthermore, the current consumption of a differential LNA is twice compared to a single ended LNA. Moreover, most of the time output of antennas are single ended, therefore, a single ended to differential transformation is required in the input stage. Differen- tial stages require matching in both inputs which increases the number of components and the cost of a receiver.

VDD

L C C T L T T T

_ RF + RF out out C M 2 C O O M 2 I C C B 1 1

R 1 M 3 M 1 M 1 + RFin _ RFin

R 1

FIGURE 5.11. Circuit diagram of a fully differential cascode LNA. Chapter 5. Integrated Low Noise Amplifier Design 99

5.6 Gain and Noise Optimization Techniques

In the past, researchers [73-76] paid a great deal of attention to noise figure optimization techniques of an inductively degenerated common source LNA. Recent research into the design of LNAs have focused on the optimization of noise figure and input matching [75- 80]. Generally, the main objective in LNA design is to achieve simultaneous noise and input matching (SNIM) for a given power consumption. The main design techniques that have been reported to satisfy these goals are [77]:

• Classical noise matching (CNM) technique [94]

• Simultaneous noise and input matching (SNIM) technique [95]