Using Arm Scalable Vector Extension to Optimize OPEN MPI
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Vectorization Optimization
Vectorization Optimization Klaus-Dieter Oertel Intel IAGS HLRN User Workshop, 3-6 Nov 2020 Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. *Other names and brands may be claimed as the property of others. Changing Hardware Impacts Software More Cores → More Threads → Wider Vectors Intel® Xeon® Processor Intel® Xeon Phi™ processor 5100 5500 5600 E5-2600 E5-2600 E5-2600 Platinum 64-bit E5-2600 Knights Landing series series series V2 V3 V4 8180 Core(s) 1 2 4 6 8 12 18 22 28 72 Threads 2 2 8 12 16 24 36 44 56 288 SIMD Width 128 128 128 128 256 256 256 256 512 512 High performance software must be both ▪ Parallel (multi-thread, multi-process) ▪ Vectorized *Product specification for launched and shipped products available on ark.intel.com. Optimization Notice Copyright © 2020, Intel Corporation. All rights reserved. 2 *Other names and brands may be claimed as the property of others. Vectorize & Thread or Performance Dies Threaded + Vectorized can be much faster than either one alone Vectorized & Threaded “Automatic” Vectorization Not Enough Explicit pragmas and optimization often required The Difference Is Growing With Each New 130x Generation of Threaded Hardware Vectorized Serial 2010 2012 2013 2014 2016 2017 Intel® Xeon™ Intel® Xeon™ Intel® Xeon™ Intel® Xeon™ Intel® Xeon™ Intel® Xeon® Platinum Processor Processor Processor Processor Processor Processor X5680 E5-2600 E5-2600 v2 E5-2600 v3 E5-2600 v4 81xx formerly codenamed formerly codenamed formerly codenamed formerly codenamed formerly codenamed formerly codenamed Westmere Sandy Bridge Ivy Bridge Haswell Broadwell Skylake Server Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. -
Pwny Documentation Release 0.9.0
pwny Documentation Release 0.9.0 Author Nov 19, 2017 Contents 1 pwny package 3 2 pwnypack package 5 2.1 asm – (Dis)assembler..........................................5 2.2 bytecode – Python bytecode manipulation..............................7 2.3 codec – Data transformation...................................... 11 2.4 elf – ELF file parsing.......................................... 16 2.5 flow – Communication......................................... 36 2.6 fmtstring – Format strings...................................... 41 2.7 marshal – Python marshal loader................................... 42 2.8 oracle – Padding oracle attacks.................................... 43 2.9 packing – Data (un)packing...................................... 44 2.10 php – PHP related functions....................................... 46 2.11 pickle – Pickle tools.......................................... 47 2.12 py_internals – Python internals.................................. 49 2.13 rop – ROP gadgets........................................... 50 2.14 shellcode – Shellcode generator................................... 50 2.15 target – Target definition....................................... 79 2.16 util – Utility functions......................................... 80 3 Indices and tables 83 Python Module Index 85 i ii pwny Documentation, Release 0.9.0 pwnypack is the official CTF toolkit of Certified Edible Dinosaurs. It aims to provide a set of command line utilities and a python library that are useful when playing hacking CTFs. The core functionality of pwnypack -
Protecting Million-User Ios Apps with Obfuscation: Motivations, Pitfalls, and Experience
Protecting Million-User iOS Apps with Obfuscation: Motivations, Pitfalls, and Experience Pei Wang∗ Dinghao Wu Zhaofeng Chen Tao Wei [email protected] [email protected] [email protected] [email protected] The Pennsylvania State The Pennsylvania State Baidu X-Lab Baidu X-Lab University University ABSTRACT ACM Reference Format: In recent years, mobile apps have become the infrastructure of many Pei Wang, Dinghao Wu, Zhaofeng Chen, and Tao Wei. 2018. Protecting popular Internet services. It is now fairly common that a mobile app Million-User iOS Apps with Obfuscation: Motivations, Pitfalls, and Experi- ence. In ICSE-SEIP ’18: 40th International Conference on Software Engineering: serves a large number of users across the globe. Different from web- Software Engineering in Practice Track, May 27–June 3, 2018, Gothenburg, based services whose important program logic is mostly placed on Sweden. ACM, New York, NY, USA, 10 pages. https://doi.org/10.1145/3183519. remote servers, many mobile apps require complicated client-side 3183524 code to perform tasks that are critical to the businesses. The code of mobile apps can be easily accessed by any party after the software is installed on a rooted or jailbroken device. By examining the code, skilled reverse engineers can learn various knowledge about the 1 INTRODUCTION design and implementation of an app. Real-world cases have shown During the last decade, mobile devices and apps have become the that the disclosed critical information allows malicious parties to foundations of many million-dollar businesses operated globally. abuse or exploit the app-provided services for unrightful profits, However, the prosperity has drawn many malevolent attempts to leading to significant financial losses for app vendors. -
Vegen: a Vectorizer Generator for SIMD and Beyond
VeGen: A Vectorizer Generator for SIMD and Beyond Yishen Chen Charith Mendis Michael Carbin Saman Amarasinghe MIT CSAIL UIUC MIT CSAIL MIT CSAIL USA USA USA USA [email protected] [email protected] [email protected] [email protected] ABSTRACT Vector instructions are ubiquitous in modern processors. Traditional A1 A2 A3 A4 A1 A2 A3 A4 compiler auto-vectorization techniques have focused on targeting single instruction multiple data (SIMD) instructions. However, these B1 B2 B3 B4 B1 B2 B3 B4 auto-vectorization techniques are not sufficiently powerful to model non-SIMD vector instructions, which can accelerate applications A1+B1 A2+B2 A3+B3 A4+B4 A1+B1 A2-B2 A3+B3 A4-B4 in domains such as image processing, digital signal processing, and (a) vaddpd (b) vaddsubpd machine learning. To target non-SIMD instruction, compiler devel- opers have resorted to complicated, ad hoc peephole optimizations, expending significant development time while still coming up short. A1 A2 A3 A4 A1 A2 A3 A4 A5 A6 A7 A8 As vector instruction sets continue to rapidly evolve, compilers can- B1 B2 B3 B4 B5 B6 B7 B8 not keep up with these new hardware capabilities. B1 B2 B3 B4 In this paper, we introduce Lane Level Parallelism (LLP), which A1*B1+ A3*B3+ A5*B5+ A7*B8+ captures the model of parallelism implemented by both SIMD and A1+A2 B1+B2 A3+A4 B3+B4 A2*B2 A4*B4 A6*B6 A7*B8 non-SIMD vector instructions. We present VeGen, a vectorizer gen- (c) vhaddpd (d) vpmaddwd erator that automatically generates a vectorization pass to uncover target-architecture-specific LLP in programs while using only in- Figure 1: Examples of SIMD and non-SIMD instruction in struction semantics as input. -
Exploiting Automatic Vectorization to Employ SPMD on SIMD Registers
Exploiting automatic vectorization to employ SPMD on SIMD registers Stefan Sprenger Steffen Zeuch Ulf Leser Department of Computer Science Intelligent Analytics for Massive Data Department of Computer Science Humboldt-Universitat¨ zu Berlin German Research Center for Artificial Intelligence Humboldt-Universitat¨ zu Berlin Berlin, Germany Berlin, Germany Berlin, Germany [email protected] [email protected] [email protected] Abstract—Over the last years, vectorized instructions have multi-threading with SIMD instructions1. For these reasons, been successfully applied to accelerate database algorithms. How- vectorization is essential for the performance of database ever, these instructions are typically only available as intrinsics systems on modern CPU architectures. and specialized for a particular hardware architecture or CPU model. As a result, today’s database systems require a manual tai- Although modern compilers, like GCC [2], provide auto loring of database algorithms to the underlying CPU architecture vectorization [1], typically the generated code is not as to fully utilize all vectorization capabilities. In practice, this leads efficient as manually-written intrinsics code. Due to the strict to hard-to-maintain code, which cannot be deployed on arbitrary dependencies of SIMD instructions on the underlying hardware, hardware platforms. In this paper, we utilize ispc as a novel automatically transforming general scalar code into high- compiler that employs the Single Program Multiple Data (SPMD) execution model, which is usually found on GPUs, on the SIMD performing SIMD programs remains a (yet) unsolved challenge. lanes of modern CPUs. ispc enables database developers to exploit To this end, all techniques for auto vectorization have focused vectorization without requiring low-level details or hardware- on enhancing conventional C/C++ programs with SIMD instruc- specific knowledge. -
Anatomy of Cross-Compilation Toolchains
Embedded Linux Conference Europe 2016 Anatomy of cross-compilation toolchains Thomas Petazzoni free electrons [email protected] Artwork and Photography by Jason Freeny free electrons - Embedded Linux, kernel, drivers - Development, consulting, training and support. http://free-electrons.com 1/1 Thomas Petazzoni I CTO and Embedded Linux engineer at Free Electrons I Embedded Linux specialists. I Development, consulting and training. I http://free-electrons.com I Contributions I Kernel support for the Marvell Armada ARM SoCs from Marvell I Major contributor to Buildroot, an open-source, simple and fast embedded Linux build system I Living in Toulouse, south west of France Drawing from Frank Tizzoni, at Kernel Recipes 2016 free electrons - Embedded Linux, kernel, drivers - Development, consulting, training and support. http://free-electrons.com 2/1 Disclaimer I I am not a toolchain developer. Not pretending to know everything about toolchains. I Experience gained from building simple toolchains in the context of Buildroot I Purpose of the talk is to give an introduction, not in-depth information. I Focused on simple gcc-based toolchains, and for a number of examples, on ARM specific details. I Will not cover advanced use cases, such as LTO, GRAPHITE optimizations, etc. I Will not cover LLVM free electrons - Embedded Linux, kernel, drivers - Development, consulting, training and support. http://free-electrons.com 3/1 What is a cross-compiling toolchain? I A set of tools that allows to build source code into binary code for -
Introduction on Vectorization
C E R N o p e n l a b - Intel MIC / Xeon Phi training Intel® Xeon Phi™ Product Family Code Optimization Hans Pabst, April 11th 2013 Software and Services Group Intel Corporation Agenda • Introduction to Vectorization • Ways to write vector code • Automatic loop vectorization • Array notation • Elemental functions • Other optimizations • Summary 2 Copyright© 2012, Intel Corporation. All rights reserved. 4/12/2013 *Other brands and names are the property of their respective owners. Parallelism Parallelism / perf. dimensions Single Instruction Multiple Data • Across mult. applications • Perf. gain simply because • Across mult. processes an instruction performs more works • Across mult. threads • Data parallel • Across mult. instructions • SIMD (“Vector” is usually used as a synonym) 3 Copyright© 2012, Intel Corporation. All rights reserved. 4/12/2013 *Other brands and names are the property of their respective owners. History of SIMD ISA extensions Intel® Pentium® processor (1993) MMX™ (1997) Intel® Streaming SIMD Extensions (Intel® SSE in 1999 to Intel® SSE4.2 in 2008) Intel® Advanced Vector Extensions (Intel® AVX in 2011 and Intel® AVX2 in 2013) Intel Many Integrated Core Architecture (Intel® MIC Architecture in 2013) * Illustrated with the number of 32-bit data elements that are processed by one “packed” instruction. 4 Copyright© 2012, Intel Corporation. All rights reserved. 4/12/2013 *Other brands and names are the property of their respective owners. Vectors (SIMD) float *restrict A; • SSE: 4 elements at a time float *B, *C; addps xmm1, xmm2 • AVX: 8 elements at a time for (i=0; i<n; ++i) { vaddps ymm1, ymm2, ymm3 A[i] = B[i] + C[i]; • MIC: 16 elements at a time } vaddps zmm1, zmm2, zmm3 Scalar code computes the above b1 with one-element at a time. -
Cross-Compiling Linux Kernels on X86 64: a Tutorial on How to Get Started
Cross-compiling Linux Kernels on x86_64: A tutorial on How to Get Started Shuah Khan Senior Linux Kernel Developer – Open Source Group Samsung Research America (Silicon Valley) [email protected] Agenda ● Cross-compile value proposition ● Preparing the system for cross-compiler installation ● Cross-compiler installation steps ● Demo – install arm and arm64 ● Compiling on architectures ● Demo – compile arm and arm64 ● Automating cross-compile testing ● Upstream cross-compile testing activity ● References and Package repositories ● Q&A Cross-compile value proposition ● 30+ architectures supported (several sub-archs) ● Native compile testing requires wide range of test systems – not practical ● Ability to cross-compile non-natively on an widely available architecture helps detect compile errors ● Coupled with emulation environments (e.g: qemu) testing on non-native architectures becomes easier ● Setting up cross-compile environment is the first and necessary step arch/ alpha frv arc microblaze h8300 s390 um arm mips hexagon score x86_64 arm64 mn10300 unicore32 ia64 sh xtensa avr32 openrisc x86 m32r sparc blackfin parisc m68k tile c6x powerpc metag cris Cross-compiler packages ● Ubuntu arm packages (12.10 or later) – gcc-arm-linux-gnueabi – gcc-arm-linux-gnueabihf ● Ubuntu arm64 packages (13.04 or later) – use arm64 repo for older Ubuntu releases. – gcc-4.7-aarch64-linux-gnu ● Ubuntu keeps adding support for compilers. Search Ubuntu repository for packages. Cross-compiler packages ● Embedded Debian Project is a good resource for alpha, mips, -
Advanced Parallel Programming II
Advanced Parallel Programming II Alexander Leutgeb, RISC Software GmbH RISC Software GmbH – Johannes Kepler University Linz © 2016 22.09.2016 | 1 Introduction to Vectorization RISC Software GmbH – Johannes Kepler University Linz © 2016 22.09.2016 | 2 Motivation . Increasement in number of cores – Threading techniques to improve performance . But flops per cycle of vector units increased as much as number of cores . No use of vector units wasting flops/watt . For best performance – Use all cores – Efficient use of vector units – Ignoring potential of vector units is so inefficient as using only one core RISC Software GmbH – Johannes Kepler University Linz © 2016 22.09.2016 | 3 Vector Unit . Single Instruction Multiple Data (SIMD) units . Mostly for floating point operations . Data parallelization with one instruction – 64-Bit unit 1 DP flop, 2 SP flop – 128-Bit unit 2 DP flop, 4 SP flop – … . Multiple data elements are loaded into vector registers and used by vector units . Some architectures have more than one instruction per cycle (e.g. Sandy Bridge) RISC Software GmbH – Johannes Kepler University Linz © 2016 22.09.2016 | 4 Parallel Execution Scalar version works on Vector version carries out the same instructions one element at a time on many elements at a time a[i] = b[i] + c[i] x d[i]; a[i:8] = b[i:8] + c[i:8] * d[i:8]; a[i] a[i] a[i+1] a[i+2] a[i+3] a[i+4] a[i+5] a[i+6] a[i+7] = = = = = = = = = b[i] b[i] b[i+1] b[i+2] b[i+3] b[i+4] b[i+5] b[i+6] b[i+7] + + + + + + + + + c[i] c[i] c[i+1] c[i+2] c[i+3] c[i+4] c[i+5] c[i+6] c[i+7] x x x x x x x x x d[i] d[i] d[i+1] d[i+2] d[i+3] d[i+4] d[i+5] d[i+6] d[i+7] RISC Software GmbH – Johannes Kepler University Linz © 2016 22.09.2016 | 5 Vector Registers RISC Software GmbH – Johannes Kepler University Linz © 2016 22.09.2016 | 6 Vector Unit Usage (Programmers View) Use vectorized libraries Ease of use (e.g. -
The Arms Race to Trustzone
The ARMs race to TrustZone Jonathan Levin http://Technologeeks.com (C) 2016 Jonathan Levin & Technologeeks.com - Share freely, but please cite source! `whoami` • Jonathan Levin, CTO of technologeeks[.com] – Group of experts doing consulting/training on all things internal • Author of a growing family of books: – Mac OS X/iOS Internals – Android Internals (http://NewAndroidbook.com ) – *OS Internals (http://NewOSXBook.com ) (C) 2016 Jonathan Levin – Share freely, but please cite source! For more details – Technologeeks.com Plan • TrustZone – Recap of ARMv7 and ARMv8 architecture • iOS Implementation – Apple’s “WatchTower” (Kernel Patch Protector) implementation • Android Implementations – Samsung, Qualcomm, Others (C) 2016 Jonathan Levin & Technologeeks.com - Share freely, but please cite source! TrustZone & ELx (C) 2016 Jonathan Levin & Technologeeks.com - Share freely, but please cite source! TrustZone • Hardware support for a trusted execution environment • Provides a separate “secure world” 安全世界 – Self-contained operating system – Isolated from “non-secure world” • In AArch64, integrates well with Exception Levels (例外層級) – EL3 only exists in the secure world – EL2 (hypervisor) not applicable in secure world. • De facto standard for security enforcement in mobile world (C) 2016 Jonathan Levin & Technologeeks.com - Share freely, but please cite source! TrustZone Regular User mode TrustZone (Untrusted) User mode, root (Untrusted, Privileged) Kernel mode (Trusted, Privileged) Hardware (C) 2016 Jonathan Levin & Technologeeks.com - Share freely, but please cite source! Trust Zone Architecture (Aarch32) 非安全世界 安全世界 Source: ARM documentation (C) 2016 Jonathan Levin & Technologeeks.com - Share freely, but please cite source! Android uses of TrustZone • Cryptographic hardware backing (keystore, gatekeeper) – Key generation, storage and validation are all in secure world – Non secure world only gets “tokens” – Public keys accessible in non-secure world – Secret unlocking (e.g. -
MMX and SSE MMX Data Types
MMX and SSE Extensions to the instruction set for parallel SIMD operations on packed data SIMD – Single Instruction stream Multiple Data stream MMX – Multimedia Extensions SSE – Streaming SIMD Extension SSE2 – Streaming SIMD Extension 2 Designed to speed up multimedia and communication applications graphics and image processing video and audio processing speech compression and recognition 1 MMX data types MMX instructions operate on 8, 16, 32 or 64-bit integer values, packed into a 64-bit field 4 MMX data types 63 0 packed byte b7 b6 b5 b4 b3 b2 b1 b0 8 bytes packed into a 64-bit quantity packed word 4 16-bit words packed into a 63 0 w3 w2 w1 w0 64-bit quantity packed doubleword 63 0 2 32-bit doublewords packed into a dw1 dw0 64-bit quantity quadword 63 0 one 64-bit quantity qw Operates on integer values only 2 1 MMX registers Floating-point registers 8 64-bit MMX registers aliased to the x87 floating-point MM7 registers MM6 no stack-organization MM5 MM4 The 32-bit general-purouse MM3 registers (EAX, EBX, ...) can also MM2 MM1 be used for operands and adresses MM0 MMX registers can not hold memory addresses 63 0 MMX registers have two access modes 64-bit access y 64-bit memory access, transfer between MMX registers, most MMX operations 32-bit access y 32-bit memory access, transfer between MMX and general-purpose registers, some unpack operations 3 MMX operation SIMD execution performs the same operation in parallel on 2, 4 or 8 values MMX instructions perform arithmetic and logical operations in parallel on -
Compiler Auto-Vectorization with Imitation Learning
Compiler Auto-Vectorization with Imitation Learning Charith Mendis Cambridge Yang Yewen Pu MIT CSAIL MIT CSAIL MIT CSAIL [email protected] [email protected] [email protected] Saman Amarasinghe Michael Carbin MIT CSAIL MIT CSAIL [email protected] [email protected] Abstract Modern microprocessors are equipped with single instruction multiple data (SIMD) or vector instruction sets which allow compilers to exploit fine-grained data level parallelism. To exploit this parallelism, compilers employ auto-vectorization techniques to automatically convert scalar code into vector code. Larsen & Amaras- inghe (2000) first introduced superword level parallelism (SLP) based vectorization, which is a form of vectorization popularly used by compilers. Current compilers employ hand-crafted heuristics and typically only follow one SLP vectorization strategy which can be suboptimal. Recently, Mendis & Amarasinghe (2018) for- mulated the instruction packing problem of SLP vectorization by leveraging an integer linear programming (ILP) solver, achieving superior runtime performance. In this work, we explore whether it is feasible to imitate optimal decisions made by their ILP solution by fitting a graph neural network policy. We show that the learnt policy, Vemal, produces a vectorization scheme that is better than the well-tuned heuristics used by the LLVM compiler. More specifically, the learnt agent produces a vectorization strategy that has a 22.6% higher average reduction in cost compared to the LLVM compiler when measured using its own cost model, and matches the runtime performance of the ILP based solution in 5 out of 7 applications in the NAS benchmark suite. 1 Introduction Modern microprocessors have introduced single instruction multiple data (SIMD) or vector units (e.g.