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5.2 Binary Convolutional Codes Digital Communication Systems ECS 452 Asst. Prof. Dr. Prapun Suksompong [email protected] 5.2 Binary Convolutional Codes Office Hours: Check Google Calendar on the course website. Dr.Prapun’s Office: 6th floor of Sirindhralai building, 163 BKD Digital Communication Systems ECS 452 Asst. Prof. Dr. Prapun Suksompong [email protected] 5.2 Binary Convolutional Codes Introduction to Binary Convolutional Codes Binary Convolutional Codes Introduced by Elias in 1955 There, it is referred to as convolutional parity-check symbols codes. Peter Elias received Claude E. Shannon Award in 1977 IEEE Richard W. Hamming Medal in 2002 for "fundamental and pioneering contributions to information theory and its applications The encoder has memory. In other words, the encoder is a sequential circuit or a finite- state machine. Easily implemented by shift register(s). The state of the encoder is defined as the contents of its memory. 165 Binary Convolutional Codes The encoding is done on a continuous running basis rather than by blocks of k data digits. So, we use the terms bit streams or sequences for the input and output of the encoder. In theory, these sequences have infinite duration. In practice, the state of the convolutional code is periodically forced to a known state and therefore code sequences are produced in a block-wise manner. 166 Binary Convolutional Codes In general, a rate- convolutional encoder has k shift registers, one per input information bit, and n output coded bits that are given by linear combinations (over the binary field, of the contents of the registers and the input information bits. k and n are usually small. For simplicity of exposition, and for practical purposes, only rate- binary convolutional codes are considered here. k = 1. These are the most widely used binary codes. 167 (Serial-in/Serial-out) Shift Register Accept data serially: one bit at a time on a single line. Each clock pulse will move an input bit to the next FF. For example, a 1 is shown as it moves across. Example: five-bit serial-in serial-out register. FF0 FF1 FF2 FF3 FF4 Serial 1 1 1 1 1 1 Serial data D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 data input output C C C C C CLKCLK 168 Example 1: n = 2, k = 1 + + 169 Digital Communication Systems ECS 452 Asst. Prof. Dr. Prapun Suksompong [email protected] 5.2 Binary Convolutional Codes Three Graphical Representations Graphical Representations Three different but related graphical representations have been devised for the study of convolutional encoding: 1. the state diagram 2. the code tree 3. the trellis diagram 171 Ex. 1: State (Transition) Diagram The encoder behavior can be seen from the perspective of a finite state machine with its state (transition) diagram. 0/00 + 00 1/11 0/11 1/00 + 10 01 0/10 1/01 0/01 A four-state directed graph that 11 uniquely represents the input-output relation of the encoder. 1/10 172 Drawing State Diagram 00 10 01 11 + + 173 Input bit Drawing State Diagram 0 00 + 1 0 0 0 + 10 01 + 11 1 0 0 + + + 174 Corresponding Input bit output bits Drawing State Diagram 0/00 00 + 0 1/11 0 0 0 + 10 01 0 + 1 11 1 0 0 + 1 + + 175 Drawing State Diagram 0/00 00 + 1 1/11 0/11 1/00 0 0 1 + 10 01 1 + 0 11 1 0 1 + 0 + + 176 Drawing State Diagram 0/00 00 1/11 0/11 + 1/00 + 10 01 (1) (2) bs1 s2 x x 0/10 0000 0 1/01 0/01 1001 1 11 0011 1 1010 0 1/10 0101 0 + 1100 1 0110 1 1111 0 + 177 Tracing the State Diagram to Find the Outputs 0/00 00 1/11 0/11 1/00 10 01 0/10 1/01 0/01 Input 1 1 0 1 1 1 11 Output 11 01 01 00 01 10 1/10 + + 178 Directly Finding the Output + + (1) (2) bs1 s2 x x 100 1 Input 1 1 0 1 1 1 0 Output 1 1 + 1 + 179 Digital Communication Systems ECS 452 Asst. Prof. Dr. Prapun Suksompong [email protected] 5.2 Binary Convolutional Codes Code Tree and Trellis Diagram Graphical Representations Three different but related graphical representations have been devised for the study of convolutional encoding: 1. the state diagram 0/00 2. the code tree 00 1/11 0/11 3. the trellis diagram 1/00 10 01 0/10 1/01 0/01 11 1/10 182 Parts for Code Tree 0/00 00 1/11 0/11 0/11 0/00 00 00 1/00 00 01 1/11 1/00 10 01 10 10 0/10 1/01 0/01 0/01 11 0/10 01 01 10 11 1/01 11 1/10 11 1/10 Two branches initiate from each node, + the upper one for 0 and the lower one for 1. + 183 Show the coded output for any possible sequence of data digits. 0/00 Code Tree 00 0/00 00 1/11 0/00 0/11 10 00 00 0/00 00 01 00 0/10 1/11 1/00 01 10 10 1/11 10 1/01 11 0/10 0/00 01 0/01 01 Initially, we 00 0/11 10 11 00 1/01 11 1/10 always assume 0/10 01 11 that all the 1/00 10 1/11 10 contents of the 0/01 10 1/01 11 register are 0. 1/10 11 Start 00 0/00 0/11 00 00 1/11 0/10 10 01 0/10 1/00 01 10 + 1/01 11 10 0/11 1/11 0/01 00 01 1/00 10 + 1/01 11 0/01 10 1/10 11 184 1/10 11 0/00 Code Tree 00 0/00 00 1/11 10 0/00 00 0/10 01 1/11 10 1/01 11 Input 1 1 0 1 0/00 00 0/11 00 Output 11 01 01 00 0/10 01 1/00 10 1/11 10 0/01 10 1/01 11 1/10 11 Start 00 0/00 0/11 00 00 1/11 0/10 10 01 0/10 1/00 01 10 + 1/01 11 10 0/11 1/11 0/01 00 01 1/00 10 + 1/01 11 0/01 10 1/10 11 185 1/10 11 Code Trellis [Carlson & Crilly, 2009, p. 620] 0/00 0/11 00 00 00 01 1/11 1/00 Current Next 10 10 State State 0/10 01 0/01 01 00 0/00 00 10 11 1/01 1/10 11 11 10 10 01 01 11 11 1/10 + + 186 Another useful way of Towards the Trellis Diagram representing the code tree. 0/00 0/00 00 0/00 0/00 0/00 0/00 00 10 10 01 01 11 11 1/10 1/10 1/10 1/10 1/10 1/10 + + 187 Trellis Diagram 0/00 0/00 00 0/00 0/00 0/00 0/00 00 10 10 Initially, we 01 01 always assume that all the contents of the 11 11 1/10 1/10 1/10 1/10 register are 0. + Each path that traverses through the trellis represents a valid codeword. + 188 Trellis Diagram 0/00 0/00 00 0/00 0/00 0/00 0/00 00 10 10 01 01 11 11 1/10 1/10 1/10 1/10 Input 1 1 0 1 1 1 + Output 11 01 01 00 01 10 + 189 Trellis โครงลูกไม้,โครงสร้างบงตาทั ่เปี ็นช่อง,โครงสร้างสาหรํ ับปลูกไม้เล้ือย 190 Convolutional Encoder: Graphical Representations + + 0/00 00 0/00 0/00 00 1/11 10 0/00 0/00 0/00 0/00 00 00 00 1/11 0/11 0/10 01 1/11 1/00 10 1/01 11 10 01 10 Start 00 0/10 0/11 00 0/01 0/10 1/01 01 01 11 1/00 10 10 1/11 0/01 1/10 01 11 1/01 11 1/10 1/10 11 191 + The Codebook + 0/00 0/00 00 0/00 00 1/11 10 00 0/00 00 1/11 0/11 0/10 01 1/11 b b b x x x x x x 1/00 10 1 2 3 1 2 3 4 5 6 1/01 11 10 01 Start 00 0/11 0/10 00 0000 0 0 0 0 0 0/10 01 1/00 1/01 0/01 10 11 10 0010 0 0 0 1 1 1/11 0/01 01 1/01 11 1/10 1/10 11 0100 0 1 1 1 0 00 0/00 0/00 0/00 0110 0 1 1 0 1 10 1001 1 1 0 1 1 01 1011 1 1 0 0 0 1101 1 0 1 0 1 11 1/10 1111 1 0 1 1 0 192 Digital Communication Systems ECS 452 Asst. Prof. Dr. Prapun Suksompong [email protected] 5.2 Binary Convolutional Codes Introduction to Viterbi Decoding Convolutional Encoder and Decoder + d,b + Message (Stream of data) x,c Convolutional Digital Encoder Modulator Encoded stream Transmitted Signal 0 1-p 0 p Channel Binary Symmetric p 1 1 Channel with 2 0/00 (2) 0/00 (1) 3 2 0/00 (0) 2 0/00 (1) 3 3 1-p 00 0 3 3 1 3 3 10 p < 0.5 2 1 2 2 3 01 Noise & Interference 0 1 2 1 1 Received 11 1/10 (1) 1/10 (1) 1/10 (0) , Signal Channel Digital yxe Recovered Message Decoder Demodulator 194 minimum distance decoder Viterbi decoder Direct Minimum Distance Decoding Suppose = [11 01 11].
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