2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design

Proceedings

May 18th – 22nd, 2008 Opio, France

TABLE OF CONTENTS

NVSMW/ICMTD Conference Schedule/Program vi

Conference Facilities viii

Map of Hotel x

Session 1 1

E. Doller "The Evolving Role and Challenges of Non-volatile Memory in Not Available Communication and Computing Devices" for Publication

V. Lipponen "Memories in Mobile World Evolution" Not Available for Publication

B. Eitan "Will Charge Trapping Become the Not Available NVM Technology of Choice?" for Publication

Y.J. Choi "System Requirements and Memory Subsystem Evolution Not Available from System Perspective" for Publication

Session 2 3

D. Oh "Program Disturb Phenomenon by DIBL in 5 MLC NAND Flash Device"

S.-H. Bae "Characterization of Low Frequency Noise in 8 Floating Gate NAND Flash Memory"

D. Wellekens "Optimization of Al2O3 Interpoly Dielectric for 12 Embedded Flash Memory Applications"

S. Shukuri "Advantage of Floating Gate B4-Flash over Retention 16 Reliability after Cycling - Characterization by Variation of Transconductance"

W. Kwon "3-D Channel Structure Flash Having Short Channel Effect 20 Immunity and Low Random Telegraph Signal Noise"

B. Wang "Opportunities and Challenges in Multi-Times-Programmable 22 Floating-Gate Logic Non-Volatile Memories"

Y. K. Lee "2T-FN eNVM with 90 nm Logic Process for Smart Card" 26

A. Conte "A 90nm Embedded Page Flash for EEPROM Replacement 28 in System On Chip"

Session 3 31

S.-L. Wang "In-Ga-O Based Double-Heater Phase Change Memory Cell" 33

L. Goux "Evidence of the Prominent Role of the Time-Under-Melt 37 Parameter in the Reset Switching of Phase-Change Line Cells"

iii TABLE OF CONTENTS

A. Redaelli "Numerical Implementation of Low Field Resistance Drift for 39 Phase Change Memory Simulations"

F. J. Jedema "Scaling Properties of Doped Sb2Te Phase 43 Change Line Cells"

S. Lee "A Novel Programming Method to Refresh a Long-Cycled 46 Phase Change Memory Cell"

A. Chimenton "Set of Electrical Characteristic Parameters Suitable for 49 Reliability Analysis of Multimegabit Phase Change Memory Arrays" P. Zhou "Improvement of Endurance and Switching Stability of 52 Forming-Free CuxO RRAM"

R. Takemura "TMR Design Methodology for SPin-Transfer Torque 54 RAM (SPRAM) with Nonvolatile and SRAM Compatible Operations" Session 4 57

S.-T. Kang "Si Nanocrystal Split Gate Technology Optimization for 59 High Performance and Reliable Embedded Microcontroller Applications"

E. Nowak "On the Influence of Fin Corner Rounding in 61 3D Nanocrystal Flash Memories"

G. Molas "Integration of Silicon Nanocrystal Memory Arrays with 64 HfAlOx Based Interpoly Dielectric"

J. Buckley "On the Influence of Molecular Linker on Charge 68 Transfer Rate in Hybrid Molecular (Ferrocene)/Silicon Field Effect Memories"

D. Wouters Panel Discussion: "New Storage Effects for 72 Non-Volatile Memory Application"

Session 5 73

N. Akil "Low Voltage and Fast Program and Erase SONOS with 75 Thick Tunnel Oxide for Low Cost Embedded EEPROM-like Memory Applications"

N. Ogura "N-Channel Complementary Pairing in Nitride Trap Memory" 77

T. Ogura "A Highly Reliable Logic NVM "eCFlash 79 (Embedded CMOS Flash)" Utilizing Differential Sense-Latch Cell with Charge-Trapping Storage"

M. Fliesler "A 15ns 4Mb NVSRAM in 0.13u SONOS Technology" 83

G. Tempel "Influence and Comparison of Cu and Alu Metallization 87 Schemes on Endurance of Embedded Flash Memories"

iv TABLE OF CONTENTS Y. Roizin "C-Flash: An Ultra-Low Power Single Poly Logic NVM" 90

J. R. Power "Improved Retention for a Al2O3 IPD Embedded Flash Cell 93 without Top-Oxide"

G. Fukano "A 65nm 1Mb SRAM Macro with Dynamic Voltage Scaling in 97 Dual Power Supply Scheme for Low Power SoCs"

Session 6 99

S.-C. Lai "An Oxide-Buffered BE-MANOS Charge-Trapping Device and 101 the Role of Al2O3"

S. Sakai "Highly Scalable Fe(Ferroelectric)-NAND Cell with 103 MFIS (Metal-Ferroelectric-Insulator-Semiconductor) Structure for Sub-10nm Tera-Bit Capacity NAND Flash Memories"

C. Jahan "Performance Enhancement in Ultra-Scaled SONOS FinFlash 106 by Inclusion of High-k Dielectric in the Gate Stack"

C. H. Lee "Numerical Simulation of Programming Transient 109 Behavior in Charge Trapping Storage Memory"

P. Mazoyer Panel discussion on “Emerging Solutions” 111

Session 7 113

T.-H. Hsu "A Study of Sub-40nm FinFET BE-SONOS NAND Flash" 115

S. I. Chang "Reliability Characteristics of TANOS (TaN/AlO/SiN/Oxide/Si) 117 NAND Flash Memory with Rounded Corner (RC) Structure"

H.-T. Lue "Study of Charge Trapping Vertical Location and Capture 119 Efficiency of SONOS-Type Devices by Gate-Sensing and Channel-Sensing (GSCS) Method"

M. F. Beug "Anomalous Erase Behavior in 121 Charge Trapping Memory Cells"

I. C. Yang "The Impact of Interference on Multi-Level-Cell Applications in 124 Scaled Nitride-Storage Flash Memory"

L. Breuil "Improvement of TANOS NAND Flash Performance by the 126 Optimization of a Sealing Layer"

G. Van den bosch "Nitride Engineering for Improved Erase Performance and 128 Retention of TANOS NAND Flash Memory"

T. Melde "Nitride Thickness Scaling Limitations in 130 TANOS Charge Trapping Devices"

Author Index 133

Notes 137

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